summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/sun9i-a80.dtsi
Commit message (Collapse)AuthorAgeFilesLines
* ARM: dts: sun9i: Add pinmux settings for LCD0 RGB888 output.Chen-Yu Tsai2018-03-191-0/+11
| | | | | | | | The A80 supports RGB888 with H/V sync from LCD0. Add a pinmux setting for the needed pins. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun9i: Add device nodes for documented display pipelines for A80Chen-Yu Tsai2018-03-191-0/+381
| | | | | | | | | | | | | | | | | | | | | | | The Allwinner A80 SoC has 3 display pipelines, of which some parts are documented: - 3x display front ends (FE), documented - 2x display enhancement units (DEU), undocumented - 3x display back ends (BE), documented - 2x dynamic range controller (DRC), undocumented - 2x LCDC/TCONs, documented - 1x LCDC/TCON, undocumented, and probably not useable - 1x HDMI transmitter, undocumented but DesignWare compatible - 1x MERGE block, function unknown This patch adds device nodes for the first 2 documented pipelines: FE0 - DEU0 - - BE0 - DRC0 - TCON0 x FE1 - DEU1 - - BE1 - DRC1 - TCON1 Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun9i: Add enable-method for SMP support for the A80 SoCChen-Yu Tsai2018-03-101-0/+8
| | | | | | | | | | | | Using the enable-method property for SMP support would allow future PSCI implementations to override any in-OS support. This is better than just matching against the machine compatible, and then having to determine whether other methods are available or not. This adds enable-method properties to all CPU nodes. Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Add secure SRAM node used for SMP hotplugChen-Yu Tsai2018-02-161-0/+19
| | | | | | | | | The A80 stores some magic flags in a portion of the secure SRAM. The BROM jumps directly to the software entry point set by the SMP code if the flags are set. This is required for CPU0 hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Add PRCM device node for the A80 dtsiChen-Yu Tsai2018-02-161-0/+5
| | | | | | | | | | The PRCM is a collection of clock controls, reset controls, and various power switches/gates. Some of these can be independently listed and supported, while a number of CPU related ones are used in tandem with CPUCFG for SMP bringup and CPU hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Add CPUCFG device node for A80 dtsiChen-Yu Tsai2018-02-161-0/+5
| | | | | | | | | | | CPUCFG is a collection of registers that are mapped to the SoC's signals from each individual processor core and associated peripherals, such as resets for processors, L1/L2 cache and other things. These registers are used for SMP bringup and CPU hotplugging. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Add CCI-400 device nodes for A80Chen-Yu Tsai2018-02-161-0/+46
| | | | | | | | | | | The A80 includes an ARM CCI-400 interconnect to support multi-cluster CPU caches. Also add the maximum clock frequency for the CPUs, as listed in the A80 Optimus Board FEX file. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Change node names to remove underscoresMaxime Ripard2017-10-131-5/+5
| | | | | | | Some node names in the A80 DTSI still have underscores in them. Remove them in favour of hyphens to remove DTC warnings. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Rename pinctrl nodes to avoid warningsMaxime Ripard2017-10-061-6/+6
| | | | | | | | Our pinctrl node names were containing unit-adresses without a reg property, resulting in a warning. Change the names for our new convention. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Remove skeleton to avoid warningsMaxime Ripard2017-10-061-7/+2
| | | | | | | | | Using skeleton.dtsi will create a memory node that will generate a warning in DTC. However, that node will be created by the bootloader, so we can just remove it entirely in order to remove that warning. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove leading zeros from unit-addressesMaxime Ripard2017-10-061-43/+43
| | | | | | | | | | Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-2/+0
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-02-251-297/+107
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
| * ARM: dts: sun9i: Switch to new clock bindingsChen-Yu Tsai2017-01-301-297/+107
| | | | | | | | | | | | | | Now that we have a full clock driver for sun9i, switch to it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge tag 'sunxi-dt-for-4.11' of ↵Arnd Bergmann2017-02-071-0/+3
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT changes for 4.11" from Maxime Ripard: The usual chunk of DT changes, most notably: - Support for the H2+ and the V3s - CPUFreq support for the A33 - SPDIF support for the A31 and H3 - New boards: Beelink X2, Lichee Pi One, Lichee Pi Zero, Orange Pi Zero * tag 'sunxi-dt-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (42 commits) ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB ARM: sun8i: sina33: Enable display ARM: sun8i: a23/a33: Add the oscillators accuracy ARM: sun8i: a23/a33: Enable the real LOSC and use it ARM: dts: sunxi: add support for Lichee Pi Zero board ARM: dts: sunxi: add dtsi file for V3s SoC ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode ARM: dts: sun8i: reference-design: use AXP223 DTSI ARM: dts: sun8i: parrot: use AXP223 DTSI ARM: dts: sun8i: sina33: use AXP223 DTSI ARM: dts: sun8i: a33-olinuxino: use AXP223 DTSI ARM: dts: add DTSI for AXP223 dt-bindings: power: axp20x-usb: add axp223 compatible ARM: dts: sun7i: Add wifi dt node on Banana Pro ARM: dts: sun6i: Add SPDIF to the Mele I7 devicetree: bindings: Add vendor prefix for Shenzhen Xunlong Software ARM: dts: sun8i-h3: orange-pi-pc: Enable audio codec ...
| * | ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai2017-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | ARM: DTS: Fix register map for virt-capable GICMarc Zyngier2017-02-071-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-25/+25
| | | | | | | | | | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-4/+0
|/ | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard2016-11-221-2/+4
| | | | | | | | | The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun9i: Add mmc1 pinmux settingChen-Yu Tsai2016-11-221-0/+8
| | | | | | | | On the A80, mmc1 is available on pingroup G. Designs mostly use this to connect to an SDIO WiFi chip. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add missing #interrupt-cells to R_PIO pinctrl device nodeChen-Yu Tsai2016-08-271-2/+1
| | | | | | | | | | | | | The R_PIO device node is missing #interrupt-cells, which causes interrupt parsing to fail to match it as a valid interrupt controller. Add #interrupt-cells to it. Also remove the unnecesary #address-cells and #size-cells. Fixes: 1ac56a6da9e1 ("ARM: dts: sun9i: Add A80 R_PIO pin controller device node") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Switch to the AC100 RTC clock outputs for osc32kChen-Yu Tsai2016-08-221-6/+5
| | | | | | | | | | | The 32.768 kHz clock inside the A80 SoC is fed from an external source, typically the AC100 RTC module. Make the osc32k placeholder a fixed-factor clock so board dts files can specify its source. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Include SDC2_RST pin in mmc2_8bit_pinsChen-Yu Tsai2016-01-251-1/+2
| | | | | | | | mmc2_8bit_pins is used with eMMC chips, which also have a reset pin. The MMC controller also has a reset output that is supported. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Use sun9i specific mmc compatibleChen-Yu Tsai2016-01-251-4/+4
| | | | | | | | | | sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA trigger levels can be increased. Also, the mmc module clock parent has a higher clock rate, and the sample and output delay phases are different. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add NMI controller device nodeChen-Yu Tsai2015-12-031-0/+8
| | | | | | | | | | The Allwinner A80 SoC has an NMI controller. NMI is an external interrupt pin exclusely used with PMICs and other system critical peripherals (such as RTC) in Allwinner's reference designs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add Reduced Serial Bus controller device node to A80 dtsiChen-Yu Tsai2015-12-011-0/+21
| | | | | | | | | | | This patch adds a device node for the Reduced Serial Bus (RSB) controller and the defacto pinmux setting to the A80 dtsi. Since there is only one possible pinmux setting for RSB, just set it in the dtsi. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add consumer IR receiver device node and pinmux settingsChen-Yu Tsai2015-12-011-0/+19
| | | | | | | | The Allwinner A80 SoC has a consumer IR receiver, which is the same as older SoCs. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add A80 R_PIO pin controller device nodeChen-Yu Tsai2015-12-011-0/+14
| | | | | | | The A80 has a secondary pin controller. Add a device node for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add TODO comments for the main and low power clocksChen-Yu Tsai2015-12-011-0/+18
| | | | | | | | | The main (24MHz) clock on the A80 is configurable via the PRCM address space. The low power/speed (32kHz) clock is from an external chip, the AC100. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add A80 PRCM clocks and reset control nodesChen-Yu Tsai2015-12-011-1/+78
| | | | | | | | | | This adds the supported PRCM clocks and reset controls to the A80 dtsi. The DAUDIO module clocks are not supported yet. Also update clock and reset phandles for r_uart. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Fix interrupt-cells for [r]pio on A23/A31/A33/A80Hans de Goede2015-10-171-1/+1
| | | | | | | | | When the gpio interrupt bindings where changed to add a bank to the specifier list, the r_pio nodes of A23/A31/A33 where not updated to match and neither was the pio node of the A80, this fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun9i: Wrap the clock-indicesMaxime Ripard2015-08-121-10/+22
| | | | | | | | Wrap the clock-indices to match the wrapping of the clock-output-names in order to make it easier to match indices to names. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: dts: sun9i: Add device node for watchdogChen-Yu Tsai2015-06-011-0/+6
| | | | | | | | | | | | | On A80 there are 2 watchdogs, one in the main block, and one in the R (special) block. We do not have information on the R block watchdog, other than the register layout is the same, and the interrupt number. Both are able to reset the whole system. Add the main watchdog, in case the R block is used for special purposes like running an RTOS. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard2015-05-101-1/+1
| | | | | | | | | A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Remove the FSF addressMaxime Ripard2015-05-101-5/+0
| | | | | | | | | | The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Enable ARM architected timer on A80Chen-Yu Tsai2015-04-271-0/+10
| | | | | | | | The A80 SoC has the architected timer, but the existing firmware from Allwinner does not set CNTFRQ at all. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede2015-04-271-0/+8
| | | | | | | | | | | | | | Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add USB host controller nodes to a80 dtsiChen-Yu Tsai2015-04-271-0/+55
| | | | | | | The A80 has 3 EHCI/OHCI USB controllers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add usb phy nodes to a80 dtsiChen-Yu Tsai2015-04-271-0/+37
| | | | | | | | On sun9i, there are 3 independent usb phys for EHCI/OHCI. Add device nodes for them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun9i: Add usb clock nodes to a80 dtsiChen-Yu Tsai2015-04-271-0/+22
| | | | | | | | The USB controller and phy clocks and resets have a separate address block and driver. Add the nodes to represent them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'dt-for-linus' of ↵Linus Torvalds2015-02-171-32/+160
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
| * ARM: dts: sun9i: Add 8 bit mmc pinmux setting for mmc2Chen-Yu Tsai2015-01-211-0/+9
| | | | | | | | | | | | | | | | mmc2 is available on port C. Add a pinmux setting for 8 bit wide eMMC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun9i: Add mmc controller nodes to the A80 dtsiChen-Yu Tsai2015-01-211-0/+48
| | | | | | | | | | | | | | | | The A80 has 4 mmc controllers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun9i: Add mmc config clock nodesChen-Yu Tsai2015-01-211-0/+13
| | | | | | | | | | | | | | Add the device tree nodes for the mmc config clock nodes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun9i: Add pinmux setting for mmc0Chen-Yu Tsai2015-01-211-0/+8
| | | | | | | | | | | | | | | | | | mmc0 is only available on port F, and is always used with a 4 bit wide bus for the onboard micro-sd slot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun9i: Add clock-indices property for bus gate clocksChen-Yu Tsai2015-01-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | of_clk_get_parent_name() uses the clock-indices property to resolve clock phandle arguments in case that the argument index does not match the clock-output-names sequence. This is the case on sunxi, where we use the actual bit index as the argument to the phandle. Add the clock-indices property so that of_clk_get_parent_name() resolves the names correctly. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun9i: Add mmc module clock nodes for A80Chen-Yu Tsai2015-01-211-0/+36
| | | | | | | | | | | | | | | | The mmc module clocks are A80 specific module 0 (storage) type clocks. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: sunxi: DT: Convert the DTs to use the GIC headersMaxime Ripard2015-01-211-25/+27
| | | | | | | | | | | | | | | | The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
OpenPOWER on IntegriCloud