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* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-09-011-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
| * ARM: sunxi: dt: Convert users to the PIO interrupts bindingMaxime Ripard2015-07-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: sun7i: Add USB Dual Role ControllerRoman Byshko2015-07-061-0/+13
| | | | | | | | | | | | | | Add a node for the otg/drc usb controller to sun7i-a20.dtsi Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds2015-08-311-0/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.3: API: - the AEAD interface transition is now complete. - add top-level skcipher interface. Drivers: - x86-64 acceleration for chacha20/poly1305. - add sunxi-ss Allwinner Security System crypto accelerator. - add RSA algorithm to qat driver. - add SRIOV support to qat driver. - add LS1021A support to caam. - add i.MX6 support to caam" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (163 commits) crypto: algif_aead - fix for multiple operations on AF_ALG sockets crypto: qat - enable legacy VFs MPI: Fix mpi_read_buffer crypto: qat - silence a static checker warning crypto: vmx - Fixing opcode issue crypto: caam - Use the preferred style for memory allocations crypto: caam - Propagate the real error code in caam_probe crypto: caam - Fix the error handling in caam_probe crypto: caam - fix writing to JQCR_MS when using service interface crypto: hash - Add AHASH_REQUEST_ON_STACK crypto: testmgr - Use new skcipher interface crypto: skcipher - Add top-level skcipher interface crypto: cmac - allow usage in FIPS mode crypto: sahara - Use dmam_alloc_coherent crypto: caam - Add support for LS1021A crypto: qat - Don't move data inside output buffer crypto: vmx - Fixing GHASH Key issue on little endian crypto: vmx - Fixing AES-CTR counter bug crypto: null - Add missing Kconfig tristate for NULL2 crypto: nx - Add forward declaration for struct crypto_aead ...
| * | ARM: sun7i: dt: Add Security System to A20 SoC DTSLABBE Corentin2015-07-201-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on many Allwinner SoC. This patch enable the Security System on the Allwinner A20 SoC Device-tree. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
* | ARM: sun7i: Add clock indicesMaxime Ripard2015-08-121-0/+23
|/ | | | | | | | The A20 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: dts: sun7i: Add A20 SRAM and SRAM controllerMaxime Ripard2015-06-011-0/+37
| | | | | | | | | | | | | The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
* ARM: dts: sunxi: Revert SRAM controller drivers patchesMaxime Ripard2015-06-011-34/+0
| | | | | | | | | | | | This patch reverts commit ccb4ada2f193 ("ARM: dts: sun7i: Add A20 SRAM and SRAM controller"), commit e6f51e4bd2a5 ("ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controller") and commit 6d92b80f356f ("ARM: dts: sun4i: Add A10 SRAM and SRAM controller"). The bindings have been changed in the SRAM driver, and we need to change the DT accordingly. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add uart4_pins_b definitionMichael Ring2015-06-011-0/+7
| | | | | | | | | Some boards (e.g. the BananaPro) use alternative pins for uart4, add a pinmux entry for these. Signed-off-by: Michael Ring <mail@michael-ring.org> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Split the SPI pinctrl groupsMaxime Ripard2015-05-101-4/+39
| | | | | | | | | | | | | | | | | | | The pinctrl groups for SPI until now were also adding the chip selects in the SPI pinctrl group. This was causing a few issues, since a board was forced to use a random number of chipselects, even though it might use one of these chip selects for another pin. The number of chipselects defined was also not the same from one group to another because of different needs at the time these groups have been introduced, resulting in no clear view from the board DTS on what exactly is being muxed, which even might change in the future. Solve this by creating different pinctrl groups for the chipselects and the standard SPI pins (CLK, MOSI and MISO) so that we fix both issues. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Fix whitespace errorsMaxime Ripard2015-05-101-9/+9
| | | | | | | | | A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard2015-05-101-14/+27
| | | | | | | | | A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Remove the FSF addressMaxime Ripard2015-05-101-5/+0
| | | | | | | | | | The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dts: split IR pins for A10 and A20Marcus Cooper2015-05-021-4/+18
| | | | | | | | | | Currently none of the target boards nor the driver supports IR TX. However this pin is used in a few instances as a GPIO. Split the pin ctrl descriptions so that only the IR RX is configured to be used. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Update ahb clocks for sun5i and sun7iChen-Yu Tsai2015-04-271-3/+10
| | | | | | | | | | | | | | | The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add A20 SRAM and SRAM controllerMaxime Ripard2015-04-271-0/+34
| | | | | | | | | | | | | | The A20 has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [hdegoede@redhat.com: Do not change soc node name, change compatible to sun4i-a10-sram-controller to match the driver change] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede2015-04-271-0/+8
| | | | | | | | | | | | | | Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and laterHans de Goede2015-04-271-1/+1
| | | | | | | | | | The touchscreen controller in the A13 and later has a different temperature curve than the one in the original A10, change the compatible for the A13 and later so that the kernel will use the correct curve. Reported-by: Tong Zhang <lovewilliam@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove overclocked/overvoltaged OPPChen-Yu Tsai2015-03-241-2/+1
| | | | | | | | | | | | | | Without proper regulator support for individual boards, it is dangerous to have overclocked/overvoltaged OPPs in the list. Cpufreq will increase the frequency without the accompanying voltage increase, resulting in an unstable system. Remove them for now. We can revisit them with the new version of OPP bindings, which support boost settings and frequency ranges, among other things. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-211-20/+52
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * Merge branch 'clk-next' into v3.19-rc7Michael Turquette2015-02-021-20/+52
| |\
| | * ARM: sunxi: dt: Add sample and output mmc clocksMaxime Ripard2015-01-141-20/+52
| | | | | | | | | | | | | | | | | | | | | | | | Add the sample and output clocks for the MMC phase support. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
* | | Merge tag 'dt-for-linus' of ↵Linus Torvalds2015-02-171-117/+230
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
| * | ARM: sunxi: dts: Add A10/A20 PS2 pin muxing optionsVishnu Patekar2015-01-251-0/+14
| | | | | | | | | | | | | | | Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: dts: Add PS2 nodes to dtsi for A10,A20Vishnu Patekar2015-01-251-0/+16
| | | | | | | | | | | | | | | | | | Signed-off-by: VishnuPatekar <vishnupatekar0510@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sunxi: Add missing mdio labelAleksei Mamlin2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | This patch add missing mdio label for sun[457]i. Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun7i: Add cpu thermal zones to dtsiChen-Yu Tsai2015-01-211-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sunxi: Add simplefb nodes for de_be0-lcd0, de_be0-lcd0-tve0 pipelinesHans de Goede2015-01-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0" display pipelines for when u-boot has set up a pipeline to drive a LCD panel / VGA output rather then the HDMI output. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun7i: Add cpu clock reference and operating points to dtsiChen-Yu Tsai2015-01-211-1/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the A20 FEX files in the sunxi-boards repository. Not all boards have the same settings. The settings in this patch are the most generic ones. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sunxi: Enable thermal sensor support for RTP on sun[457]iChen-Yu Tsai2015-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the resistive touchpanel driver supports thermal sensors, add the "#thermal-sensor-cells" property as required by the thermal framework. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Eduardo Valentin <edubezval@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert the DTs to use the GIC headersMaxime Ripard2015-01-211-53/+55
| | | | | | | | | | | | | | | | | | | | | | | | The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodesMaxime Ripard2015-01-211-58/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert the DTs to use a header for the DMA argumentsMaxime Ripard2015-01-211-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA engine for the A10/A20 and derivatives require an opaque extra argument. Add a dt-bindings header, and convert the device trees to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert to device tree includesMaxime Ripard2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | Prepare the device trees to use the C preprocessor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun7i: Add lradc nodeHans de Goede2015-01-211-0/+7
| |/ | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: dt: Fix aliasesMaxime Ripard2015-01-251-8/+0
|/ | | | | | | | | | Commit f77d55a3b56a ("serial: 8250_dw: get index of serial line from DT aliases") made the serial driver now use the serial aliases to get the tty number, pointing out that our aliases have been wrong all along. Remove them from the DTSI and add custom ones in the relevant boards. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-201-10/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * ARM: dts: sunxi: unify APB1 clockEmilio López2014-11-231-10/+2
| | | | | | | | | | | | | | | | | | | | With the new factors infrastructure in place, we can unify apb1 and apb1_mux as a single clock now. Signed-off-by: Emilio López <emilio@elopez.com.ar> [wens@csie.org: Change apb1 node label to "apb1"; reword commit title] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sunxi: Update simplefb nodes so that u-boot can find themHans de Goede2014-11-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Review of the u-boot sunxi simplefb patches has led to the decision that u-boot should not use a specific path to find the nodes as this goes contrary to how devicetree usually works. Instead a platform specific compatible + properties should be used for this. The simplefb bindings have already been updated to reflect this, this patch brings the sunxi devicetree files in line with the new binding, and the actual u-boot implementation as it is going upstream. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sunxi: Add de_be0 clk parent pll to simplefb nodeHans de Goede2014-11-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Avoid the parent pll for the mod-clk for de_be0 getting disabled when non of the other users are enabled (which can happen when none of i2c, spi and mmc are in use). Note for now we point directly to the parent rather then to the de_be0 mod-clk as that is not modelled in our devicetree yet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun7i: Add simplefb nodeHans de Goede2014-11-231-0/+12
| | | | | | | | | | | | | | Add a simplefb template node for u-boot to further fill and activate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun7i: dtsi: add support for usbphy0Roman Byshko2014-11-231-2/+2
| | | | | | | | | | Signed-off-by: Roman Byshko <rbyshko@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: Fix GPLv2 wordingMaxime Ripard2014-11-231-3/+3
| | | | | | | | | | | | | | | | | | During the GPL to GPL/X11 licensing migration, the GPL notice introduced mentionned the device trees as a library, which is not really accurate. It began to spread by copy and paste. Fix all these library mentions to reflect the file that it's actually just a file. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun7i: Add mmc2_pins_a pinctrl definitionHans de Goede2014-11-231-0/+7
| | | | | | | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun7i: Add uart3_pins_b pinctrl settingHans de Goede2014-11-231-0/+7
| | | | | | | | | | | | | | | | The uart3_pins_a multiplexes the uart3 pins to port G, add a pinctrl entry for mapping them to port H (as used on the Bananapi). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun7i: Add spi0_pins_a pinctrl settingHans de Goede2014-11-231-0/+7
|/ | | | | Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.18' of ↵Linus Torvalds2014-10-151-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock tree updates from Mike Turquette: "The clk tree changes for 3.18 are dominated by clock drivers. Mostly fixes and enhancements to existing drivers as well as new drivers. This tag contains a bit more arch code than I usually take due to some OMAP2+ changes. Additionally it contains the restart notifier handlers which are merged as a dependency into several trees. The PXA changes are the only messy part. Due to having a stable tree I had to revert one patch and follow up with one more fix near the tip of this tag. Some dead code is introduced but it will soon become live code after 3.18-rc1 is released as the rest of the PXA family is converted over to the common clock framework. Another trend in this tag is that multiple vendors have started to push the complexity of changing their CPU frequency into the clock driver, whereas this used to be done in CPUfreq drivers. Changes to the clk core include a generic gpio-clock type and a clk_set_phase() function added to the top-level clk.h api. Due to some confusion on the fbdev mailing list the kernel boot parameters documentation was updated to further explain the clk_ignore_unused parameter, which is often required by users of the simplefb driver. Finally some fixes to the locking around the clock debugfs stuff was done to prevent deadlocks when interacting with other subsystems." * tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux: (99 commits) clk: pxa clocks build system fix Revert "arm: pxa: Transition pxa27x to clk framework" clk: samsung: register restart handlers for s3c2412 and s3c2443 clk: rockchip: add restart handler clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate doc/kernel-parameters.txt: clarify clk_ignore_unused arm: pxa: Transition pxa27x to clk framework dts: add devicetree bindings for pxa27x clocks clk: add pxa27x clock drivers arm: pxa: add clock pll selection bits clk: dts: document pxa clock binding clk: add pxa clocks infrastructure clk: gpio-gate: Ensure gpiod_ APIs are prototyped clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe clk: ti: LLVMLinux: Move __init outside of type definition clk: ti: consider the fact that of_clk_get() might return an error clk: ti: dra7-atl-clock: fix a memory leak clk: ti: change clock init to use generic of_clk_init clk: hix5hd2: add I2C clocks clk: hix5hd2: add watchdog0 clocks ...
| * ARM: sunxi: dt: Switch to the new mbus compatibleMaxime Ripard2014-09-271-1/+1
| | | | | | | | | | | | | | Now that we have a compatible of its own for the mbus clock, switch to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sun7i: Relicense the A20 DTSI under GPLv2/X11Maxime Ripard2014-09-071-5/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Alexander Bersenev <bay@hackerdom.ru> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Carlo Caione <carlo@caione.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Emilio López <emilio@elopez.com.ar> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Oliver Schinagl <oliver@schinagl.nl> Acked-by: Roman Byshko <rbyshko@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* | ARM: dts: sun7i: Add uart3/4/5, i2c3 and spi2 pinmuxWills Wang2014-08-191-0/+35
| | | | | | | | | | | | | | | | This patch add generic dts node for uart3/4/5, i2c3 and spi2. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Wills Wang <wills.wang.open@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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