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* ARM: dts: sun7i: Add Mali nodeGiulio Benetti2018-02-151-0/+25
| | | | | | | The A20 has an ARM Mali 400 GPU, so add binding to our DT. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun[4-7]i: Remove "cooling-{min|max}-level" for CPU nodesViresh Kumar2018-02-131-2/+0
| | | | | | | | | | | | The "cooling-min-level" and "cooling-max-level" properties are not parsed by any part of the kernel currently and the max cooling state of a CPU cooling device is found by referring to the cpufreq table instead. Remove the unused properties from the CPU nodes. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun7i: include correct ccu clock headerGiulio Benetti2018-02-131-1/+1
| | | | | | | | | | Including sun4i header instead of sun7i prevents using sun7i specific defines. Substitute header inclusion in sun7i-a20.dtsi using right one. Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun[47]i: Fix display backend 1 output to TCON0 remote endpointChen-Yu Tsai2018-01-061-1/+1
| | | | | | | | | | | | | | | There is a copy-paste error in the display pipeline device tree graph. The remote endpoint of the display backend 1's output to TCON0 points to the wrong endpoint. This will result in the driver incorrectly parsing the relationship of the components. Reported-by: Andrea Venturi <ennesimamail.av@gmail.com> Fixes: 0df4cf33a594 ("ARM: dts: sun4i: Add device nodes for display pipelines") Fixes: 5b92b29bed45 ("ARM: dts: sun7i: Add device nodes for display pipelines") Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Convert to CCU index macros for HDMI controllerChen-Yu Tsai2017-12-051-2/+2
| | | | | | | | | | | | When the HDMI controller device node was added, the needed PLL clock macros were not exported. A separate patch addresses that, but it is merged through a different tree. Now that both patches are in mainline proper, we can convert the raw numbers to proper macros. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-dt-for-4.15' of ↵Arnd Bergmann2017-10-301-632/+391
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Pull "Allwinner DT changes for 4.15" from Maxime Ripard: The most notable changes are: - Conversion to the last SoC (A10, A20) to the new clock framework - HDMI and dual pipeline support for the A10, A20 and A31 DRM driver - Support for the various power supplies on a number of boards - Fix of DTC warnings on a number of SoCs, but most of them still need some work - New boards: A20-OLinuXino-MICRO-eMMC, TBS A711, Banana Pi M2 Berry, Banana Pi M2 Ultra - New R40 SoC support * tag 'sunxi-dt-for-4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (63 commits) ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: r40: add USB host port nodes for R40 ARM: dts: sun4i: Enable HDMI support on some A10 devices ARM: dts: sun7i: Enable HDMI support on some A20 devices ARM: dts: sun7i: Add device nodes for display pipelines ARM: dts: sun4i: Add device nodes for display pipelines ARM: dts: sun8i: r40: add watchdog device node ARM: dts: sun5i: reference-design-tablet: Enable AXP209 AC and battery ARM: dts: sun9i: Change node names to remove underscores ARM: dts: sun9i: Change node names to remove underscores ARM: dts: sun4i: Remove underscores from nodes names ARM: dts: sun4i: Provide default muxing for relevant controllers ARM: dts: sun4i: Change pinctrl nodes to avoid warning ARM: dts: sun6i: Enable HDMI support on some A31/A31s devices ARM: dts: sun6i: Add device node for HDMI controller ARM: dts: sun4i: Change LRADC node names to avoid warnings ARM: dts: sun4i: Remove skeleton and memory to avoid warnings ARM: dts: sun4i: Remove gpio-keys warnings ...
| * ARM: dts: sun7i: Add device nodes for display pipelinesJonathan Liu2017-10-181-0/+307
| | | | | | | | | | | | | | | | | | | | | | | | The A20 has two interconnected display pipelines, mirroring the A10. Add all the device nodes for them, including the downstream HDMI controller that we already support. Signed-off-by: Jonathan Liu <net147@gmail.com> [wens@csie.org: Squashed in HDMI and provided commit message] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sunxi: Remove leading zeros from unit-addressesMaxime Ripard2017-10-061-61/+61
| | | | | | | | | | | | | | | | | | | | Most of our device trees have had leading zeros for padding as part of the nodes unit-addresses. Remove all these useless zeros that generate warnings Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun7i: Convert to CCUPriit Laes2017-09-171-635/+86
| | | | | | | | | | | | | | | | | | Convert sun7i-a20.dtsi to new CCU driver. Tested on Cubietruck. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | arm: dts: fix unit-address leading 0sRob Herring2017-10-201-114/+114
|/ | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: dts: sunxi: add SoC specific compatibles for the crypto nodesAntoine Tenart2017-06-071-1/+2
| | | | | | | | Add SoC specific compatibles for all sunXi crypto nodes, in addition to the one already used (allwinner,sun4i-a10-crypto). Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux settingChen-Yu Tsai2017-05-141-6/+0
| | | | | | | | | | As part of our effort to move pinctrl/GPIO interlocking into the driver where it belongs, this patch drops the definition and usage of the mmc0_cd_pin_reference_design pinmux setting for the default mmc0 card detect GPIO pin. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: fix device node orderingPatrick Menschel2017-04-051-15/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the device node position of ps20 and ps21 to fix ordering by rising physical address. From uart7: serial@01c29c00 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 ps20: ps2@01c2a000 ps21: ps2@01c2a400 to uart7: serial@01c29c00 ps20: ps2@01c2a000 ps21: ps2@01c2a400 i2c0: i2c@01c2ac00 i2c1: i2c@01c2b000 i2c2: i2c@01c2b400 i2c3: i2c@01c2b800 i2c4: i2c@01c2c000 gmac: ethernet@01c50000 hstimer@01c60000 gic: interrupt-controller@01c81000 Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add can0_pins_a pinctrl settingsPatrick Menschel2017-04-041-0/+5
| | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the pinctrl settings for pins PH20 and PH21. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add CAN nodePatrick Menschel2017-04-041-0/+9
| | | | | | | | | | | | | The A20 SoC has an on-board CAN controller. This patch adds the device node. The CAN controller is inherited from the A10 SoC and uses the same driver. This patch is adapted from the description in Documentation/devicetree/bindings/net/can/sun4i_can.txt Signed-off-by: Patrick Menschel <menschel.p@posteo.de> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-1/+0
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-dt-for-4.11' of ↵Arnd Bergmann2017-02-071-0/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT changes for 4.11" from Maxime Ripard: The usual chunk of DT changes, most notably: - Support for the H2+ and the V3s - CPUFreq support for the A33 - SPDIF support for the A31 and H3 - New boards: Beelink X2, Lichee Pi One, Lichee Pi Zero, Orange Pi Zero * tag 'sunxi-dt-for-4.11' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (42 commits) ARM: dts: sun8i-h3: Add SPDIF to the Beelink X2 ARM: dts: sun8i-h3: Add the SPDIF block to the H3 ARM: dts: sun8i-h3: Add SPDIF TX pin to the H3 ARM: dts: sun8i-h3: Add dts for the Beelink X2 STB ARM: sun8i: sina33: Enable display ARM: sun8i: a23/a33: Add the oscillators accuracy ARM: sun8i: a23/a33: Enable the real LOSC and use it ARM: dts: sunxi: add support for Lichee Pi Zero board ARM: dts: sunxi: add dtsi file for V3s SoC ARM: dts: sun6i: sina31s: Enable USB OTG controller in peripheral mode ARM: dts: sun8i: reference-design: use AXP223 DTSI ARM: dts: sun8i: parrot: use AXP223 DTSI ARM: dts: sun8i: sina33: use AXP223 DTSI ARM: dts: sun8i: a33-olinuxino: use AXP223 DTSI ARM: dts: add DTSI for AXP223 dt-bindings: power: axp20x-usb: add axp223 compatible ARM: dts: sun7i: Add wifi dt node on Banana Pro ARM: dts: sun6i: Add SPDIF to the Mele I7 devicetree: bindings: Add vendor prefix for Shenzhen Xunlong Software ARM: dts: sun8i-h3: orange-pi-pc: Enable audio codec ...
| * ARM: dts: sunxi: Add num-cs for A20 spi nodesEmmanuel Vadot2017-01-101-0/+4
| | | | | | | | | | | | | | | | | | | | | | The spi0 controller on the A20 have up to 4 CS (Chip Select) while the others three only have 1. Add the num-cs property to each node. The current driver doesn't read this property but this is useful for downstream user of DTS (FreeBSD for example). Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai2017-01-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: DTS: Fix register map for virt-capable GICMarc Zyngier2017-02-071-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo <shawnguo@kernel.org> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Acked-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-102/+102
| | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-37/+0
| | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-36/+0
| | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard2016-11-221-1/+2
| | | | | | | | | The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sunxi: Use new sun7i-a20-mmc compatible on sun7i and newerHans de Goede2016-09-261-4/+4
| | | | | | | | | Use the new sun7i-a20-mmc compatible for the mmc controllers on sun7i and newer. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* ARM: sun7i: Add DAI nodesMaxime Ripard2016-07-041-0/+39
| | | | | | Add the new DAI blocks to the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: Add mod1 clock nodesEmilio López2016-07-041-2/+46
| | | | | | | | This commit adds all the mod1 clocks available on A20 to its device tree. This list was created by looking at the A20 user manual. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add NFC node to Allwinner A20 SoCBoris Brezillon2016-07-041-0/+13
| | | | | | | | Add NAND Flash controller node definition to the A20 SoC. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Re-order pinctrl nodes alphabeticallyAleksei Mamlin2016-07-041-142/+142
| | | | | | | No functional change. Re-order sun7i pinctrl nodes alphabetically. Signed-off-by: Aleksei Mamlin <mamlinav@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: HDMI and the tv-encoder use tcon ch1 not ch0Hans de Goede2016-07-041-4/+6
| | | | | | | | | | | Update the simplefb nodes for hdmi / tv-encoder out to point to tcon0_ch1 instead of tcon0_ch0 as tcon clock. While at it fix the clocks lines being longer than 80 chars. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: A20: Add display and TCON clocksPriit Laes2016-07-041-7/+81
| | | | | | | | Enable the display and TCON clocks that are needed to drive the display engine, tcon and TV encoders. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Fix pll3x2 and pll7x2 not having a parent clockHans de Goede2016-06-291-0/+2
| | | | | | | | | Fix pll3x2 and pll7x2 not having a parent clock, specifically this fixes the kernel turning of pll3 while simplefb is using it when uboot has configured things to use pll3x2 as lcd ch clk parent. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add pll3 to simplefb nodes clocks listsHans de Goede2016-06-221-5/+6
| | | | | | | | | | | Now that we've a clock node describing pll3 we must add it to the simplefb nodes clocks lists to avoid it getting turned off when simplefb is used. This fixes the screen going black when using simplefb. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: dt: Add pll3 and pll7 clocksPriit Laes2016-05-081-0/+41
| | | | | | | Enable pll3 and pll7 clocks that are needed by display clocks. Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: dt: Enable dram gate 5 (tve0 clock) for simplefb TV outputPriit Laes2016-03-271-2/+3
| | | | | | | | | | | Seems like dram_gate 5 was forgotten when DRAM gating driver was added. Add it. Cc: stable@vger.kernel.org Fixes: 0b4bf5a5200b (ARM: dts: sun7i: Add DRAM gates) Signed-off-by: Priit Laes <plaes@plaes.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add the SPDIF block to the A20Marcus Cooper2016-03-271-0/+13
| | | | | | | Add the SPDIF transceiver controller block to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add the SPDIF clk to the A20Marcus Cooper2016-03-271-0/+11
| | | | | | | Add the SPDIF clock to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add SPDIF TX pin to the A20Marcus Cooper2016-03-271-0/+7
| | | | | | | Add the SPDIF TX pin to the A20 dtsi. Signed-off-by: Marcus Cooper <codekipper@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add VE (Video Engine) module clock nodeChen-Yu Tsai2015-12-081-0/+9
| | | | | | | | The video engine has its own module clock, which also includes a reset control for it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun7i: Add DRAM gatesChen-Yu Tsai2015-12-071-3/+29
| | | | | | | | | The DRAM gates controls direct memory access for some peripherals. These peripherals include the display pipeline, so add the required gates to the simplefb nodes as well. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun7i: Add sunxi codec device nodeEmilio López2015-10-211-0/+13
| | | | | | | | | | The A20 SoC includes the Allwinner audio codec, capable of both 24-bit playback and capture. This commit adds a device node for it. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun7i: Add audio codec clockMaxime Ripard2015-10-211-0/+9
| | | | | | | | The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun7i: Add audio PLLMaxime Ripard2015-10-211-0/+9
| | | | | | | | The A20 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). Add it to the DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun7i: Add keypad clk nodeYassin Jaffer2015-09-271-0/+8
| | | | | | | This patch add support to the keypad clock on sun7i Signed-off-by: Yassin Jaffer <yassinjaffer@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Raise minimum CPU voltage for sun7i-a20 to meet SoC ↵Timo Sigurdsson2015-09-131-1/+1
| | | | | | | | | | | | | | | | specifications sun7i-a20.dtsi contains a cpufreq operating point at 0.9 volts. The minimum CPU voltage for the Allwinner A20 SoC, however, is 1.0 volts. Thus, raise the voltage for the lowest operating point to 1.0 volts in order to stay within the SoC specifications. It is an undervolted setting that isn't stable across all SoCs and boards out there. Cc: <stable@vger.kernel.org> # v4.0+ Fixes: d96b7161916f ("ARM: dts: sun7i: Add cpu clock reference and operating points to dtsi") Signed-off-by: Timo Sigurdsson <public_timo.s@silentcreek.de> Acked-by: Iain Paton <ipaton0@gmail.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-09-011-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
| * ARM: sunxi: dt: Convert users to the PIO interrupts bindingMaxime Ripard2015-07-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: sun7i: Add USB Dual Role ControllerRoman Byshko2015-07-061-0/+13
| | | | | | | | | | | | | | Add a node for the otg/drc usb controller to sun7i-a20.dtsi Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | Merge git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6Linus Torvalds2015-08-311-0/+8
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull crypto updates from Herbert Xu: "Here is the crypto update for 4.3: API: - the AEAD interface transition is now complete. - add top-level skcipher interface. Drivers: - x86-64 acceleration for chacha20/poly1305. - add sunxi-ss Allwinner Security System crypto accelerator. - add RSA algorithm to qat driver. - add SRIOV support to qat driver. - add LS1021A support to caam. - add i.MX6 support to caam" * git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (163 commits) crypto: algif_aead - fix for multiple operations on AF_ALG sockets crypto: qat - enable legacy VFs MPI: Fix mpi_read_buffer crypto: qat - silence a static checker warning crypto: vmx - Fixing opcode issue crypto: caam - Use the preferred style for memory allocations crypto: caam - Propagate the real error code in caam_probe crypto: caam - Fix the error handling in caam_probe crypto: caam - fix writing to JQCR_MS when using service interface crypto: hash - Add AHASH_REQUEST_ON_STACK crypto: testmgr - Use new skcipher interface crypto: skcipher - Add top-level skcipher interface crypto: cmac - allow usage in FIPS mode crypto: sahara - Use dmam_alloc_coherent crypto: caam - Add support for LS1021A crypto: qat - Don't move data inside output buffer crypto: vmx - Fixing GHASH Key issue on little endian crypto: vmx - Fixing AES-CTR counter bug crypto: null - Add missing Kconfig tristate for NULL2 crypto: nx - Add forward declaration for struct crypto_aead ...
| * | ARM: sun7i: dt: Add Security System to A20 SoC DTSLABBE Corentin2015-07-201-0/+8
| |/ | | | | | | | | | | | | | | | | | | | | The Security System is a hardware cryptographic accelerator that support AES/MD5/SHA1/DES/3DES/PRNG algorithms. It could be found on many Allwinner SoC. This patch enable the Security System on the Allwinner A20 SoC Device-tree. Signed-off-by: LABBE Corentin <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
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