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* ARM: sunxi: dt: Fix whitespace errorsMaxime Ripard2015-05-101-5/+5
| | | | | | | | | A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard2015-05-101-11/+19
| | | | | | | | | A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Remove the FSF addressMaxime Ripard2015-05-101-5/+0
| | | | | | | | | | The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Set PLL6 as parent to AHB1 clock in AHB1 clock nodeChen-Yu Tsai2015-04-271-4/+8
| | | | | | | | | | | | | On sun6i we already have PLL6 as AHB1 clock's parent. However this was previously set in the dma controller node, which takes effect when the dma controller is probed. We want this to take effect as soon as possible, so hrtimer rate calculation is correct, and to be sure the AHB1 clock rate remains as stable as possible. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add cpu thermal zones to dtsiChen-Yu Tsai2015-04-271-0/+33
| | | | | | | | The core temperature sensor now supports thermal zones. Add a thermal zone mapping for the cpus with passive cooling (cpufreq throttling). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add cpu clock reference and operating points to dtsiChen-Yu Tsai2015-04-271-1/+13
| | | | | | | | | | | | | The cpu core is clocked from the "cpu" clock. Add a reference to it in the first cpu node. Also add "cpu0" label to the node. The operating points were taken from the a list compiled by Maxime Ripard, which is based on A31 FEX files from the sunxi-boards repository. Not all boards have the same settings. The settings in this patch are the ones shared by A/B/C revisions, plus the default clock setting from u-boot. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add pinmux settings for mmc1 to dtsiChen-Yu Tsai2015-04-271-0/+8
| | | | | | | | mmc1 is used to connect to the WiFi chip on the Hummingbird A31. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [maxime: Changed the drive and pull values for their defines] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede2015-04-271-0/+8
| | | | | | | | | | | | | | Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: add p2wi controller node to dtsiBoris BREZILLON2015-04-271-0/+21
| | | | | | | | | | The p2wi controller has only one possible pinmux setting. Use it by default in the dtsi, instead of having to set it in each board's dts. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> [wens@csie.org: reformat commit title; rename p2wi pins and use as default] Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-211-31/+55
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * Merge branch 'clk-next' into v3.19-rc7Michael Turquette2015-02-021-31/+55
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| | * ARM: sunxi: dt: Add sample and output mmc clocksMaxime Ripard2015-01-141-20/+52
| | | | | | | | | | | | | | | | | | | | | | | | Add the sample and output clocks for the MMC phase support. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
| | * ARM: dts: sun6i: Unify ahb1 clock nodesChen-Yu Tsai2014-12-211-11/+3
| | | | | | | | | | | | | | | | | | | | | | | | The clock driver has unified support for the ahb1 clock. Unify the clock nodes so it works. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | | Merge tag 'dt-for-linus' of ↵Linus Torvalds2015-02-171-64/+118
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
| * | ARM: dts: sun6i: Add resistive touchscreen controller node to dtsiChen-Yu Tsai2015-01-241-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Now that we support the sun6i variant of the touchscreen controller, add the device node to the dtsi so we can use it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sun6i: Enable ARM arch timersMaxime Ripard2015-01-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The A31 has non-initialized architected timers, without CNTFRQ or CNTVOFF set by the Allwinner's bootloader. Use the new DT property for such case, and enable the arch timers. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sunxi: Add simplefb nodes for de_be0-lcd0, de_be0-lcd0-tve0 pipelinesHans de Goede2015-01-211-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add simplefb nodes for "[de_fe0-]de_be0-lcd0" and "[de_fe0-]de_be0-lcd0-tve0" display pipelines for when u-boot has set up a pipeline to drive a LCD panel / VGA output rather then the HDMI output. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert the DTs to use the GIC headersMaxime Ripard2015-01-211-48/+51
| | | | | | | | | | | | | | | | | | | | | | | | The GIC requires some extra opaque arguments to set the IRQ type and flags. Convert the DTs to using the common defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert the DTs to use a header for the pinctrl nodesMaxime Ripard2015-01-211-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pinctrl nodes require some extra opaque arguments for the pull up and drive strength values. Introduce a new header file and convert the device trees to replace these opaque numbers by defines. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: sunxi: DT: Convert to device tree includesMaxime Ripard2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | Prepare the device trees to use the C preprocessor. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun6i: Add ir nodeHans de Goede2015-01-211-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Add a node for the ir receiver found on the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> [Maxime: Added a node label] Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun6i: Add ir_clk nodeHans de Goede2015-01-211-0/+7
| | | | | | | | | | | | | | | | | | | | | Add an ir_clk sub-node to the prcm node. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * | ARM: dts: sun6i: Add pinmux settings for the ir pinsHans de Goede2015-01-211-0/+7
| |/ | | | | | | | | | | | | Add pinmux settings for the ir receive pin of the A31. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: dt: Fix aliasesMaxime Ripard2015-01-251-6/+0
|/ | | | | | | | | | Commit f77d55a3b56a ("serial: 8250_dw: get index of serial line from DT aliases") made the serial driver now use the serial aliases to get the tty number, pointing out that our aliases have been wrong all along. Remove them from the DTSI and add custom ones in the relevant boards. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-201-10/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * ARM: dts: sunxi: Use sun4i-a10-apb1-clk for sun6i/sun8i apb2 clocks.Chen-Yu Tsai2014-11-231-10/+2
| | | | | | | | | | | | | | | | | | | | The apb2 clocks are actually the same as apb1 clocks on the other sunxi platforms, hence compatible with "allwinner,sun4i-a10-apb1-clk". Update the dtsi to use the new unified apb1 clk. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sunxi: Update simplefb nodes so that u-boot can find themHans de Goede2014-11-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Review of the u-boot sunxi simplefb patches has led to the decision that u-boot should not use a specific path to find the nodes as this goes contrary to how devicetree usually works. Instead a platform specific compatible + properties should be used for this. The simplefb bindings have already been updated to reflect this, this patch brings the sunxi devicetree files in line with the new binding, and the actual u-boot implementation as it is going upstream. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sunxi: Add de_be0 clk parent pll to simplefb nodeHans de Goede2014-11-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Avoid the parent pll for the mod-clk for de_be0 getting disabled when non of the other users are enabled (which can happen when none of i2c, spi and mmc are in use). Note for now we point directly to the parent rather then to the de_be0 mod-clk as that is not modelled in our devicetree yet. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun6i: Add simplefb nodeHans de Goede2014-11-231-0/+10
| | | | | | | | | | | | | | Add a simplefb template node for u-boot to further fill and activate. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun6i: DT: Add PLL6 multiple outputsChen-Yu Tsai2014-11-231-14/+14
| | | | | | | | | | | | | | PLL6 on sun6i has multiple outputs, just like the other sunxi platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: Fix GPLv2 wordingMaxime Ripard2014-11-231-3/+3
| | | | | | | | | | | | | | | | | | During the GPL to GPL/X11 licensing migration, the GPL notice introduced mentionned the device trees as a library, which is not really accurate. It began to spread by copy and paste. Fix all these library mentions to reflect the file that it's actually just a file. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun6i: Re-parent ahb1_mux to pll6 as required by dma controllerChen-Yu Tsai2014-11-081-0/+4
|/ | | | | | | | | | | | | | | | | | The dma controller requires that the ahb1 bus clock be driven by pll6 for peripheral access to work. Previously this was done in the dma controller driver, but was since removed as part of a series to unify the ahb1_mux and ahb1 clock drivers, in 14e0e28 dmaengine: sun6i: Remove obsolete clk muxing code Unfortunately the rest of that series did not make it, leaving us with broken dma on sun6i. This patch reparents ahb1_mux to pll6 using the DT assigned-clocks properties in the dma controller node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'sunxi-dt-for-3.18' of ↵Arnd Bergmann2014-09-251-9/+47
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/dt Pull "Allwinner DT Additions for 3.18" from Maxime Ripard: Mostly: - A23 bringup ongoing - New boards: HSG H702, Merrii A20 Hummingbird - sun(4|5|7)i DMA support - DT relicensing to a dual GPL/X11 license Signed-off-by: Arnd Bergmann <arnd@arndb.de> * tag 'sunxi-dt-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux: (30 commits) ARM: dts: sun8i: Add DMA controller node ARM: dts: sun5i: Add DT for HSG H702 tablet board ARM: dts: sunxi: Add fixed 5V regulator ARM: sun8i: Relicense the A23 DTSI under GPLv2/X11 ARM: sun7i: Relicense the A20 DTSI under GPLv2/X11 ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11 ARM: sun7i: Add support for Olimex A20-OLinuXino-LIME ARM: dts: sun7i: Add Merrii A20 Hummingbird board ARM: dts: sun7i: Add uart3/4/5, i2c3 and spi2 pinmux ARM: dt: sunxi: Remove i2c controller clock-frequency that matches default ARM: dts: sun8i: Enable i2c controllers on ippo-q8h-v5 ARM: dts: sun8i: Add i2c controller nodes ARM: dts: sun8i: Add pin-muxing info for the i2c controllers ARM: dts: sun8i: Enable mmc controller on ippo-q8h-v5 ARM: dts: sun8i: Add mmc controller nodes ARM: dts: sun8i: Add pin-muxing info for the mmc controllers ARM: dts: sun8i: Add mmc clocks to the dtsi ARM: dts: sun8i: ippo-q8h: Add pinctrl properties for R_UART ARM: dts: sun8i: Add pin muxing option for R_UART ARM: dts: sun8i: Add pinmux set for uart0 ...
| * ARM: sun6i: Relicense the A31 DTSI under GPLv2/X11Maxime Ripard2014-09-071-5/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current GPL only licensing on the DTSI makes it very impractical for other software components licensed under another license. In order to make it easier for them to reuse our device trees, relicense our DTSI first under a GPL/X11 dual-license. Hopefully, the DTS will follow soon. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Carlo Caione <carlo@caione.org> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: dt: sunxi: Remove i2c controller clock-frequency that matches defaultChen-Yu Tsai2014-08-181-4/+0
| | | | | | | | | | | | | | | | | | The clock-frequency values of the i2c controller nodes match the defaults of the driver. Remove the properties to use the defaults, and be consistent with sun8i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
| * ARM: dts: sun6i: add rtc device nodeChen-Yu Tsai2014-08-171-0/+6
| | | | | | | | | | | | | | | | Now that we have a driver for sun6i's rtc hardware, add a device node for it so we can use it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dt: sun6i: Add #address-cells and #size-cells to i2c controller nodesChen-Yu Tsai2014-07-281-0/+8
|/ | | | | | | | | | dtc was giving warnings for missing #address-cells and #size-cells for the new sun6i-a31-hummingbird.dts, which has a i2c-based rtc device. This patch adds the properties for all i2c controller nodes for sun6i. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add ethernet alias for GMACChen-Yu Tsai2014-07-181-0/+1
| | | | | | | Alias GMAC as ethernet0 so U-boot can fill in the MAC address. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add A31 GMAC gigabit ethernet controller nodeChen-Yu Tsai2014-07-181-0/+17
| | | | | | | | The A31 has the same GMAC found on the A20 SoC, except it has an extra reset control. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add GMAC clock node to the A31 dtsiChen-Yu Tsai2014-07-181-0/+28
| | | | | | | | | The GMAC uses 1 of 2 sources for its transmit clock, depending on the PHY interface mode. Add both sources as dummy clocks, and as parents to the GMAC clock node. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun6i: Add pin muxing options for GMACChen-Yu Tsai2014-07-181-0/+42
| | | | | | | | The A31 SoC has a GMAC gigabit ethernet controller supporting MII, GMII, RGMII modes. Add pin muxing options for these modes. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add #interrupt-cells to pinctrl nodesChen-Yu Tsai2014-07-011-2/+2
| | | | | | | | | | | | The pinctrl device is also an interrupt controller for external interrupts. Add the missing #interrupt-cells property. Also remove the unused #address-cells property. Signed-off-by: Chen-Yu Tsai <wens@csie.org> [hdegoede@redhat.com: make the same change for sun4i, sun5i and sun6i] Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge branch 'timers-core-for-linus' of ↵Linus Torvalds2014-06-041-0/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip into next Pull timer core updates from Thomas Gleixner: "This time you get nothing really exciting: - A huge update to the sh* clocksource drivers - Support for two more ARM SoCs - Removal of the deprecated setup_sched_clock() API - The usual pile of fixlets all over the place" * 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits) clocksource: Add Freescale FlexTimer Module (FTM) timer support ARM: dts: vf610: Add Freescale FlexTimer Module timer node. clocksource: ftm: Add FlexTimer Module (FTM) Timer devicetree Documentation clocksource: sh_tmu: Remove unnecessary OOM messages clocksource: sh_mtu2: Remove unnecessary OOM messages clocksource: sh_cmt: Remove unnecessary OOM messages clocksource: em_sti: Remove unnecessary OOM messages clocksource: dw_apb_timer_of: Do not trace read_sched_clock clocksource: Fix clocksource_mmio_readX_down clocksource: Fix type confusion for clocksource_mmio_readX_Y clocksource: sh_tmu: Fix channel IRQ retrieval in legacy case clocksource: qcom: Implement read_current_timer for udelay ntp: Make is_error_status() use its argument ntp: Convert simple_strtol to kstrtol timer_stats/doc: Fix /proc/timer_stats documentation sched_clock: Remove deprecated setup_sched_clock() API ARM: sun6i: a31: Add support for the High Speed Timers clocksource: sun5i: Add support for reset controller clocksource: efm32: use $vendor,$device scheme for compatible string KConfig: Vexpress: build the ARM_GLOBAL_TIMER with vexpress platform ...
| * ARM: sun6i: a31: Add support for the High Speed TimersMaxime Ripard2014-04-221-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The Allwinner A31 has support for four high speed timers. Apart for the number of timers (4 vs 2), it's basically the same logic than the high speed timers found in the sun5i chips. Now that we have a driver to support it, we can enable them in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
* | ARM: sun6i: Fix OHCI2 node nameMaxime Ripard2014-05-221-1/+1
| | | | | | | | | | | | | | The unit-address doesn't match the reg property. Since the reg property is correct, change the unit-address accordingly. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun6i: Define the A31 CPUs enable-methodMaxime Ripard2014-05-171-0/+1
| | | | | | | | | | | | That will allow to use the CPU_METHOD_OF_DECLARE definition we did previously. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: dt: declare the r_pio pin controller for A31 SoCBoris BREZILLON2014-05-151-0/+14
| | | | | | | | | | | | | | | | The A31 SoC has a different pin controller for PL and PM banks. Define this new controller in the device tree. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: dt: add PRCM clk and reset controller subdevicesBoris BREZILLON2014-05-151-0/+38
| | | | | | | | | | | | | | | | Add DT definitions for PRCM (Power/Reset/Clock Management) clock and reset controller subdevices. Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun6i: dt: Add support for the USB controllersMaxime Ripard2014-05-141-0/+77
| | | | | | | | | | | | | | The A31 has two ECHI/OHCI controllers, and one OHCI-only phy-less controller. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sun6i: Add the USB clocks to the DTSIMaxime Ripard2014-05-141-0/+11
| | | | | | | | | | | | | | | | The USB clocks of the A31 seems to be parented to the 24MHz oscillator, and handle the clocks for the USB phys and OHCI devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com>
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