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* ARM: dts: sun5i: Fix the SRAM A3-A4 declarationMaxime Ripard2018-07-191-6/+6
| | | | | | | | | According to the system control bindings, the A3-A4 SRAM node should be a child node of the SRAM it belongs to. However, it was introduced at the same level, therefore breaking the binding. Fix this. Fixes: 85870196258f ("ARM: sun5i: a13: Merge common controllers into the common DTSI") Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun5i: Add support for the C1 SRAM region with the SRAM controllerMaxime Ripard2018-07-111-0/+14
| | | | | | | | | | | | This adds support for the C1 SRAM region (to be used with the SRAM controller driver) for sun5i-based platforms. The region is shared between the Video Engine and the CPU. Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> [Maxime: Fixed the SRAM C size to take the C2 and C3 SRAM into account] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* ARM: dts: sun5i: Use most-qualified system control compatiblesPaul Kocialkowski2018-07-111-4/+6
| | | | | | | | | | | | | | This switches the sun5i dtsi to use the most qualified compatibles for the system-control block (previously named SRAM controller) as well as the SRAM blocks. The node name for system control is also updated to reflect the fact that the controller described is really about system control rather than SRAM control. Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> [Maxime: Removed the A10 compatible for the driver] Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
* arm: dts: fix unit-address leading 0sRob Herring2017-10-201-43/+43
| | | | | | | | | | | | | Fix dtc warnings for 'simple_bus_reg' due to leading 0s. Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find arch/arm/boot/dts -type -f -name '*.dts*' Dropped changes to ARM, Ltd. boards LED nodes and manually fixed up some occurrences of uppercase hex. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* ARM: sun5i: add a cryptographic engine nodeAntoine Tenart2017-06-071-0/+9
| | | | | | | | | Add a node for the cryptographic engine that can be found on sun5i SoCs. This cryptographic engine is compatible with the Allwinner cryptographic accelerator driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: a10s: Add the HDMI controller nodeMaxime Ripard2017-05-191-0/+1
| | | | | | | | | | | | The A10s has an HDMI controller connected to the second TCON channel. Add it to our DT. Since the TV Encoder was the only channel 1 user so far, also add the property now that we have several users. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> [wens@csie.org: Replaced CLK_PLL_VIDEO[01]_2X with raw numbers for now Signed-off-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun5i: Add interrupt for display backendChen-Yu Tsai2017-03-291-0/+1
| | | | | | | | The display backend on sun5i shares the same interrupt line as the display frontend. Add it. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Remove no longer used pinctrl/sun4i-a10.h headerChen-Yu Tsai2017-03-271-1/+0
| | | | | | | | | | | | | | | | | All dts files for the sunxi platform have been switched to the generic pinconf bindings. As a result, the sunxi specific pinctrl macros are no longer used. Remove the #include entry with the following command: sed --follow-symlinks -i -e '/pinctrl\/sun4i-a10.h/D' \ arch/arm/boot/dts/sun?i*.* arch/arm/boot/dts/sun9i-a80.dtsi was then edited to remove the extra empty line. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: gr8: Use common sun5i DTSIMaxime Ripard2017-03-061-0/+45
| | | | | | | | | | | Most of the GR8 DTSI is duplicated with the common sun5i DTSI, and some of the extra nodes defined there actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it, and include the sun5i DTSI. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: r8: Merge common controllers into the common DTSIMaxime Ripard2017-03-061-0/+23
| | | | | | | | | Some controllers found in the R8 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: a10s: Merge common controllers into the common DTSIMaxime Ripard2017-03-061-0/+62
| | | | | | | | | Some controllers found in the A10s DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: a13: Merge common controllers into the common DTSIMaxime Ripard2017-03-061-0/+140
| | | | | | | | | Some controllers found in the A13 DTSI actually apply to all of the sun5i family. Move those into the common DTSI so that all SoCs can benefit from it. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: Rename UART3 flow control pinsMaxime Ripard2017-03-061-1/+1
| | | | | | | | The UART3 pin group for the CTS and RTS signals doesn't follow our usual pattern. Rename it so that it matches. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: Add UART2 pin groupMaxime Ripard2017-03-061-0/+10
| | | | | | | | | | | There's one UART2 pin group that can be used across all sun5i SoCs. However, the A10s already has one pin group for that controller. Change the index of the one in the A10s DTSI, and add the common one to sun5i.dtsi Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* Merge tag 'clk-for-linus' of ↵Linus Torvalds2017-02-251-317/+36
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The usual collection of new drivers, non-critical fixes, and updates to existing clk drivers. The bulk of the work is on Allwinner and Rockchip SoCs, but there's also an Intel Atom driver in here too. New Drivers: - Tegra BPMP firmware - Hisilicon hi3660 SoCs - Rockchip rk3328 SoCs - Intel Atom PMC - STM32F746 - IDT VersaClock 5P49V5923 and 5P49V5933 - Marvell mv98dx3236 SoCs - Allwinner V3s SoCs Removed Drivers: - Samsung Exynos4415 SoCs Updates: - Migrate ABx500 to OF - Qualcomm IPQ4019 CPU clks and general PLL support - Qualcomm MSM8974 RPM - Rockchip non-critical fixes and clk id additions - Samsung Exynos4412 CPUs - Socionext UniPhier NAND and eMMC support - ZTE zx296718 i2s and other audio clks - Renesas CAN and MSIOF clks for R-Car M3-W - Renesas resets for R-Car Gen2 and Gen3 and RZ/G1 - TI CDCE913, CDCE937, and CDCE949 clk generators - Marvell Armada ap806 CPU frequencies - STM32F4* I2S/SAI support - Broadcom BCM2835 DSI support - Allwinner sun5i and A80 conversion to new style clk bindings" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (130 commits) clk: renesas: mstp: ensure register writes complete clk: qcom: Do not drop device node twice clk: mvebu: adjust clock handling for the CP110 system controller clk: mvebu: Expand mv98dx3236-core-clock support clk: zte: add i2s clocks for zx296718 clk: sunxi-ng: sun9i-a80: Fix wrong pointer passed to PTR_ERR() clk: sunxi-ng: select SUNXI_CCU_MULT for sun5i clk: sunxi-ng: Check kzalloc() for errors and cleanup error path clk: tegra: Add BPMP clock driver clk: uniphier: add eMMC clock for LD11 and LD20 SoCs clk: uniphier: add NAND clock for all UniPhier SoCs ARM: dts: sun9i: Switch to new clock bindings clk: sunxi-ng: Add A80 Display Engine CCU clk: sunxi-ng: Add A80 USB CCU clk: sunxi-ng: Add A80 CCU clk: sunxi-ng: Support separately grouped PLL lock status register clk: sunxi-ng: mux: Get closest parent rate possible with CLK_SET_RATE_PARENT clk: sunxi-ng: mux: honor CLK_SET_RATE_NO_REPARENT flag clk: sunxi-ng: mux: Fix determine_rate for mux clocks with pre-dividers clk: qcom: SDHCI enablement on Nexus 5X / 6P ...
| * ARM: sun5i: Convert to CCUMaxime Ripard2017-01-231-317/+36
| | | | | | | | | | | | | | | | Now that we have drivers for all of them, convert all the SoCs that share the sun5i DTSI to the new CCU driver. Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sun5i: add a pinctrl node for 4bit mmc2Icenowy Zheng2017-01-101-0/+8
| | | | | | | | | | | | | | | | | | Some board only use 4bit mode of mmc2. Add a pinctrl node for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: dts: sunxi: Explicitly enable pull-ups for MMC pinsChen-Yu Tsai2017-01-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the past, all the MMC pins had allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; which was actually a no-op. We were relying on U-boot to set the bias pull up for us. These properties were removed as part of the fix up to actually support no bias on the pins. During the transition some boards experienced regular MMC time-outs during normal operation, while others completely failed to initialize the SD card. Given that MMC starts in open-drain mode and the pull-ups are required, it's best to enable it for all the pin settings. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sunxi: Convert pinctrl nodes to generic bindingsMaxime Ripard2016-12-261-28/+28
| | | | | | | | | | | | | | | | Now that we can handle the generic pinctrl bindings, convert our DT to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,pull propertyMaxime Ripard2016-12-261-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | The allwinner,pull property set to NO_PULL was really considered our default (and wasn't even changing the default value in the code). Remove these properties to make it obvious that we do not set anything in such a case. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* | ARM: sunxi: Remove useless allwinner,drive propertyMaxime Ripard2016-12-261-9/+0
|/ | | | | | | | | The allwinner,drive property set to 10mA was really considered as our default. Remove all those properties entirely to make that obvious. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: sunxi: Add the missing clocks to the pinctrl nodesMaxime Ripard2016-11-221-1/+2
| | | | | | | | | The pin controllers also use the two oscillators for debouncing. Add them to the DTs. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: Add RGB 565 LCD pinsMaxime Ripard2016-11-221-0/+10
| | | | | | | Some boards use the LCD in RGB565. Enable the pin muxing option. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: Add SPI2 pinsMaxime Ripard2016-11-221-0/+14
| | | | | | | | All the sun5i have the SPI2 pins exposed on the PE bank. Add them to the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rateMaxime Ripard2016-07-041-1/+1
| | | | | | | | | In order to be able to properly generate its pixel clock, the pll3-2x fixed factor needs to be able to change the PLL3 rate too. Add the needed extra compatible so that it behaves that way. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: dt: Add pll3 and pll7 clocksMaxime Ripard2016-04-191-0/+43
| | | | | | | | | Enable the pll3 and pll7 clocks in the DT that are used to drive the display-related clocks. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: Add the Audio codec DT nodeMaxime Ripard2015-10-211-0/+13
| | | | | | | | The A13 and A10s also have the audio codec present. List it in the device tree. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: Add audio codec clockMaxime Ripard2015-10-211-0/+9
| | | | | | | | The audio codec functional clock is a child of PLL2 and is used to control the audio rate, enable it in the DT. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: Add audio PLLMaxime Ripard2015-10-211-0/+9
| | | | | | | | | | The A13 uses the PLL2 as the audio PLL, which is the parent of all the other audio clocks in the system (i2s, codec, etc.). However, it has a different divider configuration than the A10, hence the difference compatible. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Chen-Yu Tsai <wens@csie.org>
* ARM: dts: sun5i: Add PWM channel 0 pinmux setting for A13/A10sHans de Goede2015-10-121-0/+7
| | | | | | | | Add a pinmux setting for the first pwm channel. This is often used for backlight dimming on tablets. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: dt: Add UART3 CTS and RTS pinsMaxime Ripard2015-10-111-0/+7
| | | | | | | | | Add a separate pinctrl node for the UART3 CTS and RTS pins shared between the A10s and A13. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
* ARM: sun5i: dt: Move uart3 pinctrl node to common DTSIMaxime Ripard2015-10-111-0/+7
| | | | | | | | | The uart3 pins are shared between the A10s and A13, move the pinctrl node to the common DTSI to avoid duplication. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
* Merge tag 'armsoc-dt' of ↵Linus Torvalds2015-09-011-2/+14
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "Ladies and gentlemen, we proudly announce to you the latest branch of ARM device tree contents for the mainline kernel. Come and see, come and see! No less than twentythree thousand lines of additions! Just imagine the joy you will have of using your mainline kernel on newly supported hardware such as Rockchip Chromebooks, Freescale i.MX6UL boards or UniPhier hardware! For those of you feeling less adventurous, added hardware support on platforms such as TI DM814x and Gumstix Overo platforms might be more of your liking. We've got something for everyone here! Ahem. Cough. So, anyway... This is the usual large batch of DT updates. Lots and lots of smaller changes, some of the larger ones to point out are: - Rockchip veyron (Chromebook) support, as well as several other new boards - DRM support on Atmel AT91SAM9N12EK - USB additions on some Allwinner platforms - Mediatek MT6580 support - Freescale i.MX6UL support - cleanups for Renesas shmobile platforms - lots of added devices on LPC18xx - lots of added devices and boards on UniPhier There's also some dependent code added here, in particular some branches that are primarily merged through the clock tree" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (389 commits) ARM: tegra: Add gpio-ranges property ARM: tegra: Fix AHB base address on Tegra20, Tegra30 and Tegra114 ARM: tegra: Add Tegra124 PMU support ARM: tegra: jetson-tk1: Add GK20A GPU DT node ARM: tegra: venice2: Add GK20A GPU DT node ARM: tegra: Add IOMMU node to GK20A ARM: tegra: Add CPU regulator to the Jetson TK1 device tree ARM: tegra: Add entries for cpufreq on Tegra124 ARM: tegra: Enable the DFLL on the Jetson TK1 ARM: tegra: Add the DFLL to Tegra124 device tree ARM: dts: zynq: Add devicetree entry for Xilinx Zynq reset controller. ARM: dts: UniPhier: fix PPI interrupt CPU mask of timer nodes ARM: dts: rockchip: correct regulator power states for suspend ARM: dts: rockchip: correct regulator PM properties ARM: dts: vexpress: Use assigned-clock-parents for sp810 pinctrl: tegra: Only set the gpio range if needed arm: boot: dts: am4372: add ARM timers and SCU nodes ARM: dts: AM4372: Add the am4372-rtc compatible string ARM: shmobile: r8a7794 dtsi: Add CPG/MSTP Clock Domain ARM: shmobile: r8a7793 dtsi: Add CPG/MSTP Clock Domain ...
| * ARM: sunxi: dt: Convert users to the PIO interrupts bindingMaxime Ripard2015-07-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current DTs were setting the cell size to 2, but used the default xlate function that was assuming an interrupt cell size of 1, leading to the second part of the cell (the flags) being ignored, while we were having an inconsistent binding between the interrupts and gpio (that could also be used as interrupts). That "binding" doesn't work either with newer SoCs that have multiple irq banks. Now that we fixed the pinctrl driver to handle this like it should always have been handled, convert the DT users, and while we're at it, remove the size-cells property of PIO that is completely useless. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
| * ARM: dts: sun5i: Add USB Dual Role ControllerHans de Goede2015-07-061-0/+13
| | | | | | | | | | | | | | Add a node for the otg/drc usb controller to sun5i-a1*.dtsi. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* | ARM: sun5i: Add clock indicesMaxime Ripard2015-08-121-0/+1
|/ | | | | | | | The A10s and A13 gates have a non continuous set of clock IDs that are valid. Add the clock-indices property to the DT to express this. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
* ARM: dts: sun5i: Add A10s and A13 SRAM and SRAM controllerMaxime Ripard2015-06-011-0/+30
| | | | | | | | | | | | | The A10s and A13 have a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Add the SRAM controller, the SRAM that it drives and the section that can be used by the various devices. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Hans de Goede <hdegoede@redhat.com> Tested-by: Hans de Goede <hdegoede@redhat.com>
* ARM: dts: sunxi: Revert SRAM controller drivers patchesMaxime Ripard2015-06-011-34/+0
| | | | | | | | | | | | This patch reverts commit ccb4ada2f193 ("ARM: dts: sun7i: Add A20 SRAM and SRAM controller"), commit e6f51e4bd2a5 ("ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controller") and commit 6d92b80f356f ("ARM: dts: sun4i: Add A10 SRAM and SRAM controller"). The bindings have been changed in the SRAM driver, and we need to change the DT accordingly. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Fix whitespace errorsMaxime Ripard2015-05-101-1/+1
| | | | | | | | | A few lines (probably copy pasted) have an indentation mixing tabs and spaces that triggers a checkpatch warning. Fix those, and while we're at it, fix the space-indented sections. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: DT: Fix lines over 80 charactersMaxime Ripard2015-05-101-1/+2
| | | | | | | | | A few lines in our DTSIs are over the 80 characters limit, making checkpatch complain about that. If possible (and relevant), wrap these lines to 80 characters. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: dt: Remove the FSF addressMaxime Ripard2015-05-101-5/+0
| | | | | | | | | | The FSF address triggers a warning on checkpatch, saying that the FSF license is already present in the Linux source code, and that it has already changed in the past. Remove it from our DT, as suggested. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Update ahb clocks for sun5i and sun7iChen-Yu Tsai2015-04-271-2/+8
| | | | | | | | | | | | | | | The clock driver now supports a muxable ahb clock. Update the dtsi with the proper compatible and add the new parent clocks. This also adds the new pll6/4 output for pll6 on sun7i-a20. The output is not used on sun4/5i. Also use assigned-clocks to reparent ahb to pll6. We want ahb to have a stable, non-changing clock rate. cpu/axi clock rate changes as a result of newly added cpufreq support. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun5i: Add A13 and A10s SRAM and SRAM controllerHans de Goede2015-04-271-0/+34
| | | | | | | | | | | The A13 / A10s has a few SRAM that can be mapped either to a device or to the CPU, with the mapping being controlled by a SRAM controller. Since most of the time these SRAM won't be accessible by the CPU, we can't use the mmio-sram driver and compatible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Add address- and size-cells properties to the mmc ctrl nodesHans de Goede2015-04-271-0/+6
| | | | | | | | | | | | | | Sometimes we need to specify non-probably information for sdio devices in the devicetree, this is done through child nodes addressed by the reg property, whereby the reg property refers to the sdio function number, see; Documentation/devicetree/bindings/mmc/mmc.txt This commit adds the necessary address- and size-cells properties to the mmc controller nodes in the dtsi files, so that dts files needing such a child node do not need to specify these themselves. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sunxi: Adjust touchscreen compatible for sun5i and laterHans de Goede2015-04-271-1/+1
| | | | | | | | | | The touchscreen controller in the A13 and later has a different temperature curve than the one in the original A10, change the compatible for the A13 and later so that the kernel will use the correct curve. Reported-by: Tong Zhang <lovewilliam@gmail.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun5i: Add mmc2 pinmux settingsHans de Goede2015-04-271-0/+9
| | | | | | | Add A13 mmc2 pinmux settings, note these are for a 8bit bus. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: dts: sun5i: Stop using different compatibles for ehci/ohci on a13 vs a10sHans de Goede2015-04-271-0/+2
| | | | | | | | | | | | | | | The A13 and the A10s use the same die (this has been confirmed by Allwinner), as such there is no need to differentiate between the ehci/ohci parts of both, the only reasons there were different allwinner,sun5i-a*-foo compatible between these 2 parts is costemetically and because we could when we still had 2 completely different dtsi files. The allwinner,sun5i-a*-foo compatible strings are not used for binding at all, the actual driver binds to the generic-?hci compatible, so we can safely remove this cosmetical difference and simplify the dtsi files. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: a13: Move to the common sun5i DTSIMaxime Ripard2015-04-271-0/+28
| | | | | | Now that we have a common DTSI for the sun5i family, move the A13 to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sun5i: Add a DTSI common to A10s and A13Maxime Ripard2015-04-271-0/+532
| | | | | | | | | | | The A10s and the A13 are very similar SoCs, the only difference being the number of pins and the number of devices available (number of UARTs, EMAC only in the A10s, etc.), and the clocks and pinctrl functions obviously. Create a common DTSI that will be included by the A10s and A13 DTSI, that will add their SoC differences in there. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
* ARM: sunxi: rename device tree source filesOlof Johansson2012-12-201-20/+0
| | | | | | | This is the rename portion of "ARM: sunxi: Change device tree naming scheme for sunxi" that were missed when the patch was applied. Signed-off-by: Olof Johansson <olof@lixom.net>
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