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* ARM: STi: DT: STiH415: 415 DT Entry for clockgen A9Gabriel FERNANDEZ2014-05-211-9/+39
| | | | | | | | Patch adds DT entries for clockgen A9 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: STiH415: Remove unused CLK_S_GMAC0_PHY & CLK_S_ETH1_PHY fixed ↵Gabriel FERNANDEZ2014-05-211-14/+0
| | | | | | | | | clocks CLK_S_GMAC0_PHY & CLK_S_ETH1_PH clocks are no longer used. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: STiH415: Remove unused CLK_S_ICN_REG_0 fixed clockGabriel FERNANDEZ2014-05-211-10/+0
| | | | | | | CLK_S_ICN_REG_0 clock is no longer used. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: STiH415: 415 DT Entry for clockgen A0/1/10/11/12Gabriel FERNANDEZ2014-05-211-0/+475
| | | | | | | | Patch adds DT entries for clockgen A0/1/10/11/12 Signed-off-by: Pankaj Dev <pankaj.dev@st.com> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: STiH41x: Rename CLK_SYSIN into clk_sysinGabriel FERNANDEZ2014-05-211-1/+1
| | | | | | | all-caps node name is not very usual. Signed-off-by: Gabriel Fernandez <gabriel.fernandez@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: STiH415: Add ethernet support.Srinivas Kandagatla2014-03-111-0/+14
| | | | | | | | | | This patch adds support to STiH415 SOC, which has two ethernet snps,dwmac controllers version 3.610. With this patch B2000 and B2020 boards can boot with ethernet in MII and RGMII modes. Tested on both B2020 and B2000. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com>
* ARM: sti: Add STiH415 SOC supportSrinivas Kandagatla2013-06-251-0/+38
The STiH415 is the next generation of HD, AVC set-top box processors for satellite, cable, terrestrial and IP-STB markets. It is an ARM Cortex-A9 1.0 GHz, dual-core CPU. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> CC: Stephen Gallimore <stephen.gallimore@st.com> CC: Stuart Menefy <stuart.menefy@st.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Olof Johansson <olof@lixom.net>
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