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* ARM: STi: DT: Add STiH407 family mtsin0 pinctrl configurationPeter Griffin2015-07-221-0/+19
| | | | | | | mtsin0 channel can only be configured for parallel data transfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsout1 pinctrl configurationPeter Griffin2015-07-221-0/+12
| | | | | | | tsout1 channel can only be configured for serial data tranfer. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsout0 pinctrl configurationPeter Griffin2015-07-221-0/+28
| | | | | | | | tsout0 channel can be configured for either serial or parallel data transfer. Both pin configurations are provided. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin5 pinctrl configurationPeter Griffin2015-07-221-0/+21
| | | | | | | | | | | | tsin5 can only be configured for serial data transfer. However depending on board design, two alternate tsin5 pin configurations are available, both in pin-controller-front0. pinctrl_tsin5_serial_alt1 is brought out on B2120 reference design as TSD on NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin4 pinctrl configurationPeter Griffin2015-07-221-0/+24
| | | | | | | | | | | | | tsin4 can only be configured for serial data transfer. However depending on board design, two alternate pin configurations are available. One in pin-controller-front0 and the other in pin-controller-front1. pinctrl_tsin4_serial_alt3 is brought out on B2120 reference design as TSC on NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin3 pinctrl configurationPeter Griffin2015-07-221-0/+12
| | | | | | | | | | tsin3 channel can only be configured for serial data transfer. On B2120 reference design tsin3 is brought out as TSB on the NIMB slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin2 pinctrl configurationPeter Griffin2015-07-221-0/+28
| | | | | | | | tsin2 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin1 pinctrl configurationPeter Griffin2015-07-221-0/+28
| | | | | | | | tsin1 channel can be configured for either serial or parallel data transfer. This patch adds the pinctrl config for both possibilities. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: Add STiH407 family tsin0 pinctrl configurationPeter Griffin2015-07-221-0/+28
| | | | | | | | | | tsin0 and be configured as either serial or parallel. This patch adds the pinctrl config for both possiblities. On B2120 reference design tsin0 is brought out as TSA on the NIMA slot of the B2004A daughter board. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: STi: DT: STiH407: Fix retime pin mask for PIO5 and PIO35Karim BEN BELGACEM2015-04-301-0/+2
| | | | | | | | | | | | This will avoid programming the retime registers when not implemented - PIO5 : no retime registers assigned to pins 6 and 7 - PIO35 : pin 7 is reserved so no retime register assigned to it Signed-off-by: Karim BEN BELGACEM <karim.ben-belgacem@st.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
* ARM: dts: Add STiH407 SoC supportMaxime Coquelin2014-05-211-0/+615
The STiH407 is advanced multi-HD AVC processor with 3D graphics acceleration and 1.5-GHz ARM Cortex-A9 SMP CPU. Acked-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Acked-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
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