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* ARM: dts: spear13xx: fix PCI bus dtc warningsRob Herring2017-08-181-0/+3
| | | | | | | | | dtc recently added PCI bus checks. Fix these warnings. Signed-off-by: Rob Herring <robh@kernel.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Update Viresh Kumar's email addressViresh Kumar2015-07-171-1/+1
| | | | | | | | | Switch to my kernel.org alias instead of a badly named gmail address, which I rarely use. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* PCI: spear: Pass config resource through reg propertyPratyush Anand2014-09-221-9/+9
| | | | | | | | | PCIe configuration space should be passed through reg property, rather than through ranges property. This patch does the correction for SPEAr13XX SOCs. Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Mohit Kumar <mohit.kumar@st.com>
* ARM: SPEAr13xx: Add pcie and miphy DT nodesPratyush Anand2014-07-141-3/+90
| | | | | | | | | | | | | | | | | | | | | | | This patch adds necessary DT nodes for pcie controllers and miphys for SPEAr13xx SoCs. SPEAr1310 has 3 PCIe ports and SPEAr1340 has 1, which are multiplexed with ahci/sata pins. By default evaluation board of both controller works in ahci mode. Because of this, these nodes are marked "disabled" by default. In order to use pcie controller on evaluation boards do necessary modifications on board and enable (By replacing "disabled" with "okay") pcie and miphy from respective 'evb' dtsi file. Phy specific initialization was previously done from spear1340.c, which isn't required anymore as we have separate drivers for it. Remove it. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Pratyush Anand <pratyush.anand@st.com> Signed-off-by: Mohit Kumar <mohit.kumar@st.com> [viresh: fixed logs/cclist/checkpatch warnings, clubbed multiple patches into one] Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* gpio: add gpio offset in gpio range cells propertyHaojian Zhuang2013-03-071-2/+2
| | | | | | | | | Add gpio offset into "gpio-range-cells" property. It's used to support sparse pinctrl range in gpio chip. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: SPEAr: DT: Update device nodesShiraz Hashim2012-11-261-0/+2
| | | | | | | | | | | | | This patch adds multiple device nodes for SPEAr machines and boards. Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com> Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* ARM: SPEAr: DT: Modify DT bindings for STMMACDeepak Sikri2012-11-261-0/+4
| | | | | | | | | This patch modifies the DT bindings for the GMAC IP existings for the SPEAr family. The DT bindings now additionally pass the phy mode as a configuration parameter for the ethernet device. Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* ARM: SPEAr: DT: Fix existing DT supportVipul Kumar Samar2012-11-261-7/+7
| | | | | | | | | | | | | | | | | This patch fixes existing DT support for all SPEAr SoC's. This includes: - Removing few nodes from board files - Updating DT data of few nodes - Updating ranges of few busses - Moving devices to correct parent bus Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com> Signed-off-by: Deepak Sikri <deepak.sikri@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com> Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* ARM: SPEAr13xx: DT: Add spics gpio controller nodesShiraz Hashim2012-11-261-0/+12
| | | | | | | | | | | | | | SPEAr platform provides a provision to control chipselects of ARM PL022 Prime Cell spi controller through its system registers, which otherwise remains under PL022 control which some protocols do not want. This patch adds spics controller nodes in device tree for various SPEAr13xx SoCs. Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Reviewed-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
* ARM: SPEAr: Add plgpio node in device tree dtsi filesViresh Kumar2012-11-111-0/+27
| | | | | | | This patch adds plgpio nodes in SPEAr DT files. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* Viresh has movedViresh Kumar2012-06-201-1/+1
| | | | | | | | | | | viresh.kumar@st.com email-id doesn't exist anymore as I have left the company. Replace ST's id with viresh.linux@gmail.com. It also updates .mailmap file to fix address for 'git shortlog' Signed-off-by: Viresh Kumar <viresh.linux@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* SPEAr13xx: Add dts and dtsi filesViresh Kumar2012-05-141-0/+184
This patch adds machines/boards dts{i} files for SPEAr1310 and SPEAr1340. Both are based on ARM, Cortex A9 processor family. Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
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