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* ARM: dts: rk3288: add arm,cpu-registers-not-fw-configuredSonny Rao2014-12-051-0/+1
| | | | | | | | | | | | | | This will enable use of physical arch timers on rk3288, where each core comes out of reset with a different virtual offset. Using physical timers will help with SMP booting on coreboot and older u-boot and should also allow suspend-resume and cpu-hotplug to work on all firmwares. Firmware which does initialize the cpu registers properly at boot and cpu-hotplug can remove this property from the device tree. Signed-off-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Olof Johansson <olof@lixom.net>
* Revert "ARM: dts: rockchip: temporarily disable smp on rk3288"Olof Johansson2014-12-041-0/+1
| | | | | | | | | We now have the physical-timers patches lined up as a dependency in this same branch, so we can revert the temporary disablement. This reverts commit b77d43943ea83997c6c37b8831d1561981d499c5. Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: rockchip: add main thermal info to rk3288Caesar Wang2014-11-251-0/+27
| | | | | | | | | | | | | | If for some reason we are unable to shut it down in orderly fashion (kernel is stuck holding a lock or similar), then hardware TSHUT will reset it. If the temperature is over 95C over a period of time the thermal shutdown of the tsadc is invoked with can either reset the entire chip via the CRU, or notify the PMIC via a GPIO. This should be set in the specific board. Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com> Reviewed-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: temporarily disable smp on rk3288Heiko Stuebner2014-11-221-1/+0
| | | | | | | | | | | | | | | | | | | | Stock firmware on rk3288 does not initizalize the CNTVOFF registers of the architected timer correctly. This introduces issues with the newly added SMP support for rk3288, resulting in rcu stalls due to differing timer values per core. There exist preliminary and tested patches for u-boot for this problem, but there are a minority of boards using other bootloaders like coreboot. There also is currently a second solution for miss-initialized architected timers in the works: - clocksource: arch_timer: Fix code to use physical timers when requested - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers Therefore disable smp on rk3288 again till these are finalized, also allowing coreboot-based boards to boot again. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rk3288: add VOP iommu nodesDaniel Kurtz2014-11-051-0/+18
| | | | | | | | | | | | Add device nodes for the VOP iommus. Device nodes for other iommus will be added in later patches. The iommu nodes use the #iommu-cells property as described in: Documentation/devicetree/bindings/iommu/iommu.txt Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Simon Xue <xxm@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: add reset for CPU nodesKever Yang2014-11-021-0/+4
| | | | | | | | This patch add reset for CPU nodes to use the reset controller. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: add intmem node for rk3288 smp supportKever Yang2014-11-021-0/+12
| | | | | | | | This patch add intmem node des which is needed by platsmp.c Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: add pmu references to cpus nodesKever Yang2014-11-021-0/+2
| | | | | | | | This patch add pmu reference and enable-method for smp Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: Add SPI DMA into rk3288.dtsiDoug Anderson2014-10-251-0/+6
| | | | | | | | Now that SPI DMA has been fixed on rk3288 we can enable it. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Alexandru M Stan <amstan@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: enable init rate for clockKever Yang2014-10-201-0/+10
| | | | | | | | | | | | | | | | | | We need to initialize PLL rate and some of bus clock rate while kernel init, for there is no other module will do that. Basically on rk3288 we use GPLL for cpu bus, peripheral bus and most of peripheral clock, CPLL for devices who require 50M/200M clock rate, leave NPLL behind for special requirement from display system. The common-clock-framework will help us to select best source for child clocks after we init the PLLs propriety. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: add operating points and armclk referencesHeiko Stuebner2014-10-201-1/+18
| | | | | | | | | Add basic OPP entries for current supported Rockchip SoCs. The operating points are currently very conservative, so individual boards may opt to redefine them. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ARM: dts: add rk3288 i2s controllerJianqun2014-09-261-0/+26
| | | | | | | | | | | Add dt for rk3288 i2s controller, since i2s clock pins and data pins default to be GPIO, this patch also add pinctrl to mux them. Tested on RK3288 board. Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Merge tag 'v3.18-rockchip-dts2-v2' of ↵Olof Johansson2014-09-231-0/+218
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Merge "second bunch of dts changes for 3.18" from Heiko Stubner: More peripheral support for Rockchip SoCs - dwc2 usb controllers - spi controllers - emmc controller * tag 'v3.18-rockchip-dts2-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: Remove "regulator-always-on" in vcc_rmii for Radxa Rock ARM: dts: rockchip: fix rk3188 emmc pull references ARM: dts: rockchip: fix swapped Radxa Rock pinctrl references ARM: dts: rockchip: clean up rk3xxx mmc nodes ARM: dts: rockchip: add emmc nodes for rk3066 and rk3188 ARM: dts: rockchip: add Cortex-A9 SPI controller nodes ARM: dts: rockchip: enable usb ports on Radxa Rock ARM: dts: rockchip: add dwc2 controllers for rk3066 and rk3188 ARM: dts: rockchip: remove rockchip,bus-index from rk3xxx i2c0 ARM: dts: Switch i2c0 to 400kHz on rk3288-evb-rk808 ARM: dts: Add rk808 PMIC to rk3288-evb-rk808 ARM: dts: Add mshc aliases for rk3288 ARM: dts: Add SPI nodes to rk3288 ARM: dts: Enable USB host1(dwc) on rk3288-evb ARM: dts: add rk3288 dwc2 controller support ARM: dts: Add sdio0 and sdio1 to the rk3288 Signed-off-by: Olof Johansson <olof@lixom.net>
| * ARM: dts: Add mshc aliases for rk3288Doug Anderson2014-09-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | It's convenient (and less confusing to people reading logs) if the eMMC port on rk3288 is consistenly marked with mmc0 and the sdmmc port on rk3288 is consistently marked with mmc1. Add the appropriate aliases. Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * ARM: dts: Add SPI nodes to rk3288huang lin2014-09-091-0/+92
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic SPI nodes to the base rk3288 device tree file. A few notes: * It's assumed that most users of the SPI ports are using chip select 0. Thus the default pinctrl for the ports enables chip select 0 (but not chip select 1 on ports that have it). If a board wants to use chip select 1 or wants a GPIO chip select the board should override the pinctrl (just like boards can override UART pinctrl if they have hardware flow control). * Since SPI DMA support appears broken and the SPI works fine without DMA we don't include the DMA references. That can come in a later change. Signed-off-by: huang lin <hl@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * ARM: dts: add rk3288 dwc2 controller supportKever Yang2014-09-091-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | rk3288 has two kind of usb controller, this add the dwc2 controller for otg and host1. Controller can works with usb PHY default setting and Vbus on. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * ARM: dts: Add sdio0 and sdio1 to the rk3288Addy Ke2014-09-041-0/+102
| | | | | | | | | | | | | | | | | | This patch requires that <https://patchwork.kernel.org/patch/4701721/> land in order to compile. Reviewed-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | Merge tag 'v3.18-rockchip-dma' of ↵Arnd Bergmann2014-09-041-0/+38
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt Pull "rockchip dma support" from Heiko Stuebner: Enable the AMBA bus and add necessary dma-controller dts nodes * tag 'v3.18-rockchip-dma' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: ARM: dts: rockchip: add rk3066 and rk3188 dma controllers ARM: dts: rockchip: add rk3288 dma controllers ARM: rockchip: enable the AMBA bus Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: dts: rockchip: add rk3288 dma controllersHeiko Stübner2014-09-021-0/+38
| | | | | | | | | | | | | | | | | | | | Add both the bus and peripheral pl330 dma controllers present in rk3288 socs. The first dma controller can change between secure and non-secure mode. Both instances are added but the non-secure variant is left disabled by default, as on the majority of boards the bootloader leaves it in secure mode. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Kever Yang <kever.yang@rock-chips.com>
* | ARM: dts: rockchip: add saradc nodesHeiko Stübner2014-08-271-0/+10
| | | | | | | | | | | | | | Add the core device nodes for the SARADC found on both the Cortex-A9 series (rk3066 and rk3188) as well as the newer rk3288. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | ARM: dts: Add main PWM info to rk3288Doug Anderson2014-08-271-0/+68
| | | | | | | | | | | | | | | | | | This adds the PWM info (other than the VOP PWM) to the main rk3288 dtsi file. Signed-off-by: Caesar Wang <caesar.wang@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | ARM: dts: Add emmc and sdmmc to the rk3288 device treeDoug Anderson2014-08-161-0/+20
|/ | | | | | | | This adds support for the sdmmc and emmc ports on the rk3288. Signed-off-by: Doug Anderson <dianders@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: Fix the sort ordering of EHCI and HSIC in rk3288.dtsiDoug Anderson2014-08-091-20/+20
| | | | | | | | | | The EHCI and HSIC device tree nodes were added in the wrong place. Fix them. Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Olof Johansson <olof@lixom.net>
* ARM: dts: add rk3288 ehci usb devicesKever Yang2014-07-311-0/+20
| | | | | | | | | | | | | | | rk3288 has two kind of usb controller; this adds the ehci variant for host0 and hsic. At the moment we don't add any phys for these controllers, but the default settings seem to work OK. There is a hardware problem in ohci controller which make it unavailable and host0 controller can only support high-speed devices. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* ARM: dts: rockchip: add core rk3288 dtsiHeiko Stuebner2014-07-261-0/+575
Node definitions shared by all rk3288 based boards. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Will Deacon <will.deacon@arm.com> Tested-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Doug Anderson <dianders@chromium.org> Acked-by: Arnd Bergmann <arnd@arndb.de>
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