| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ARM: meson: DTS: enable L2 cache | Beniamino Galvani | 2014-11-18 | 1 | -0/+4 |
| | | | | | | | | | This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org> | ||||
| * | ARM: dts: add dtsi for Amlogic Meson8 SoCs | Beniamino Galvani | 2014-11-18 | 1 | -0/+88 |
| This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6 dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency of clk81. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org> | |||||
 |
index : op-kernel-dev | |
| Development kernel branch for OpenPOWER systems | Raptor Engineering, LLC |
| summaryrefslogtreecommitdiffstats |
|