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* ARM: dts: meson8: add the USB reset lineMartin Blumenstingl2018-02-121-0/+2
| | | | | | | | | Now that we support the reset controller on Meson8 we can add the reset line to the USB PHYs (just like on Meson8b). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add the reset controllerMartin Blumenstingl2018-02-121-0/+7
| | | | | | | | | | Meson8 uses the same reset controller as Meson8b. Add the node along with the #include for the reset lines to meson8.dtsi so we can use it from there as well. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: enable the GPIO interrupt controllerMartin Blumenstingl2017-12-111-0/+5
| | | | | | | | | | This enables the GPIO interrupt controller for the Meson8 SoCs. Interrupt support on the GPIOs can be used by the MMC framework to detect when an SD card is inserted/removed or by the input framework to detect button presses. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: use stable UART bindings with correct gate clockMartin Blumenstingl2017-12-061-4/+12
| | | | | | | | | | Switch to the stable UART bindings and add the correct gate clocks to the non-AO UART nodes. This fixes the non-AO UARTs if the bootloader didn't un-gate the clocks. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: drop "sana" clock from SAR ADCXingyu Chen2017-12-061-3/+2
| | | | | | | | | | The SAR ADC modules doesn't require The "sana" clock. Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add more L2 cache settingsMartin Blumenstingl2017-12-061-0/+3
| | | | | | | | | | | | | | | | | | | | Amlogic's vendor kernel prints these PL310 L2 cache controller settings during boot: 8 ways, 4096 sets, CACHE_ID 0x4100a0c9, Cache size: 1048576 B AUX_CTRL 0x7ec80001, PERFETCH_CTRL 0x71000007, POWER_CTRL 0x00000000 TAG_LATENCY 0x00000111, DATA_LATENCY 0x00000222 Add the "prefetch-data", "prefetch-instr" and "arm,shared-override" properties to get the same L2 cache controller configuration as the vendor kernel. Two differences still remain: - L310_AUX_CTRL_NS_INT_CTRL is currently not supported by the cache-l2x0 driver - bit 23 is set by the vendor kernel, but this is defined in cache-l2x0.h Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* Merge tag 'amlogic-dt64' of ↵Arnd Bergmann2017-10-301-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt Pull "Amlogic 64-bit platforms: DT updates for v4.15" from Kevin Hilman: - new SoC support: A113D - new boards: Tronsmart Vega S96, Khadas vim2 - reserved memory fixups - gpio-names cleanups - MMC cleanups, enable high-speed modes - misc cleanups * tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: arm64: dts: meson-axg: add initial A113D SoC DT support dt-bindings: arm: amlogic: Add Meson AXG binding ARM64: dts: meson-gx: remove unnecessary uart compatible ARM64: dts: meson-gx: remove unnecessary clocks properties ARM64: dts: meson-gxl: Add alternate ARM Trusted Firmware reserved memory zone ARM64: dts: meson-gxm: enable HS400 on the vim2 ARM64: dts: meson-gxbb-nexbox-a95x: Enable USB Nodes dt-bindings: arm: amlogic: Add Tronsmart Vega S96 binding ARM64: dts: meson-gxm: Add Vega S96 board ARM64: dts: meson-gxm: Add support for Khadas VIM2 ARM64: dts: meson-gxl: Take eMMC data strobe out of eMMC pins ARM64: dts: meson-gxl: adjust libretech-cc gpio-line-names ARM64: dts: meson-gxl: adjust kvim gpio-line-names ARM64: dts: meson-gxbb: adjust odroid-c2 gpio-line-names ARM64: dts: meson-gxbb: adjust nanopi-k2 gpio-line-names ARM64: dts: meson-gx: adjust gpio-ranges for TEST_N ARM64: dts: meson-gx: remove gpio offset ARM: dts: meson8: remove gpio offset ARM64: dts: meson-gxl-libretech-cc: enable internal phy leds ARM64: dts: meson-gxl-libretech-cc: enable saradc
| * ARM: dts: meson8: remove gpio offsetJerome Brunet2017-10-111-1/+1
| | | | | | | | | | | | | | | | | | Remove pin offset on the AO controller. meson pinctrl no longer has this quirk Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add the efuse nodeMartin Blumenstingl2017-10-291-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Meson6, Meson8 and Meson8b use a similar IP block which has access to 512 bytes of efuse data. During SoC manufacturing some calibration settings for the CVBS connector and the internal temperature sensor are written to this efuse. On some boards it additionally stores for example the MAC addresses. The efuse is enabled on Meson8 and Meson8b but kept disabled on Meson6 since we do not have a clock driver there (which is required to read data from the efuse). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson8: add support for booting the secondary CPU coresMartin Blumenstingl2017-10-291-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Booting the secondary CPU cores involves the following nodes/devices: - SCU (Snoop-Control-Unit, for which we already have a DT node) - a reset line for each CPU core, provided by the reset-controller which is built into the clock-controller - the PMU (power management unit) which controls the power of the CPU cores - a range in the SRAM specifically reserved for booting secondary CPU cores - the "enable-method" which activates booting the secondary CPU cores This adds all required nodes and properties to boot the secondary CPU cores. Suggested-by: Carlo Caione <carlo@caione.org> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add the SDIO MMC controllerMartin Blumenstingl2017-10-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Meson6, Meson8 and Meson8b are using the same MMC controller IP. This adds the MMC controller node to meson.dtsi so it can be used by all SoCs. The controller itself is a bit special, because it has multiple slots. Each slot is accessed through a sub-node of the controller. However, currently the driver for this hardware only supports one slot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* | ARM: dts: meson: add SoC information nodesMartin Blumenstingl2017-10-061-0/+5
|/ | | | | | | | | | | | | | | | The SoC type and version information is encoded in different register blocks. The SoC type information is part of the "assist" registers. The misc version information is part of the "bootrom" registers. On Meson8, Meson8b and Meson8m2 there is additionally information about the minor version. This information is stored in the "analog top" registers. Add the nodes for these register blocks so we can decode the SoC type and version information. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: mark the clock controller also as reset controllerMartin Blumenstingl2017-08-011-0/+1
| | | | | | | | | The clock controller provides a few reset lines as well. Add the corresponding CPU cores. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add the PWM controller nodesMartin Blumenstingl2017-07-281-0/+15
| | | | | | | | | | | pwm_ab and pwm_cd are already inherited from meson.dtsi, we only need to define the correct "compatible" string so the pwm-meson driver can choose the parent clocks correctly. pwm_ef is added to meson8.dtsi directly (similar to how it's done in meson8b.dtsi) as this controller only exists on Meson8 and Meson8b. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8bMartin Blumenstingl2017-06-161-1/+1
| | | | | | | | | | | Until now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use CLKID_ETH for both SoCs, which is the real gate clock for the ethernet controller. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8b: add the SCU device nodeMartin Blumenstingl2017-06-161-0/+5
| | | | | | | | | | Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add USB support on Meson8 and Meson8bMartin Blumenstingl2017-06-161-0/+24
| | | | | | | | | | | | | This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add the hardware random number generatorMartin Blumenstingl2017-06-161-0/+6
| | | | | | | | | | | | | All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add reserved memory zonesMartin Blumenstingl2017-06-161-0/+27
| | | | | | | | | | | | | | | | | | | | | | | There seem to be two memory regions that need to be reserved, otherwise the system just hangs when running: $ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \ --vm-keep -m 1 The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources. The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state. This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: add the SAR ADCMartin Blumenstingl2017-06-161-0/+8
| | | | | | | | | | This adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add the pins for the SDIO controllerMartin Blumenstingl2017-06-161-0/+24
| | | | | | Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add the PWM_E and PWM_F pinsMartin Blumenstingl2017-06-161-0/+14
| | | | | | | | | | | This adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to meson8.dtsi, allowing devices to use them. PWM_E can be used on some devices to generate the 32.768kHz clock for the SDIO wifi module, while PWM_F can be used to control the power LED. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: use C preprocessor friendly include syntaxMartin Blumenstingl2017-06-161-1/+1
| | | | | | | | | | | This replaces the "/include/" syntax with the "#include" syntax in all Amlogic Meson .dts and .dtsi files. That is required to use preprocessor defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files which directly or indirectly include meson.dtsi need to use the "#include" syntax, otherwise the .dts files cannot be compiled). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: fix the IR receiver pinsMartin Blumenstingl2017-06-161-7/+7
| | | | | | | | | | | | The IR receiver pins are currently defined in the CBUS pin-controller. However the pins are in the AO region, which is controlled by the AOBUS pin-controller. Move the pins to pinctrl_aobus so they can actually be used. Fixes: b60e1157d8fa ("ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add and use the real clock controllerMartin Blumenstingl2017-06-091-16/+16
| | | | | | | | | | This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8bCarlo Caione2017-05-261-0/+6
| | | | | | | | | | | This patch extends the L2 cache controller node for the Amlogic Meson8 and Meson8b SoCs with some missing parameters. These are taken from the Amlogic GPL kernel source. Signed-off-by: Carlo Caione <carlo@endlessm.com> [apply the change to Meson8 and Meson8b and updated description] Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson: organize devices in their corresponding bussesMartin Blumenstingl2017-05-261-38/+78
| | | | | | | | | | | | | | | | | | The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: Add gpio-ranges propertiesNeil Armstrong2017-03-281-0/+2
| | | | | | Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8bCarlo Caione2016-03-301-25/+32
| | | | | | Signed-off-by: Carlo Caione <carlo@endlessm.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Tested-by: Kevin Hilman <khilman@baylibre.com>
* ARM: dts: meson8: add pinctrl nodeBeniamino Galvani2015-03-021-0/+68
| | | | | | | | Add pinctrl node to the DTSI file for meson8 and sub-nodes for some standard mux configurations. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Signed-off-by: Carlo Caione <carlo@endlessm.com>
* ARM: meson: DTS: enable L2 cacheBeniamino Galvani2014-11-181-0/+4
| | | | | | | | This enables the L2 cache controller available in Amlogic SoCs. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
* ARM: dts: add dtsi for Amlogic Meson8 SoCsBeniamino Galvani2014-11-181-0/+88
This adds a dtsi for Amlogic Meson8 SoCs. It differs from the Meson6 dtsi for the number of Cortex-A9 cores (4 vs 2) and for the frequency of clk81. Signed-off-by: Beniamino Galvani <b.galvani@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Carlo Caione <carlo@caione.org>
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