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* ARM: dts: Add Exynos4210 SoC camera port pinctrl nodesAndrzej Hajda2013-08-071-0/+23
| | | | | | | | | | | Add pinctrl nodes for the camera parallel port CAM_A data bus and the CAM_A_CLKOUT clock output pin. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: dts: Add LCD related pinctrl entries for exynos4210Sachin Kamat2013-06-191-0/+61
| | | | | | | | Adds pinctrl entries required by FIMD. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: dts: Add PWM related pinctrl entries for exynos4210Sachin Kamat2013-06-191-0/+28
| | | | | | | | PWM nodes are added to EXYNOS4210 pinctrl DT file. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: dts: Use drive strength 3 for SD pins for exynos4Tomasz Figa2012-11-221-28/+28
| | | | | | | | | | | | | | | This patch modifies pin control groups of SD pins on EXYNOS4210 and EXYNOS4X12 to use drive strength 3 as a default value which corresponds to S5P_GPIO_DRVSTR_LV4 in legacy non-DT code. This is needed at least on Origen board for sdhci2 to work and if any other drive strength is required on each board, we can overide it. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: edited commit message] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* pinctrl: samsung: Use per-bank IRQ domain for wake-up interruptsTomasz Figa2012-10-151-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks wake-up interrupt handling in pinctrl-exynos driver, so each pin bank, which provides wake-up interrupts, has its own IRQ domain. Information about whether given pin bank provides wake-up interrupts, how many and whether they are separate or muxed are parsed from device tree. It gives following advantages: - interrupts can be specified in device tree in a more readable way, e.g. : device { /* ... */ interrupt-parent = <&gpx2>; interrupts = <4 0>; /* ... */ }; - the amount and layout of interrupts is not hardcoded in the code anymore, but defined in SoC-specific structure - bank and pin of each wake-up interrupt can be easily identified, to allow operations, such as setting the pin to EINT function, from irq_set_type() callback Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: exynos4210-pinctrl: Add nodes for pin banksTomasz Figa2012-10-151-0/+272
| | | | | | | | | | | This patch is a preparation for converting the pinctrl-samsung driver to one GPIO chip and IRQ domain per bank. It allows particular banks to be specified using their phandles. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Reviewed-by: Kyungmin Park <kyungmin.park@samsung.com> Acked-by: Thomas Abraham <thomas.abraham@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
* ARM: dts: Add pinctrl node entries for SAMSUNG EXYNOS4210 SoCThomas Abraham2012-09-071-0/+457
Add pinctrl driver nodes for the three instances of pin controllers in SAMSUNG EXYNOS4210 SoC and add the pin group nodes available in the each of those three instances. Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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