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* Merge branch 'for-v3.16/ti-clk-drv' of github.com:t-kristo/linux-pm into ↵Mike Turquette2014-06-101-12/+12
|\ | | | | | | clk-next
| * ARM: dts: OMAP5/DRA7: use omap5-mpu-dpll-clock capable of dealing with ↵Nishanth Menon2014-06-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | higher frequencies OMAP5432, DRA75x and DRA72x have MPU DPLLs that need Duty Cycle Correction(DCC) to operate safely at frequencies >= 1.4GHz. Switch to "ti,omap5-mpu-dpll-clock" compatible property which provides this support. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
| * ARM: dts: dra7xx-clocks: Correct name for atl clkin3 clockPeter Ujfalusi2014-05-281-11/+11
| | | | | | | | | | | | | | | | To allign the name with the other atl clock names: atlclkin3_ck -> atl_clkin3_ck Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
* | ARM: dts: dra7-clock: Add "l3init_960m_gfclk" clock gateRoger Quadros2014-05-141-2/+10
|/ | | | | | | | | | | | | | | | | This clock gate description is missing in the older Reference manuals. It is present on the SoC to provide 960MHz reference clock to the internal USB PHYs. Reference: DRA75x_DRA74x_ES1.1_NDA_TRM_vO.pdf, pg. 900, Table 3-812. CM_COREAON_L3INIT_60M_GFCLK_CLKCTRL Use l3init_960m_gfclk as parent of usb_otg_ss1_refclk960m and usb_otg_ss2_refclk960m. CC: Benoît Cousson <bcousson@baylibre.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: dra7xx-clocks: Correct mcasp2_ahclkx_mux bit-shiftPeter Ujfalusi2014-04-181-1/+1
| | | | | | | | The correct bit is 24 for AHCLKX. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: dts: DRA7: Add PCIe related clock nodesJ Keerthy2014-01-171-0/+25
| | | | | | | | | | | | This patch adds optfclk_pciephy_clk and optfclk_pciephy_div_clk which are used by PCIe phy. It also adds a mux clock to choose the source of optfclk_pciephy_div_clk clock. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* ARM: dts: DRA7: Change apll_pcie_m2_ck to fixed factor clockJ Keerthy2014-01-171-6/+3
| | | | | | | | | | | This patch changes apll_pcie_m2_ck to fixed factor clock as there are no configurable divider associated to m2. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* ARM: dts: clk: Add apll related clocksJ Keerthy2014-01-171-3/+11
| | | | | | | | | | The patch adds a mux node to choose the parent of apll_pcie_ck node. Signed-off-by: J Keerthy <j-keerthy@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* ARM: dts: dra7 clock dataTero Kristo2014-01-171-0/+1985
This patch creates a unique node for each clock in the DRA7 power, reset and clock manager (PRCM). TODO: apll_pcie clock node is still a dummy in this version, and proper support for the APLL should be added. Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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