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* Merge tag 'dt-for-linus' of ↵Linus Torvalds2015-02-171-1/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
| * ARM: dts: berlin: add PPI cpu mask to twd timer interruptsJisheng Zhang2015-01-071-1/+1
| | | | | | | | | | | | | | | | | | | | According to the gic binding document, "bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of the 8 possible cpus attached to the GIC. A bit set to '1' indicated the interrupt is wired to that CPU." This patch wants to add the PPI cpu mask for completeness. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
| * ARM: dts: berlin: add pmu node for BG2Q and BG2CDJisheng Zhang2015-01-071-0/+8
| | | | | | | | | | | | | | | | This patch adds the pmu node, enabling the PMU unit on Marvell BG2Q and BG2CD SoCs. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | ARM: dts: berlin: correct BG2Q's SM GPIO location.Jisheng Zhang2015-01-071-30/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpio4 and gpio5 are in 0xf7fc0000 apb which is located in the SM domain. This patch moves gpio4 and gpio5 to the correct location. This patch also renames them as the following to match the names we internally used in marvell: gpio4 -> sm_gpio1 gpio5 -> sm_gpio0 porte -> portf portf -> porte This also matches what we did for BG2 and BG2CD's SM GPIO. Cc: stable@vger.kernel.org # 3.16+ Fixes: cedf57fc4f2f ("ARM: dts: berlin: add the BG2Q GPIO nodes") Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* | ARM: dts: berlin: fix io clk and add missing core clk for BG2Q sdhci2 hostJisheng Zhang2015-01-071-1/+2
|/ | | | | | | | | | On BG2Q, the sdhci2 host uses nfcecc for "io" clk and nfc for "core" clk. The shdci2 can't work without this patch due to the "core" clk is gated. Cc: stable@vger.kernel.org # 3.16+ Fixes: 0d859a6a9d14 ("ARM: dts: berlin: add the SDHCI nodes for the BG2Q") Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add BG2Q nodes for USB supportAntoine Tenart2014-11-181-0/+54
| | | | | | | | Adds nodes describing the Marvell Berlin BG2Q USB PHY and USB. The BG2Q SoC has 3 USB host controller, compatible with ChipIdea. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: Add phy-connection-type to BG2Q EthernetAntoine Ténart2014-10-291-0/+1
| | | | | | | | | Internal FastEthernet PHY on BG2Q is connected via MII, add a corresponding phy-connection-type property to the Ethernet node. Tested-by: Antoine Ténart <antoine.tenart@free-electrons.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: enable timer 1 for sched_clockAntoine Ténart2014-10-291-1/+0
| | | | | | | | Enable timer 1 to be the source for the sched_clock, allowing to have a more precise value than 1/HZ. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add a required reset property in the chip controller nodeAntoine Ténart2014-10-291-0/+1
| | | | | | | | | The chip controller node now also describes the Marvell Berlin reset controller. Add the required 'reset-cells' property. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add the AHCI node for the BG2QAntoine Ténart2014-10-291-0/+39
| | | | | | | | The BG2Q has an AHCI SATA controller. Add the corresponding nodes (AHCI, PHY) into its device tree. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add the Ethernet nodeAntoine Ténart2014-09-301-0/+17
| | | | | | | | | This patch adds the Ethernet node, enabling the network unit on Berlin BG2Q SoCs. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* ARM: dts: berlin: add SMP related nodes and properties for BG2QAntoine Ténart2014-06-161-0/+6
| | | | | | | | | Add required nodes and properties into the Berlin BG2Q device tree to take advantage of the newly introduced SMP support. Add the scu and cpu-ctrl nodes along with the CPUs enable-method property. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add I2C nodes for BG2QAntoine Ténart2014-06-161-0/+72
| | | | | | | | | | | The Marvell Berlin BG2Q has 4 TWSI compatible with the Synopsys DesignWare I2C driver. Add the corresponding nodes. The pin-muxing setup is also done here, since there cannot be another muxing setup if I2C{0,1,2,3} are enabled. Signed-off-by: Antoine Ténart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin2q: set L2CC tag and data latency to 2 cyclesJisheng Zhang2014-06-161-0/+2
| | | | | | | For all BG2Q SoCs, 2 cycles is the best/correct value. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add the SDHCI nodes for the BG2QAntoine Tenart2014-05-191-0/+24
| | | | | | | | Add the SDHCI nodes for the Marvell Berlin BG2Q, using the mrvl,pxav3-mmc driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add the pinctrl node and muxing setup for uartsAntoine Tenart2014-05-191-0/+19
| | | | | | | | | Add pinctrl bindings and system control nodes to what we currently know about Berlin SoCs. Where available, also set default pinctrl property for uarts, when there is only one pinmux option for it. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: convert BG2Q to DT clock nodesAlexandre Belloni2014-05-191-35/+19
| | | | | | | | This converts Berlin BG2Q SoC dtsi to make use of the new DT clock nodes for Berlin SoCs. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add the BG2Q GPIO nodesAntoine Tenart2014-05-191-0/+102
| | | | | | | | | The Marvell Berlin BG2Q has 6 GPIO ports compatible with the snps,dw-apb-gpio driver. This patch adds the corresponding device tree nodes. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Reviewed-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* ARM: dts: berlin: add scu and chipctrl device nodes for BG2/BG2QSebastian Hesselbarth2014-05-191-0/+10
| | | | | | | | | | | | This adds scu and general purpose registers device nodes required for SMP on Berlin BG2 and BG2Q SoCs. The secondary CPUs will pick their jump address from general purpose (SW generic) register 1. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Antoine Tenart <antoine.tenart@free-electrons.com> Acked-by: Jisheng Zhang <jszhang@marvell.com> Tested-by: Antoine Tenart <antoine.tenart@free-electrons.com>
* ARM: dts: berlin: add the Marvell Armada 1500 proAntoine Tenart2014-05-191-0/+224
Adds initial support for the Marvell Armada 1500 pro (BG2Q) SoC (Berlin family). The SoC has nodes for cpu, l2 cache controller, interrupt controllers, local timer, apb timers and uarts for now. Also add corresponding binding documentation. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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