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* ARM: mvebu: use DT properties to fine-tune the L2 configurationThomas Petazzoni2015-07-091-0/+4
| | | | | | | | | | | | | | In order to optimize the L2 cache performance, this commit adjusts the configuration of the L2 on the Cortex-A9 based Marvell EBU processors (Armada 375, 38x and 39x), using the appropriate DT properties. We enable double linefill, incr double linefill, data prefetch and disable double linefill on wrap. This matches the configuration that was fine tuned in the Marvell BSP. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* ARM: mvebu: use armada-380-xor on Armada 38x and 39xThomas Petazzoni2015-07-091-2/+2
| | | | | | | | | | | | The Armada 38x and 39x SoC support have an updated XOR hardware block compared to previous SoCs. These features can be enabled by using the 'armada-380-xor' compatible string, available since commit 6f166312c6ea ("dmaengine: mv_xor: add support for a38x command in descriptor mode"). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* Merge tag 'v4.1-rc6' into next/dtKevin Hilman2015-06-111-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | Linux 4.1-rc6 Conflicts: arch/arm/boot/dts/zynq-7000.dtsi Resolution summary: Mainline had an earlier version of the commit, resolve in favor of the newer patch in next/dt branch.
| * ARM: mvebu: Fix the main PLL frequency on Armada 375, 38x and 39x SoCsGregory CLEMENT2015-05-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whereas for Armada 370 and XP the main PLL frequency was 2GHz for the Armada 375, 38x and 39x, the frequency is 1GHz. When writing support for these last SoCs, there was no official value for the PLL. Now that we have it, this patch fixes it in the device tree. This value is currently only used by the NAND driver for the setting the NAND timing. Fortunately it is not actually used: all the mainline board with a NAND flash comes with a NAND device tree node using the "marvell,nand-keep-config" property. With this property the timings are not modified in the kernel driver and are kept from the bootloader. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Marcin Wojtas <mw@semihalf.com>
* | ARM: mvebu: use improved armada spi device tree compatible name for each SoCGregory CLEMENT2015-05-271-2/+4
|/ | | | | | | Use the new compatible introduced in order to benefit of a wider and more accurate range of baud rates to be used. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
* ARM: mvebu: add Device Tree files for Armada 39x SoC and boardThomas Petazzoni2015-03-041-0/+508
This commit adds the Device Tree files for the Armada 39x family of processors, as well as one Armada 398 Development Board. Like for other Marvell EBU families, a common armada-39x.dtsi contains the description of the common features of all Armada 39x SoCs, while armada-390.dtsi and armada-398.dtsi respectively describe the specificities of those SoCs. Finally, an armada-398-db.dts file is added to describe the Armada 398 Development Board itself. So far, the following features are supported: * SMP: dual Cortex-A9 * Basic ARM IPs: SCU, timer, GIC, L2 cache * Basic Marvell IPs: pin-muxing, clocks, system controller, MBus controller, MPIC interrupt controller, timer, CPU reset for SMP, PMSU. * I2C * SPI * SDHCI * XOR * NAND * UART * PCIe Additional features will be supported in the future. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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