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* Fix common misspellingsLucas De Marchi2011-03-311-1/+1
| | | | | | Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
* [ARM] 4532/1: allow configuration of processor IDGreg Ungerer2007-10-121-1/+1
| | | | | | | | Allow for configuration of the processor ID for the simplar non-MMU ARM parts. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: manage the CP15 thingsHyok S. Choi2006-09-271-0/+8
| | | | | | | | | | | | | | | | | | | | | | | All the current CP15 access codes in ARM arch can be categorized and conditioned by the defines as follows: Related operation Safe condition a. any CP15 access !CPU_CP15 b. alignment trap CPU_CP15_MMU c. D-cache(C-bit) CPU_CP15 d. I-cache CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 || CPU_ARM720 || CPU_ARM740 || CPU_XSCALE || CPU_XSC3 ) e. alternate vector CPU_CP15 && !CPU_ARM740 f. TTB CPU_CP15_MMU g. Domain CPU_CP15_MMU h. FSR/FAR CPU_CP15_MMU For example, alternate vector is supported if and only if "CPU_CP15 && !CPU_ARM740" is satisfied. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: fixups for the exception vectorsHyok S. Choi2006-03-271-0/+17
| | | | | | | | | The high page vector (0xFFFF0000) does not supported in nommu mode. This patch allows the vectors to be 0x00000000 or the begining of DRAM in nommu mode. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* [ARM] nommu: add nommu specific Kconfig and MMUEXT variable in MakefileHyok S. Choi2006-03-271-0/+27
This patch adds Kconfig-nommu for noMMU specific configurations and MMUEXT variable into Makefile. Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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