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* ARC: build: Better way to detect ISA compatible toolchainVineet Gupta2016-03-121-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | ARC architecture has 2 instruction sets: ARCompact/ARCv2. While same gcc supports compiling for either (using appropriate toggles), we can't use the same toolchain to build kernel because libgcc needs to be unique and the toolchian (uClibc based) is not multilibed. uClibc toolchain is convenient since it allows all userspace and kernel to be built with a single install for an ISA. This however means 2 gnu installs (with same triplet prefix) are needed for building for 2 ISA and need to be in PATH. As developers we keep switching the builds, but would occassionally fail to update the PATH leading to usage of wrong tools. And this would only show up at the end of kernel build when linking incompatible libgcc. So the initial solution was to have gcc define a special preprocessor macro DEFAULT_CPU_xxx which is unique for default toolchain configuration. Claudiu proposed using grep for an existing preprocessor macro which is again uniquely defined per ISA. Cc: Michal Marek <mmarek@suse.cz> Suggested-by: Claudiu Zissulescu <claziss@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: boot report CCMs (Closely Coupled Memories)Vineet Gupta2016-02-181-12/+20
| | | | | | | | | - ARCv2 uses a seperate BCR for {I,D}CCM base address: ARCompact encoded both base/size in same BCR - Size encoding in common BCR is different for ARCompact/ARCv2 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: shrink cpuinfo by not saving full timer BCRVineet Gupta2016-01-291-2/+1
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: boot log: decode more mmu config itemsVineet Gupta2015-10-171-1/+1
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: mm: compute TLB size as needed from ways * setsVineet Gupta2015-10-171-2/+2
| | | | | | | This frees up some bits to hold more high level info such as PAE being present, w/o increasing the size of already bloated cpuinfo struct Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: make write_aux_reg safer against macro substitutionVineet Gupta2015-10-171-1/+1
| | | | | | It was generating warnings when called as write_aux_reg(x, paddr >> 32) Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: Support IO Coherency and permutations involving L1 and L2 cachesAlexey Brodkin2015-08-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of ARCv2 CPU there're could be following configurations that affect cache handling for data exchanged with peripherals via DMA: [1] Only L1 cache exists [2] Both L1 and L2 exist, but no IO coherency unit [3] L1, L2 caches and IO coherency unit exist Current implementation takes care of [1] and [2]. Moreover support of [2] is implemented with run-time check for SLC existence which is not super optimal. This patch introduces support of [3] and rework of DMA ops usage. Instead of doing run-time check every time a particular DMA op is executed we'll have 3 different implementations of DMA ops and select appropriate one during init. As for IOC support for it we need: [a] Implement empty DMA ops because IOC takes care of cache coherency with DMAed data [b] Route dma_alloc_coherent() via dma_alloc_noncoherent() This is required to make IOC work in first place and also serves as optimization as LD/ST to coherent buffers can be srviced from caches w/o going all the way to memory Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> [vgupta: -Added some comments about IOC gains -Marked dma ops as static, -Massaged changelog a bit] Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: Fix the peripheral address space detectionVineet Gupta2015-08-031-4/+3
| | | | | | | | With HS 2.1 release, the peripheral space register no longer contains the uncached space specifics, causing the kernel to panic early on. So read the newer NON VOLATILE AUX register to get that info. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: MMUv4: cache programming model changesVineet Gupta2015-06-221-2/+3
| | | | | | | | | | | | | | | Caveats about cache flush on ARCv2 based cores - dcache is PIPT so paddr is sufficient for cache maintenance ops (no need to setup PTAG reg - icache is still VIPT but only aliasing configs need PTAG setup So basically this is departure from MMU-v3 which always need vaddr in line ops registers (DC_IVDL, DC_FLDL, IC_IVIL) but paddr in DC_PTAG, IC_PTAG respectively. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: MMUv4: TLB programming Model changesVineet Gupta2015-06-221-1/+1
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: Support for ARCv2 ISA and HS38x coresVineet Gupta2015-06-221-4/+49
| | | | | | | | | | | | | | | | | | The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARCv2: [intc] HS38 core interrupt controllerVineet Gupta2015-06-221-0/+1
| | | | | | Cc: Jason Cooper <jason@lakedaemon.net> Cc: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: uncached base is hard constant for ARC, don't save itVineet Gupta2015-06-221-1/+0
| | | | | | | ioremap already uses the hard define, just make sure BCR value matches that Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: entry.S: Introduce INTERRUPT_{PROLOGUE,EPILOGUE}Vineet Gupta2015-06-191-3/+0
| | | | | | -common'ize macros for level 1 and level 2 interrupts Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: compress cpuinfo_arc_mmu (mainly save page size in KB)Vineet Gupta2015-06-191-1/+2
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Fix RTT boot printingVineet Gupta2015-04-131-0/+1
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: cosmetic: Remove unused ECR bitfield masksVineet Gupta2015-04-131-6/+3
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Fix WRITE_BCRVineet Gupta2015-04-131-2/+2
| | | | | | | * There was obvious bit rot due to lack of use * Old naming was confusing since BCR are read only Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: boot: cpu feature print enhancementsVineet Gupta2014-10-131-24/+53
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: unbork FPU save/restoreVineet Gupta2014-10-131-8/+0
| | | | | | Fixes: 2ab402dfd65d15a4b2 "ARC: make start_thread() out-of-line" CC: <stable@vger.kernel.org> #3.16 Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: remove extraneous __KERNEL__ guardsVineet Gupta2014-10-131-4/+0
| | | | | Verified by doing make headers_install as none of these files are exported to userspace
* ARC: cache boot reporting updatesVineet Gupta2014-07-231-1/+1
| | | | | | | | * print aliasing or not, VIPT/PIPT etc * compress param storage using bitfields * more use of IS_ENABLED to de-uglify code Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: pt_regs update #5: Use real ECR for pt_regs->event vs. synth valuesVineet Gupta2013-06-261-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pt_regs->event was set with artificial values to identify the low level system event (syscall trap / breakpoint trap / exceptions / interrupts) With r8 saving out of the way, the full word can be used to save real ECR (Exception Cause Register) which helps idenify the event naturally, including additional info such as cause code, param. Only for Interrupts, where ECR is not applicable, do we resort to synthetic non ECR values. SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with different runtime values. The ptrace helpers now use the sub-fields of ECR to distinguish the events (e.g. vector 0x25 is trap, param 0 is syscall...) The following benefits will follow: (1) This centralizes the location of where ECR is saved and will allow the cleanup of task->thread.cause_code ECR placeholder which is set in non-uniform way. Then ARC VM code can safely rely on it being there for purpose of finer grained VM_EXEC dcache flush (based on exec fault: I-TLB Miss) (2) Further, ECR being passed around from low level handlers as arg can be eliminated as it is part of standard reg-file in pt_regs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Entry Handler tweaks: Avoid hardcoded LIMMS for ECR valuesVineet Gupta2013-06-221-0/+5
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: cache detection code bitrotVineet Gupta2013-06-221-1/+1
| | | | | | | | | * Number of (i|d)cache ways can be retrieved from BCRs and hence no need to cross check with with built-in constants * Use of IS_ENABLED() to check for a Kconfig option * is_not_cache_aligned() not used anymore Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Disintegrate arcregs.hVineet Gupta2013-06-221-116/+0
| | | | | | | | | * Move the various sub-system defines/types into relevant files/functions (reduces compilation time) * move CPU specific stuff out of asm/tlb.h into asm/mmu.h Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Boot #2: Verbose Boot reporting / feature verificationVineet Gupta2013-02-151-10/+112
| | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Boot #1: low-level, setup_arch(), /proc/cpuinfo, mem initVineet Gupta2013-02-151-0/+5
| | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
* ARC: MMU Exception HandlingVineet Gupta2013-02-151-0/+91
| | | | | | | | | * MMU I-TLB / D-TLB Miss Exceptions - Fast Path TLB Refill Handler - slowpath TLB creation via do_page_fault() -> update_mmu_cache() * Duplicate PD Exception Handler Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: MMU Context ManagementVineet Gupta2013-02-151-0/+7
| | | | | | | | | | | | ARC700 MMU provides for tagging TLB entries with a 8-bit ASID to avoid having to flush the TLB every task switch. It also allows for a quick way to invalidate all the TLB entries for task useful for: * COW sementics during fork() * task exit()ing Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Cache Flush ManagementVineet Gupta2013-02-151-0/+80
| | | | | | | | | * ARC700 has VIPT L1 Caches * Caches don't snoop and are not coherent * Given the PAGE_SIZE and Cache associativity, we don't support aliasing D$ configurations (yet), but do allow aliasing I$ configs Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
* ARC: Timers/counters/delay managementVineet Gupta2013-02-111-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARC700 includes 2 in-core 32bit timers TIMER0 and TIMER1. Both have exactly same capabilies. * programmable to count from TIMER<n>_CNT to TIMER<n>_LIMIT * for count 0 and LIMIT ~1, provides a free-running counter by auto-wrapping when limit is reached. * optionally interrupt when LIMIT is reached (oneshot event semantics) * rearming the interrupt provides periodic semantics * run at CPU clk ARC Linux uses TIMER0 for clockevent (periodic/oneshot) and TIMER1 for clocksource (free-running clock). Newer cores provide RTSC insn which gives a 64bit cpu clk snapshot hence is more apt for clocksource when available. SMP poses a bit of challenge for global timekeeping clocksource / sched_clock() backend: -TIMER1 based local clocks are out-of-sync hence can't be used (thus we default to jiffies based cs as well as sched_clock() one/both of which platform can override with it's specific hardware assist) -RTSC is only allowed in SMP if it's cross-core-sync (Kconfig glue ensures that) and thus usable for both requirements. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Process-creation/scheduling/idle-loopVineet Gupta2013-02-111-0/+20
| | | | | | Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Al Viro <viro@ZenIV.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: Interrupt HandlingVineet Gupta2013-02-111-0/+3
| | | | | | | | | | This contains: -bootup arch IRQ init: init_IRQ(), arc_init_IRQ() -generic IRQ subsystem glue: arch_do_IRQ() -basic IRQ chip setup for in-core intc Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
* ARC: irqflags - Interrupt enabling/disabling at in-core intcVineet Gupta2013-02-111-0/+114
ARC700 has an in-core intc which provides 2 priorities (a.k.a.) "levels" of interrupts (per IRQ) hencforth referred to as L1/L2 interrupts. CPU flags register STATUS32 has Interrupt Enable bits per level (E1/E2) to globally enable (or disable) all IRQs at a level. Hence the implementation of arch_local_irq_{save,restore,enable,disable}( ) The STATUS32 reg can be r/w only using the AUX Interface of ARC, hence the use of LR/SR instructions. Further, E1/E2 bits in there can only be updated using the FLAG insn. The intc supports 32 interrupts - and per IRQ enabling is controlled by a bit in the AUX_IENABLE register, hence the implmentation of arch_{,un}mask_irq( ) routines. Signed-off-by: Vineet Gupta <vgupta@synopsys.com> Cc: Thomas Gleixner <tglx@linutronix.de>
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