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* powerpc/8xx: Adding support of IRQ in MPC8xx GPIOChristophe Leroy2017-05-021-1/+20
| | | | | | | | | | | | | | | | | | | | | | | This patch allows the use of IRQ to notify the change of GPIO status on MPC8xx CPM IO ports. This then allows to associate IRQs to GPIOs in the Device Tree. Ex: CPM1_PIO_C: gpio-controller@960 { #gpio-cells = <2>; compatible = "fsl,cpm1-pario-bank-c"; reg = <0x960 0x10>; fsl,cpm1-gpio-irq-mask = <0x0fff>; interrupts = <1 2 6 9 10 11 14 15 23 24 26 31>; interrupt-parent = <&CPM_PIC>; gpio-controller; }; The property 'fsl,cpm1-gpio-irq-mask' defines which of the 16 GPIOs have the associated interrupts defined in the 'interrupts' property. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Scott Wood <oss@buserror.net>
* dt-bindings: qman: Remove pool channel nodeScott Wood2017-01-091-20/+0
| | | | | | | No device tree has these, nor does any driver look for them. Signed-off-by: Scott Wood <oss@buserror.net> Signed-off-by: Rob Herring <robh@kernel.org>
* dt: bindings: move guts devicetree doc out of powerpc directoryyangbo lu2016-11-291-0/+44
| | | | | | | | | | | | Move guts devicetree doc to Documentation/devicetree/bindings/soc/fsl/ since it's used by not only PowerPC but also ARM. And add a specification for 'little-endian' property. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Scott Wood <oss@buserror.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* bindings: move cpm_qe binding from powerpc/fsl to soc/fslZhao Qiang2016-07-0915-0/+779
| | | | | | | | | | | cpm_qe is supported on both powerpc and arm. and the QE code has been moved from arch/powerpc into drivers/soc/fsl, so move cpm_qe binding from powerpc/fsl to soc/fsl Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Acked-by: Rob Herring<robh@kernel.org> Signed-off-by: Scott Wood <oss@buserror.net>
* Documentation: dt: binding: fsl: add devicetree binding for describing RCPMWang Dongsheng2016-03-041-0/+63
| | | | | | | | | | | | | | RCPM is the Run Control and Power Management module performs all device-level tasks associated with device run control and power management. Add this for freescale powerpc platform and layerscape platform. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Wang Dongsheng <dongsheng.wang@freescale.com> [scottwood: s/pointer/phandle and "disabled" status from example] Signed-off-by: Scott Wood <oss@buserror.net>
* powerpc/qman: Change fsl,qman-channel-id to cell-indexScott Wood2015-06-021-2/+2
| | | | | | | | | | | | | | It turns out that existing U-Boots will dereference NULL pointers if the device tree does not have cell-index in the portal nodes. No patch has yet been merged adding device tree nodes for this binding (except a dtsi that has not yet been referenced), nor has any driver yet been merged making use of the binding, so it's not too late to change the binding in order to keep compatibility with existing U-Boots. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Madalin-Cristian Bucur <madalin.bucur@freescale.com>
* dt/bindings: b/qman: Add phandle to the portalsEmil Medve2015-01-292-0/+20
| | | | | | | This supports SoC(s) with multiple B/QMan instances Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* dt/bindings: b/qman: Fix the alloc-ranges in the example(s)Emil Medve2015-01-292-3/+3
| | | | | | | 'ranges' are specified as <base size> not as <start end> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* dt/bindings: Introduce the FSL QorIQ DPAA QMan portal(s)Emil Medve2014-11-121-0/+154
| | | | | | | | | | Portals are memory mapped interfaces to QMan that allow low-latency, lock-less interaction by software running on processor cores, accelerators and network interfaces with the QMan Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I29764fa8093b5ce65460abc879446795c50d7185 Signed-off-by: Scott Wood <scottwood@freescale.com>
* dt/bindings: Introduce the FSL QorIQ DPAA QManEmil Medve2014-11-121-0/+165
| | | | | | | | | | | | | | The Queue Manager is part of the Data-Path Acceleration Architecture (DPAA). QMan supports queuing and QoS scheduling of frames to CPUs, network interfaces and DPAA logic modules, maintains packet ordering within flows. Besides providing flow-level queuing, is also responsible for congestion management functions such as RED/WRED, congestion notifications and tail discards. This binding covers the CCSR space programming model Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I3acb223893e42003d6c9dc061db568ec0b10d29b Signed-off-by: Scott Wood <scottwood@freescale.com>
* dt/bindings: Introduce the FSL QorIQ DPAA BMan portal(s)Emil Medve2014-11-121-0/+56
| | | | | | | | | | Portals are memory mapped interfaces to BMan that allow low-latency, lock-less interaction by software running on processor cores, accelerators and network interfaces with the BMan Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I6d245ffc14ba3d0e91d403ac7c3b91b75a9e6a95 Signed-off-by: Scott Wood <scottwood@freescale.com>
* dt/bindings: Introduce the FSL QorIQ DPAA BManEmil Medve2014-11-121-0/+125
The Buffer Manager is part of the Data-Path Acceleration Architecture (DPAA). BMan supports hardware allocation and deallocation of buffers belonging to pools originally created by software with configurable depletion thresholds. This binding covers the CCSR space programming model Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Change-Id: I3ec479bfb3c91951e96902f091f5d7d2adbef3b2 Signed-off-by: Scott Wood <scottwood@freescale.com>
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