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* Merge tag 'pci-v4.3-changes' of ↵Linus Torvalds2015-08-3164-681/+796
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: "PCI changes for the v4.3 merge window: Enumeration: - Allocate ATS struct during enumeration (Bjorn Helgaas) - Embed ATS info directly into struct pci_dev (Bjorn Helgaas) - Reduce size of ATS structure elements (Bjorn Helgaas) - Stop caching ATS Invalidate Queue Depth (Bjorn Helgaas) - iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth (Bjorn Helgaas) - Move MPS configuration check to pci_configure_device() (Bjorn Helgaas) - Set MPS to match upstream bridge (Keith Busch) - ARM/PCI: Set MPS before pci_bus_add_devices() (Murali Karicheri) - Add pci_scan_root_bus_msi() (Lorenzo Pieralisi) - ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi() (Lorenzo Pieralisi) Resource management: - Call pci_read_bridge_bases() from core instead of arch code (Lorenzo Pieralisi) PCI device hotplug: - pciehp: Remove unused interrupt events (Bjorn Helgaas) - pciehp: Remove ignored MRL sensor interrupt events (Bjorn Helgaas) - pciehp: Handle invalid data when reading from non-existent devices (Jarod Wilson) - pciehp: Simplify pcie_poll_cmd() (Yijing Wang) - Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slot (Yijing Wang) - Protect pci_bus->slots with pci_slot_mutex, not pci_bus_sem (Yijing Wang) - Hold pci_slot_mutex while searching bus->slots list (Yijing Wang) Power management: - Disable async suspend/resume for JMicron multi-function SATA/AHCI (Zhang Rui) Virtualization: - Add ACS quirks for Intel I219-LM/V (Alex Williamson) - Restore ACS configuration as part of pci_restore_state() (Alexander Duyck) MSI: - Add pcibios_alloc_irq() and pcibios_free_irq() (Jiang Liu) - x86: Implement pcibios_alloc_irq() and pcibios_free_irq() (Jiang Liu) - Add helpers to manage pci_dev->irq and pci_dev->irq_managed (Jiang Liu) - Free legacy IRQ when enabling MSI/MSI-X (Jiang Liu) - ARM/PCI: Remove msi_controller from struct pci_sys_data (Lorenzo Pieralisi) - Remove unused pcibios_msi_controller() hook (Lorenzo Pieralisi) Generic host bridge driver: - Remove dependency on ARM-specific struct hw_pci (Jayachandran C) - Build setup-irq.o for arm64 (Jayachandran C) - Add arm64 support (Jayachandran C) APM X-Gene host bridge driver: - Add APM X-Gene PCIe 64-bit prefetchable window (Duc Dang) - Add support for a 64-bit prefetchable memory window (Duc Dang) - Drop owner assignment from platform_driver (Krzysztof Kozlowski) Broadcom iProc host bridge driver: - Allow BCMA bus driver to be built as module (Hauke Mehrtens) - Delete unnecessary checks before phy calls (Markus Elfring) - Add arm64 support (Ray Jui) Synopsys DesignWare host bridge driver: - Don't complain missing *config* reg space if va_cfg0 is set (Murali Karicheri) TI DRA7xx host bridge driver: - Disable pm_runtime on get_sync failure (Kishon Vijay Abraham I) - Add PM support (Kishon Vijay Abraham I) - Clear MSE bit during suspend so clocks will idle (Kishon Vijay Abraham I) - Add support to make GPIO drive PERST# line (Kishon Vijay Abraham I) Xilinx AXI host bridge driver: - Check for MSI interrupt flag before handling as INTx (Russell Joyce) Miscellaneous: - Fix Intersil/Techwell TW686[4589] AV capture class code (Krzysztof Hałasa) - Use PCI_CLASS_SERIAL_USB instead of bare number (Bjorn Helgaas) - Fix generic NCR 53c810 class code quirk (Bjorn Helgaas) - Fix TI816X class code quirk (Bjorn Helgaas) - Remove unused "pci_probe" flags (Bjorn Helgaas) - Host bridge driver code simplifications (Fabio Estevam) - Add dev_flags bit to access VPD through function 0 (Mark Rustad) - Add VPD function 0 quirk for Intel Ethernet devices (Mark Rustad) - Kill off set_irq_flags() usage (Rob Herring) - Remove Intel Cherrytrail D3 delays (Srinidhi Kasagar) - Clean up pci_find_capability() (Wei Yang)" * tag 'pci-v4.3-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (72 commits) PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI PCI: Set MPS to match upstream bridge PCI: Move MPS configuration check to pci_configure_device() PCI: Drop references acquired by of_parse_phandle() PCI/MSI: Remove unused pcibios_msi_controller() hook ARM/PCI: Remove msi_controller from struct pci_sys_data ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi() PCI: Add pci_scan_root_bus_msi() ARM/PCI: Replace panic with WARN messages on failures PCI: generic: Add arm64 support PCI: Build setup-irq.o for arm64 PCI: generic: Remove dependency on ARM-specific struct hw_pci PCI: imx6: Simplify a trivial if-return sequence PCI: spear: Use BUG_ON() instead of condition followed by BUG() PCI: dra7xx: Remove unneeded use of IS_ERR_VALUE() PCI: Remove pci_ats_enabled() PCI: Stop caching ATS Invalidate Queue Depth PCI: Move ATS declarations to linux/pci.h so they're all together PCI: Clean up ATS error handling PCI: Use pci_physfn() rather than looking up physfn by hand ...
| *-. Merge branches 'pci/enumeration' and 'pci/misc' into nextBjorn Helgaas2015-08-2816-129/+148
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/enumeration: PCI: Set MPS to match upstream bridge PCI: Move MPS configuration check to pci_configure_device() PCI: Drop references acquired by of_parse_phandle() PCI/MSI: Remove unused pcibios_msi_controller() hook ARM/PCI: Remove msi_controller from struct pci_sys_data ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi() PCI: Add pci_scan_root_bus_msi() ARM/PCI: Replace panic with WARN messages on failures PCI: generic: Add arm64 support PCI: Build setup-irq.o for arm64 PCI: generic: Remove dependency on ARM-specific struct hw_pci ARM/PCI: Set MPS before pci_bus_add_devices() * pci/misc: PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCI
| | | * PCI: Disable async suspend/resume for JMicron multi-function SATA/AHCIZhang Rui2015-08-243-24/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On multi-function JMicron SATA/PATA/AHCI devices, the PATA controller at function 1 doesn't work if it is powered on before the SATA controller at function 0. The result is that PATA doesn't work after resume, and we print messages like this: pata_jmicron 0000:02:00.1: Refused to change power state, currently in D3 irq 17: nobody cared (try booting with the "irqpoll" option) Async resume was introduced in v3.15 by 76569faa62c4 ("PM / sleep: Asynchronous threads for resume_noirq"). Prior to that, we powered on the functions in order, so this problem shouldn't happen. e6b7e41cdd8c ("ata: Disabling the async PM for JMicron chip 363/361") solved the problem for JMicron 361 and 363 devices. With async suspend disabled, we always power on function 0 before function 1. Barto then reported the same problem with a JMicron 368 (see comment #57 in the bugzilla). Rather than extending the blacklist piecemeal, disable async suspend for all JMicron multi-function SATA/PATA/AHCI devices. This quirk could stay in the ahci and pata_jmicron drivers, but it's likely the problem will occur even if pata_jmicron isn't loaded until after the suspend/resume. Making it a PCI quirk ensures that we'll preserve the power-on order even if the drivers aren't loaded. [bhelgaas: changelog, limit to multi-function, limit to IDE/ATA] Link: https://bugzilla.kernel.org/show_bug.cgi?id=81551 Reported-and-tested-by: Barto <mister.freeman@laposte.net> Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v3.15+
| | * | PCI: Set MPS to match upstream bridgeKeith Busch2015-08-244-8/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Firmware typically configures the PCIe fabric with a consistent Max Payload Size setting based on the devices present at boot. A hot-added device typically has the power-on default MPS setting (128 bytes), which may not match the fabric. The previous Linux default, in the absence of any "pci=pcie_bus_*" options, was PCIE_BUS_TUNE_OFF, in which we never touch MPS, even for hot-added devices. Add a new default setting, PCIE_BUS_DEFAULT, in which we make sure every device's MPS setting matches the upstream bridge. This makes it more likely that a hot-added device will work in a system with optimized MPS configuration. Note that if we hot-add a device that only supports 128-byte MPS, it still likely won't work because we don't reconfigure the rest of the fabric. Booting with "pci=pcie_bus_peer2peer" is a workaround for this because it sets MPS to 128 for everything. [bhelgaas: changelog, new default, rework for pci_configure_device() path] Tested-by: Keith Busch <keith.busch@intel.com> Tested-by: Jordan Hargrave <jharg93@gmail.com> Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Yinghai Lu <yinghai@kernel.org>
| | * | PCI: Move MPS configuration check to pci_configure_device()Bjorn Helgaas2015-08-201-19/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we checked for invalid MPS settings, i.e., a device with MPS different than its upstream bridge, in pcie_bus_detect_mps(). We only did this if the arch or hotplug driver called pcie_bus_configure_settings(), and then only if PCIe bus tuning was disabled (PCIE_BUS_TUNE_OFF). Move the MPS checking code to pci_configure_device(), so we do it in the pci_device_add() path for every device. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: Drop references acquired by of_parse_phandle()Bjorn Helgaas2015-08-202-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_parse_phandle() returns a device_node pointer with the refcount incremented. We should dispose of this reference when we're finished. Drop the reference acquired by of_parse_phandle(). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | PCI/MSI: Remove unused pcibios_msi_controller() hookLorenzo Pieralisi2015-08-201-16/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pcibios_msi_controller() hook was only implemented by ARM, and it sets pci_bus->msi now, so it doesn't need this hook anymore. Remove the unused pcibios_msi_controller() hook. [bhelgaas: changelog, split into separate patch] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | ARM/PCI: Remove msi_controller from struct pci_sys_dataLorenzo Pieralisi2015-08-202-15/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM now uses pci_bus->msi to store the msi_controller pointer, so we don't need to save it in struct pci_sys_data, and we don't need to implement pcibios_msi_controller() to get it out of pci_sys_data. Remove msi_controller from struct pci_sys_data and pcibios_msi_controller(). [bhelgaas: changelog, split into separate patch] Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
| | * | ARM/PCI, designware, xilinx: Use pci_scan_root_bus_msi()Lorenzo Pieralisi2015-08-204-10/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM previously stored the msi_controller pointer in its sysdata, struct pci_sys_data, and implemented pcibios_msi_controller() to retrieve it. That made PCI host controller drivers specific to ARM because they had to put the msi_controller pointer in the ARM-specific pci_sys_data. There is now a generic mechanism, pci_scan_root_bus_msi(), for giving the msi_controller pointer to the PCI core. Use this for all ARM systems and for the DesignWare and Xilinx PCI host controller drivers. This removes an ARM dependency from the DesignWare, DRA7xx, EXYNOS, i.MX6, Keystone, Layerscape, SPEAr13xx, and Xilinx drivers. [bhelgaas: changelog, split into separate patch] Suggested-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Arnd Bergmann <arnd@arndb.de> CC: Simon Horman <horms@verge.net.au> CC: Russell King <linux@arm.linux.org.uk> CC: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Michal Simek <michal.simek@xilinx.com> CC: Marc Zyngier <marc.zyngier@arm.com>
| | * | PCI: Add pci_scan_root_bus_msi()Lorenzo Pieralisi2015-08-202-2/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a pci_scan_root_bus_msi() interface so an arch can specify the MSI controller up front. This removes the need for a pcibios callback to set the MSI controller later. This is not exported because I'd like to replace the variety of "scan root bus" interfaces with a single, more extensible interface that can handle the MSI controller, domain, pci_ops, resources, etc. I hope this interface is temporary. [bhelgaas: changelog, split into separate patch] Suggested-by: Russell King <linux@arm.linux.org.uk> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
| | * | ARM/PCI: Replace panic with WARN messages on failuresLorenzo Pieralisi2015-08-201-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the ARM PCI bios32 layer, failures to dynamically allocate pci_sys_data for a PCI bus, or a PCI bus scan failure have to be considered serious warnings but they should not trigger a system panic so that at least the system is given a chance to be debugged. This patch replaces the panic statements with WARN() messages to improve error reporting in the ARM PCI bios32 layer. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com> Acked-by: Marc Zyngier <marc.zyngier@arm.com> CC: Russell King <linux@arm.linux.org.uk> CC: Marc Zyngier <marc.zyngier@arm.com>
| | * | PCI: generic: Add arm64 supportJayachandran C2015-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make pci-host-generic driver (kernel option PCI_HOST_GENERIC) available on arm64. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: Build setup-irq.o for arm64Jayachandran C2015-08-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM64 requires setup-irq.o to provide pci_fixup_irqs() implementation. We are adding this now to support the pci-host-generic host controller, but we enable it for ARM64 PCI so that other host controllers can use this as well. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: generic: Remove dependency on ARM-specific struct hw_pciJayachandran C2015-08-201-19/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic OF-based host controller driver uses pci_common_init_dev(), which is ARM-specific and requires the ARM struct hw_pci. The part of pci_common_init_dev() that is needed is limited and can be done here without using hw_pci. Note that the ARM pcibios functions expect the PCI sysdata to be a pointer to a struct pci_sys_data. Add a struct pci_sys_data as the first element in struct gen_pci so that when we use a gen_pci pointer as sysdata, it is also a pointer to a struct pci_sys_data. Create and scan the root bus directly without using the ARM pci_common_init_dev() interface. [bhelgaas: changelog, move pcie_bus_configure_settings() before pci_bus_add_devices(), combine !PCI_PROBE_ONLY blocks] Tested-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Tested-by: Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com> Tested-by: Pavel Fedin <p.fedin@samsung.com> Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
| | * | ARM/PCI: Set MPS before pci_bus_add_devices()Murali Karicheri2015-07-231-13/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPS configuration should be done *before* pci_bus_add_devices(). After pci_bus_add_devices(), drivers may be bound to devices, and the PCI core shouldn't touch device configuration while a driver owns the device. [bhelgaas: remove check for bus being non-NULL] Reported-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| *---. \ \ Merge branches 'pci/host-dra7xx', 'pci/host-imx6' and 'pci/host-spear' into nextBjorn Helgaas2015-08-243-13/+4
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-dra7xx: PCI: dra7xx: Remove unneeded use of IS_ERR_VALUE() * pci/host-imx6: PCI: imx6: Simplify a trivial if-return sequence * pci/host-spear: PCI: spear: Use BUG_ON() instead of condition followed by BUG()
| | | | * | | PCI: spear: Use BUG_ON() instead of condition followed by BUG()Fabio Estevam2015-08-201-2/+1
| | | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use BUG_ON() instead of an if condition followed by BUG(). The semantic patch that makes this change is available in scripts/coccinelle/misc/bugon.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Pratyush Anand <pratyush.anand@gmail.com>
| | | * | | PCI: imx6: Simplify a trivial if-return sequenceFabio Estevam2015-08-201-10/+2
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Simplify a trivial if-return sequence by combining it with a preceding function call. The semantic patch that makes this change is available in scripts/coccinelle/misc/simple_return.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Lucas Stach <l.stach@pengutronix.de>
| | * | | PCI: dra7xx: Remove unneeded use of IS_ERR_VALUE()Fabio Estevam2015-08-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to use the IS_ERR_VALUE() macro for checking the return value from pm_runtime_* functions. Test for a negative pm_runtime_get_sync() return value instead of using IS_ERR_VALUE(). The semantic patch that makes this change is available in scripts/coccinelle/api/pm_runtime.cocci. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Kishon Vijay Abraham I <kishon@ti.com>
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| *-. \ \ \ Merge branches 'pci/host-dra7xx' and 'pci/host-iproc' into nextBjorn Helgaas2015-08-147-33/+161
| |\ \ \ \ \ | | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/host-dra7xx: ARM: dts: am57xx-evm: Add 'gpios' property with gpio2_8 PCI: dra7xx: Add support to make GPIO drive PERST# line PCI: dra7xx: Clear MSE bit during suspend so clocks will idle PCI: dra7xx: Add PM support PCI: dra7xx: Disable pm_runtime on get_sync failure * pci/host-iproc: PCI: iproc: Allow BCMA bus driver to be built as module PCI: iproc: Add arm64 support PCI: iproc: Delete unnecessary checks before phy calls
| | | * | | PCI: iproc: Allow BCMA bus driver to be built as moduleHauke Mehrtens2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change CONFIG_PCIE_IPROC_BCMA to tristate to make it possible to build this driver as a module. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Ray Jui <rjui@broadcom.com>
| | | * | | PCI: iproc: Add arm64 supportRay Jui2015-07-222-7/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add arm64 support to the iProc PCIe driver. Note that on arm32, bus->sysdata points to the arm32-specific pci_sys_data struct, and pci_sys_data.private_data contains the iproc_pcie pointer. For arm64, there's nothing corresponding to pci_sys_data, so we keep the iproc_pcie pointer directly in bus->sysdata. In addition, arm64 does IRQ mapping in pcibios_add_device(), so it doesn't need pci_fixup_irqs() as arm32 does. Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <sbranden@broadcom.com>
| | | * | | PCI: iproc: Delete unnecessary checks before phy callsMarkus Elfring2015-07-141-21/+13
| | | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The functions phy_exit() and phy_power_off() test whether their argument is NULL and then return immediately. Thus the test around the calls is not needed. This issue was detected by using the Coccinelle software. [bhelgaas: also phy_init() and phy_power_on(), as Ray Jui suggested] [bhelgaas: also remove tests in iproc_pcie_remove()] Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ray Jui <rjui@broadcom.com>
| | * | | ARM: dts: am57xx-evm: Add 'gpios' property with gpio2_8Kishon Vijay Abraham I2015-08-112-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpio2_8 is connected to the PCIe_RESETn line and it has to be driven low to reset the PCIe cards. Add gpios property to PCIe DT node. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Tony Lindgren <tony@atomide.com>
| | * | | PCI: dra7xx: Add support to make GPIO drive PERST# lineKishon Vijay Abraham I2015-08-112-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PERST# line in am57x-evm is connected to a GPIO line and PERST# should be driven high to indicate the clocks are stable (As per Figure 2-10: Power Up of the PCIe CEM spec 3.0). Add support to make GPIO drive PERST# line. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: dra7xx: Clear MSE bit during suspend so clocks will idleKishon Vijay Abraham I2015-08-111-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7xx requires the MSE bit to be cleared to set the master in standby mode. (In DRA7xx TRM_vE, section 24.9.4.5.2.2.1 PCIe Controller Master Standby Behavior advises to use the clearing of the local MSE bit to set the master in standby. Without this some of the clocks do not idle). Clear the MSE bit on suspend and enable it on resume. Clearing MSE bit is required to get clocks to be idled after suspend. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
| | * | | PCI: dra7xx: Add PM supportKishon Vijay Abraham I2015-08-111-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PM support to pci-dra7xx so PCI clocks can be disabled during suspend and enabled during resume without affecting PCI functionality. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
| | * | | PCI: dra7xx: Disable pm_runtime on get_sync failureKishon Vijay Abraham I2015-08-111-1/+3
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the error handling when pm_runtime_get_sync() fails. If pm_runtime_get_sync() fails, call pm_runtime_disable() so there are no unbalanced pm_runtime_enable() calls. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
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| *-----. \ \ Merge branches 'pci/hotplug', 'pci/iommu', 'pci/irq' and ↵Bjorn Helgaas2015-08-1419-271/+209
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pci/virtualization' into next * pci/hotplug: PCI: pciehp: Remove ignored MRL sensor interrupt events PCI: pciehp: Remove unused interrupt events PCI: pciehp: Handle invalid data when reading from non-existent devices PCI: Hold pci_slot_mutex while searching bus->slots list PCI: Protect pci_bus->slots with pci_slot_mutex, not pci_bus_sem PCI: pciehp: Simplify pcie_poll_cmd() PCI: Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slot * pci/iommu: PCI: Remove pci_ats_enabled() PCI: Stop caching ATS Invalidate Queue Depth PCI: Move ATS declarations to linux/pci.h so they're all together PCI: Clean up ATS error handling PCI: Use pci_physfn() rather than looking up physfn by hand PCI: Inline the ATS setup code into pci_ats_init() PCI: Rationalize pci_ats_queue_depth() error checking PCI: Reduce size of ATS structure elements PCI: Embed ATS info directly into struct pci_dev PCI: Allocate ATS struct during enumeration iommu/vt-d: Cache PCI ATS state and Invalidate Queue Depth * pci/irq: PCI: Kill off set_irq_flags() usage * pci/virtualization: PCI: Add ACS quirks for Intel I219-LM/V
| | | | | * | | PCI: Add ACS quirks for Intel I219-LM/VAlex Williamson2015-08-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Intel 100-series chipset now includes the integrated Ethernet as part of a multifunction package. The Ethernet function does not include native ACS support, but Intel confirms that the device is not capable of peer-to- peer within the package. We can therefore quirk it to expose the isolation. Signed-off-by: Alex Williamson <alex.williamson@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: John Ronciak <john.ronciak@gmail.com>
| | | | * | | | PCI: Kill off set_irq_flags() usageRob Herring2015-08-117-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_irq_flags is ARM-specific with custom flags which have genirq equivalents. Convert drivers to use the genirq interfaces directly, so we can kill off set_irq_flags. The translation of flags is as follows: IRQF_VALID -> !IRQ_NOREQUEST IRQF_PROBE -> !IRQ_NOPROBE IRQF_NOAUTOEN -> IRQ_NOAUTOEN For IRQs managed by an irqdomain, the irqdomain core code handles clearing and setting IRQ_NOREQUEST already, so there is no need to do this in .map() functions, and we can simply remove the set_irq_flags calls. Some users also modify IRQ_NOPROBE, and this has been maintained although it is not clear that is really needed. There appears to be a great deal of blind copy and paste of this code. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jingoo Han <jingoohan1@gmail.com> CC: Kishon Vijay Abraham I <kishon@ti.com> CC: Murali Karicheri <m-karicheri2@ti.com> CC: Thierry Reding <thierry.reding@gmail.com> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Alexandre Courbot <gnurou@gmail.com> CC: Jingoo Han <jingoohan1@gmail.com> CC: Pratyush Anand <pratyush.anand@gmail.com> CC: Simon Horman <horms@verge.net.au> CC: Michal Simek <michal.simek@xilinx.com> CC: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
| | | * | | | | PCI: Remove pci_ats_enabled()Bjorn Helgaas2015-08-132-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove pci_ats_enabled(). There are no callers outside the ATS code itself. We don't need to check ats_cap, because if we don't find an ATS capability, we'll never set ats_enabled. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Stop caching ATS Invalidate Queue DepthBjorn Helgaas2015-08-132-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stop caching the Invalidate Queue Depth in struct pci_dev. pci_ats_queue_depth() is typically called only once per device, and it returns a fixed value per-device, so callers who need the value frequently can cache it themselves. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Move ATS declarations to linux/pci.h so they're all togetherBjorn Helgaas2015-08-132-42/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move ATS declarations to linux/pci.h so they're all in one place. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Clean up ATS error handlingBjorn Helgaas2015-08-131-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's no need to BUG() if we enable ATS when it's already enabled. We don't need to BUG() when disabling ATS on a device that doesn't support ATS or if it's already disabled. If ATS is enabled, certainly we found an ATS capability in the past, so it should still be there now. Clean up these error paths. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Use pci_physfn() rather than looking up physfn by handBjorn Helgaas2015-08-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the pci_physfn() helper rather than looking up physfn by hand. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Inline the ATS setup code into pci_ats_init()Bjorn Helgaas2015-08-131-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ATS setup code in ats_alloc_one() is only used by pci_ats_init(), so inline it there. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Rationalize pci_ats_queue_depth() error checkingBjorn Helgaas2015-08-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We previously returned -ENODEV for devices that don't support ATS (except that we always returned 0 for VFs, whether or not they support ATS). For consistency, always return -EINVAL (not -ENODEV) if the device doesn't support ATS. Return zero for VFs that support ATS. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Reduce size of ATS structure elementsBjorn Helgaas2015-08-131-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The extended capabilities list is linked with 12-bit pointers, and the ATS Smallest Translation Unit and Invalidate Queue Depth fields are both 5 bits. Use u16 and u8 to hold the extended capability address and the stu and qdep values. No functional change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Embed ATS info directly into struct pci_devBjorn Helgaas2015-08-134-53/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The pci_ats struct is small and will get smaller, so I don't think it's worth allocating it separately from the pci_dev struct. Embed the ATS fields directly into struct pci_dev. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | PCI: Allocate ATS struct during enumerationBjorn Helgaas2015-08-135-57/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, we allocated pci_ats structures when an IOMMU driver called pci_enable_ats(). An SR-IOV VF shares the STU setting with its PF, so when enabling ATS on the VF, we allocated a pci_ats struct for the PF if it didn't already have one. We held the sriov->lock to serialize threads concurrently enabling ATS on several VFS so only one would allocate the PF pci_ats. Gregor reported a deadlock here: pci_enable_sriov sriov_enable virtfn_add mutex_lock(dev->sriov->lock) # acquire sriov->lock pci_device_add device_add BUS_NOTIFY_ADD_DEVICE notifier chain iommu_bus_notifier amd_iommu_add_device # iommu_ops.add_device init_iommu_group iommu_group_get_for_dev iommu_group_add_device __iommu_attach_device amd_iommu_attach_device # iommu_ops.attach_device attach_device pci_enable_ats mutex_lock(dev->sriov->lock) # deadlock There's no reason to delay allocating the pci_ats struct, and if we allocate it for each device at enumeration-time, there's no need for locking in pci_enable_ats(). Allocate pci_ats struct during enumeration, when we initialize other capabilities. Note that this implementation requires ATS to be enabled on the PF first, before on any of the VFs because the PF controls the STU for all the VFs. Link: http://permalink.gmane.org/gmane.linux.kernel.iommu/9433 Reported-by: Gregor Dick <gdick@solarflare.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de>
| | | * | | | | iommu/vt-d: Cache PCI ATS state and Invalidate Queue DepthBjorn Helgaas2015-07-201-10/+18
| | | | |_|/ / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We check the ATS state (enabled/disabled) and fetch the PCI ATS Invalidate Queue Depth in performance-sensitive paths. It's easy to cache these, which removes dependencies on PCI. Remember the ATS enabled state. When enabling, read the queue depth once and cache it in the device_domain_info struct. This is similar to what amd_iommu.c does. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Joerg Roedel <jroedel@suse.de> Acked-by: Joerg Roedel <jroedel@suse.de>
| | * | | | | PCI: pciehp: Remove ignored MRL sensor interrupt eventsBjorn Helgaas2015-08-102-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We queued interrupt events for the MRL being opened or closed, but the code in interrupt_event_handler() that handles these events ignored them. Stop enabling MRL interrupts and remove the ignored events. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: pciehp: Remove unused interrupt eventsBjorn Helgaas2015-08-101-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The list of interrupt events (INT_BUTTON_IGNORE, INT_PRESENCE_ON, etc.) was copied from other hotplug drivers, but pciehp doesn't use them all. Remove the interrupt events that aren't used by pciehp. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: pciehp: Handle invalid data when reading from non-existent devicesJarod Wilson2015-08-101-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's platform-dependent, but an MMIO read to a non-existent PCI device generally returns data with all bits set. This happens when the host bridge or Root Complex times out waiting for a response from the device and fabricates return data to complete the CPU's read. One example, reported in the bugzilla below, involved this hierarchy: pci 0000:00:1c.0: PCI bridge to [bus 02-3a] Root Port pci 0000:02:00.0: PCI bridge to [bus 03-0a] Upstream Port pci 0000:03:03.0: PCI bridge to [bus 05-07] Downstream Port pci 0000:05:00.0: PCI bridge to [bus 06-07] Thunderbolt Upstream Port pci 0000:06:00.0: PCI bridge to [bus 07] Thunderbolt Downstream Port pci 0000:07:00.0: BCM57762 NIC Unplugging the Thunderbolt switch and the NIC below it resulted in this: pciehp 0000:03:03.0: Surprise Removal tg3 0000:07:00.0: tg3_abort_hw timed out, TX_MODE_ENABLE will not clear MAC_TX_MODE=ffffffff pciehp 0000:06:00.0: unloading service driver pciehp pciehp 0000:06:00.0: pcie_isr: intr_loc 11f pciehp 0000:06:00.0: Switch interrupt received pciehp 0000:06:00.0: Latch open on Slot pciehp 0000:06:00.0: Attention button interrupt received pciehp 0000:06:00.0: Button pressed on Slot pciehp 0000:06:00.0: Presence/Notify input change pciehp 0000:06:00.0: Card present on Slot pciehp 0000:06:00.0: Power fault interrupt received pciehp 0000:06:00.0: Data Link Layer State change pciehp 0000:06:00.0: Link Up event The pciehp driver correctly noticed that the Thunderbolt switch (05:00.0 and 06:00.0) and NIC (07:00.0) had been removed, and it called their driver remove methods. Since the NIC was already gone, tg3 received 0xffffffff when it tried to read from the device. The resulting timeout is a tg3 issue and not of interest here. Similarly, since the 06:00.0 Thunderbolt switch was already gone, pcie_isr() received 0xffff when it tried to read PCI_EXP_SLTSTA, and pciehp thought that was valid status showing that many events had happened: the latch had been opened, the attention button had been pressed, a card was now present, and the link was now up. These are all wrong, of course, but pciehp went on to try to power up and enumerate devices below the non-existent bridge: pciehp 0000:06:00.0: PCI slot - powering on due to button press pciehp 0000:06:00.0: Surprise Insertion pci 0000:07:00.0 id reading try 50 times with interval 20 ms to get ffffffff [bhelgaas: changelog, also check in pcie_poll_cmd() & pcie_do_write_cmd()] Link: https://bugzilla.kernel.org/show_bug.cgi?id=99841 Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Jarod Wilson <jarod@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: Hold pci_slot_mutex while searching bus->slots listYijing Wang2015-07-305-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, pci_setup_device() and similar functions searched the pci_bus->slots list without any locking. It was possible for another thread to update the list while we searched it. Add pci_dev_assign_slot() to search the list while holding pci_slot_mutex. [bhelgaas: changelog, fold in CONFIG_SYSFS fix] Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: Protect pci_bus->slots with pci_slot_mutex, not pci_bus_semYijing Wang2015-07-302-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rajat Jain reported a deadlock when PCIe hot-add and AER recovery happen at the same time: thread 1: pciehp_enable_slot pciehp_configure_device pci_bus_add_devices pci_bus_add_device device_attach device_lock(dev) # acquire device lock ... pciehp_probe init_slot pci_hp_register pci_create_slot down_write(pci_bus_sem) # deadlock here thread 2: aer_isr_one_error aer_process_err_device do_recovery broadcast_error_message(..., report_error_detected) pci_walk_bus(..., cb=report_error_detected, ...) down_read(&pci_bus_sem) # acquire pci_bus_sem report_error_detected(dev) # cb() device_lock(dev) # deadlock here Previously, the bus->devices and bus->slots list were protected by pci_bus_sem. In pci_create_slot(), we held it for writing so we could add to the bus->slots list. Add a new local pci_slot_mutex to protect bus->slots. Hold pci_bus_sem for reading while searching the bus->devices list. [bhelgaas: changelog] Link: http://lkml.kernel.org/r/CAA93t1qpPqbih+UB0McA_d_+2rVaNkXsinAUxYzK9+JXSS+L-g@mail.gmail.com Reported-by: Rajat Jain <rajatja@google.com> Tested-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: pciehp: Simplify pcie_poll_cmd()Yijing Wang2015-07-151-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move first slot status read into while to simplify code. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | | | PCI: Use "slot" and "pci_slot" for struct hotplug_slot and struct pci_slotYijing Wang2015-07-151-61/+61
| | |/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now in pci_hotplug_core.c, we randomly name a struct hotplug_slot and a struct pci_slot. It's easy to confuse them, so let us use "slot" for a struct hotplug_slot and "pci_slot" for a struct pci_slot. No functional change. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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| *-----. \ \ \ \ Merge branches 'pci/irq', 'pci/misc', 'pci/resource' and ↵Bjorn Helgaas2015-08-0431-215/+239
| |\ \ \ \ \ \ \ \ | | | |_|_|_|/ / / | | |/| | | | / / | | | | | | |/ / | | | | | |/| / | | | | |_|_|/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pci/virtualization' into next * pci/irq: PCI/MSI: Free legacy IRQ when enabling MSI/MSI-X PCI: Add helpers to manage pci_dev->irq and pci_dev->irq_managed PCI, x86: Implement pcibios_alloc_irq() and pcibios_free_irq() PCI: Add pcibios_alloc_irq() and pcibios_free_irq() * pci/misc: PCI: Remove unused "pci_probe" flags PCI: Add VPD function 0 quirk for Intel Ethernet devices PCI: Add dev_flags bit to access VPD through function 0 PCI / ACPI: Fix pci_acpi_optimize_delay() comment PCI: Remove a broken link in quirks.c PCI: Remove useless redundant code PCI: Simplify pci_find_(ext_)capability() return value checks PCI: Move PCI_FIND_CAP_TTL to pci.h and use it in quirks PCI: Add pcie_downstream_port() (true for Root and Switch Downstream Ports) PCI: Fix pcie_port_device_resume() comment PCI: Shift PCI_CLASS_NOT_DEFINED consistently with other classes PCI: Revert aeb30016fec3 ("PCI: add Intel USB specific reset method") PCI: Fix TI816X class code quirk PCI: Fix generic NCR 53c810 class code quirk PCI: Use PCI_CLASS_SERIAL_USB instead of bare number PCI: Add quirk for Intersil/Techwell TW686[4589] AV capture cards PCI: Remove Intel Cherrytrail D3 delays * pci/resource: PCI: Call pci_read_bridge_bases() from core instead of arch code * pci/virtualization: PCI: Restore ACS configuration as part of pci_restore_state()
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