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* Merge branch 'irq-core-for-linus' of ↵Linus Torvalds2010-10-2183-2226/+2135
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'irq-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (96 commits) apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsets apic, x86: Check if EILVT APIC registers are available (AMD only) x86: ioapic: Call free_irte only if interrupt remapping enabled arm: Use ARCH_IRQ_INIT_FLAGS genirq, ARM: Fix boot on ARM platforms genirq: Fix CONFIG_GENIRQ_NO_DEPRECATED=y build x86: Switch sparse_irq allocations to GFP_KERNEL genirq: Switch sparse_irq allocator to GFP_KERNEL genirq: Make sparse_lock a mutex x86: lguest: Use new irq allocator genirq: Remove the now unused sparse irq leftovers genirq: Sanitize dynamic irq handling genirq: Remove arch_init_chip_data() x86: xen: Sanitise sparse_irq handling x86: Use sane enumeration x86: uv: Clean up the direct access to irq_desc x86: Make io_apic.c local functions static genirq: Remove irq_2_iommu x86: Speed up the irq_remapped check in hot pathes intr_remap: Simplify the code further ... Fix up trivial conflicts in arch/x86/Kconfig
| * apic, x86: Use BIOS settings for IBS and MCE threshold interrupt LVT offsetsRobert Richter2010-10-204-41/+154
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We want the BIOS to setup the EILVT APIC registers. The offsets were hardcoded and BIOS settings were overwritten by the OS. Now, the subsystems for MCE threshold and IBS determine the LVT offset from the registers the BIOS has setup. If the BIOS setup is buggy on a family 10h system, a workaround enables IBS. If the OS determines an invalid register setup, a "[Firmware Bug]: " error message is reported. We need this change also for upcomming cpu families. Signed-off-by: Robert Richter <robert.richter@amd.com> LKML-Reference: <1286360874-1471-3-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * apic, x86: Check if EILVT APIC registers are available (AMD only)Robert Richter2010-10-202-9/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements checks for the availability of LVT entries (APIC500-530) and reserves it if used. The check becomes necessary since we want to let the BIOS provide the LVT offsets. The offsets should be determined by the subsystems using it like those for MCE threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts are supported. Beginning with family 10h at least 4 offsets are available. Since offsets must be consistent for all cores, we keep track of the LVT offsets in software and reserve the offset for the same vector also to be used on other cores. An offset is freed by setting the entry to APIC_EILVT_MASKED. If the BIOS is right, there should be no conflicts. Otherwise a "[Firmware Bug]: ..." error message is generated. However, if software does not properly determines the offsets, it is not necessarily a BIOS bug. Signed-off-by: Robert Richter <robert.richter@amd.com> LKML-Reference: <1286360874-1471-2-git-send-email-robert.richter@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * Merge branch 'linus' into irq/coreIngo Molnar2010-10-20331-1493/+2628
| |\ | | | | | | | | | | | | | | | Merge reason: update to almost-final-.36 Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Call free_irte only if interrupt remapping enabledYinghai Lu2010-10-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On a system that support intr-rempping when booting with "intremap=off" [ 177.895501] BUG: unable to handle kernel NULL pointer dereference at 00000000000000f8 [ 177.913316] IP: [<ffffffff8145fc18>] free_irte+0x47/0xc0 ... [ 178.173326] Call Trace: [ 178.173574] [<ffffffff810515b4>] destroy_irq+0x3a/0x75 [ 178.192934] [<ffffffff81051834>] arch_teardown_msi_irq+0xe/0x10 [ 178.193418] [<ffffffff81458dc3>] arch_teardown_msi_irqs+0x56/0x7f [ 178.213021] [<ffffffff81458e79>] free_msi_irqs+0x8d/0xeb Call free_irte only when interrupt remapping is enabled. Signed-off-by: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <4CBCB274.7010108@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | arm: Use ARCH_IRQ_INIT_FLAGSThomas Gleixner2010-10-162-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The core code now initializes the requested number of interrupts and sets the flags in irq_desc.status which are requested by the architecture via ARCH_IRQ_INIT_FLAGS. Add ARCH_IRQ_INIT_FLAGS and remove the loop which sets those flags after the irq descriptors are allocated. [ This patch should have been in the original irq rework and got dropped accidentaly ] Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@stericsson.com> Cc: Anand Gadiyar <gadiyar@ti.com>
| * | genirq, ARM: Fix boot on ARM platformsAnand Gadiyar2010-10-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit b683de2b3 in linux-next as of 20101014 (genirq: Query arch for number of early descriptors) seems to have broken bootup on several ARM boards - my beagleboard gives the following dump with earlyprintk: NR_IRQS:402 Unable to handle kernel NULL pointer dereference at virtual address 00000028 pgd = c0004000 [00000028] *pgd=00000000 Internal error: Oops: 5 [#1] last sysfs file: Modules linked in: CPU: 0 Not tainted (2.6.36-rc7-next-20101014-linux-next-20101012+ #40) PC is at init_IRQ+0x14/0x48 LR is at start_kernel+0x150/0x2c0 [...] We seem to be using desc->status without assigning desc to anything. Fix this by adding back the code that was originally there. Signed-off-by: Anand Gadiyar <gadiyar@ti.com> Tested-by: Linus Walleij <linus.walleij@stericsson.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: linux-arm-kernel@lists.infradead.org LKML-Reference: <1287077397-21781-1-git-send-email-gadiyar@ti.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Fix CONFIG_GENIRQ_NO_DEPRECATED=y buildThomas Gleixner2010-10-122-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This option can be set to verify the full conversion to the new chip functions. Fix the fallout of the patch rework, so the core code compiles and works with it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | x86: Switch sparse_irq allocations to GFP_KERNELThomas Gleixner2010-10-121-8/+8
| | | | | | | | | | | | | | | | | | | | | No callers from atomic context (except boot) anymore. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Switch sparse_irq allocator to GFP_KERNELThomas Gleixner2010-10-121-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | The allocator functions are now called outside of preempt disabled regions. Switch to GFP_KERNEL. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Make sparse_lock a mutexThomas Gleixner2010-10-121-19/+14
| | | | | | | | | | | | | | | | | | | | | No callers from atomic regions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: lguest: Use new irq allocatorThomas Gleixner2010-10-121-2/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Rusty Russell <rusty@rustcorp.com.au>
| * | genirq: Remove the now unused sparse irq leftoversThomas Gleixner2010-10-126-266/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The move_irq_desc() function was only used due to the problem that the allocator did not free the old descriptors. So the descriptors had to be moved in create_irq_nr(). That's history. The code would have never been able to move active interrupt descriptors on affinity settings. That can be done in a completely different way w/o all this horror. Remove all of it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Sanitize dynamic irq handlingThomas Gleixner2010-10-124-125/+31
| | | | | | | | | | | | | | | | | | | | | | | | Use the cleanup functions of the dynamic allocator. No need to have separate implementations. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Remove arch_init_chip_data()Thomas Gleixner2010-10-123-10/+0
| | | | | | | | | | | | | | | | | | | | | This function should have not been there in the first place. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: xen: Sanitise sparse_irq handlingThomas Gleixner2010-10-121-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | There seems to be more cleanups possible, but that's left to the xen experts :) Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Jeremy Fitzhardinge <jeremy@xensource.com>
| * | x86: Use sane enumerationThomas Gleixner2010-10-121-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | Instead of looping through all interrupts, use the bitmap lookup to find the next. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: uv: Clean up the direct access to irq_descThomas Gleixner2010-10-123-38/+20
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Make io_apic.c local functions staticThomas Gleixner2010-10-122-11/+5
| | | | | | | | | | | | | | | | | | | | | No users outside of io_apic.c Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | genirq: Remove irq_2_iommuThomas Gleixner2010-10-122-22/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irq_2_iommu is now in the x86 code where it belongs. Remove all leftovers. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: Speed up the irq_remapped check in hot pathesThomas Gleixner2010-10-124-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irq_2_iommu is in struct irq_cfg, so we can do the irq_remapped check based on irq_cfg instead of going through a lookup function. That's especially interesting in the eoi_ioapic_irq() hotpath. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | intr_remap: Simplify the code furtherThomas Gleixner2010-10-121-84/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having irq_2_iommu in struct irq_cfg allows further simplifications. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | intr_remap: Use irq_2_iommu in struct irq_cfgThomas Gleixner2010-10-121-36/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch the intr_remapping code to use the irq_2_iommu struct in irg_cfg. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: Embedd irq_2_iommu into irq_cfgThomas Gleixner2010-10-123-7/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That interrupt remapping code is x86 specific and tied to the io_apic code. No need for separate allocator functions in the interrupt remapping code. This allows to simplify the code and irq_2_iommu is small (13 bytes on 64bit) so it's not a real problem even if interrupt remapping is runtime disabled. If it's compile time disabled the impact is zero. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | pci: intr_remap: Remove unused functionsThomas Gleixner2010-10-122-49/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No users. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | pci: intr_remap: Use irq_dataThomas Gleixner2010-10-121-31/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No need to dereference irq_desc. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | pci: intr-remap: Free irte memory if SPARSE_IRQ=yThomas Gleixner2010-10-121-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With SPARSE_IRQ=y the irte descriptors are dynamically allocated, but not freed in free_irte(). That was ok as long as the sparse irq core was not freeing irq descriptors on destroy_irq(). Now we leak the irte descriptor. Free it in free_irte(). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: Suresh Siddha <suresh.b.siddha@intel.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: io_apic: Remove the now unused sparse_irq arch_* functionsThomas Gleixner2010-10-121-120/+0
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Cleanup sparse irq codeThomas Gleixner2010-10-122-60/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Switch over to the new allocator and remove all the magic which was caused by the unability to destroy irq descriptors. Get rid of the create_irq_nr() loop for sparse and non sparse irq. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Don't setup ioapic irq for sci twiceYinghai Lu2010-10-121-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sparseirq rework triggered a warning in the iommu code, which was caused by setting up ioapic for ACPI irq 9 twice. This function is solely to handle interrupts which are on a secondary ioapic and outside the legacy irq range. Replace the sparse irq_to_desc check with a non ifdeffed version. [ tglx: Moved it before the ioapic sparse conversion and simplified the inverse logic ] Signed-off-by: Yinghai Lu <yinghai@kernel.org> LKML-Reference: <4CB00122.3030301@kernel.org> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: io_apic: Prepare alloc/free_irq_cfg()Thomas Gleixner2010-10-121-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Rename the grossly misnamed get_one_free_irq_cfg() to alloc_irq_cfg(). Add a (not yet used) irq number argument to free_irq_cfg() Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Implement new allocator functionsThomas Gleixner2010-10-121-7/+47
| | | | | | | | | | | | | | | | | | | | | Implement new allocator functions which make use of the core changes. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Cleanup get_one_free_irq_cfg()Thomas Gleixner2010-10-121-12/+11
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Cleanup some moreThomas Gleixner2010-10-121-12/+8
| | | | | | | | | | | | | | | | | | | | | Cleanup after the irq_chip conversion a bit. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Convert ht set_affinity to new chip functionThomas Gleixner2010-10-121-14/+11
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: Cleanup hpet affinity settingThomas Gleixner2010-10-121-2/+1
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Convert dmar affinity setting to new chip functionThomas Gleixner2010-10-121-13/+12
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: David Woodhouse <dwmw2@infradead.org>
| * | x86: Convert remapped msi to new chip.irq_set_affinity functionThomas Gleixner2010-10-121-17/+17
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Suresh Siddha <suresh.b.siddha@intel.com> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: Convert remapped ioapic affinity setting to new irq chip functionThomas Gleixner2010-10-121-38/+20
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Suresh Siddha <suresh.b.siddha@intel.com>
| * | x86: Convert msi affinity setting to new chip functionsThomas Gleixner2010-10-121-14/+12
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | x86: Prepare the affinity common functions for taking struct irq_data *Thomas Gleixner2010-10-123-52/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | While at it rename it to sensible function names and fix the return value from unsigned to int for __ioapic_set_affinity (set_desc_affinity). Returning -1 in a function returning unsigned int is somewhat strange. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Clean up the direct access to irq_descThomas Gleixner2010-10-121-51/+28
| | | | | | | | | | | | | | | | | | | | | Most of it is useless pseudo optimization. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | ht: Convert to new irq_chip functionsThomas Gleixner2010-10-123-18/+13
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
| * | dmar: Convert to new irq chip functionsThomas Gleixner2010-10-124-10/+11
| | | | | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu> Acked-by: David Woodhouse <dwmw2@infradead.org>
| * | x86: ioapic/hpet: Convert to new chip functionsThomas Gleixner2010-10-123-30/+26
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: ioapic: Convert mask to new irq_chip functionThomas Gleixner2010-10-121-52/+43
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: io_apic: Convert startup to new irq_chip functionThomas Gleixner2010-10-121-7/+5
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Cleanup io_apicThomas Gleixner2010-10-121-67/+42
| | | | | | | | | | | | | | | | | | | | | | | | Sanitize functions. Remove irq_desc pointer magic. Preparatory patch for further cleanups. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: Cleanup access to irq_dataThomas Gleixner2010-10-122-32/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixup the open coded access to irq_desc->[handler_data|chip_data|msi-desc] Use the macros and inline functions for it. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
| * | x86: i8259: Convert to new irq_chip functionsThomas Gleixner2010-10-125-44/+47
| | | | | | | | | | | | | | | Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Ingo Molnar <mingo@elte.hu>
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