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* Merge branch 'misc2' into develRussell King2010-02-2572-562/+1092
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| * ARM: Eliminate decompressor -Dstatic= PIC hackRussell King2010-02-254-104/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We used to build decompressors with -Dstatic= to avoid any local data being generated. The problem is that local data generates GOTOFF relocations, which means we can't relocate the data relative to the text segment. Global data, on the other hand, goes through the GOT, and can be relocated anywhere. Unfortunately, with the new decompressors, this presents a problem since they declare static data within functions, and this leads to stack overflow. Fix this by separating out the decompressor code into a separate file, and removing 'static' from BSS data in misc.c. Also, discard the .data section - this means that should we end up with read/write initialized data, the decompressor will fail to link and the problem will be obvious. Acked-by: Nicolas Pitre <nico@fluxnic.net> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5952/1: ARM: MM: Add ARM_L1_CACHE_SHIFT_6 for handle inside each ARCH ↵Kukjin Kim2010-02-243-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kconfig Add ARM_L1_CACHE_SHIFT_6 to arch/arm/Kconfig to allow CPUs with L1 cache lines which are 64bytes to indicate this without having to alter the arch/arm/mm/Kconfig entry each time. Update the mm Kconfig so that ARM_L1_CACHE_SHIFT default value uses this and change OMAP3 and S5PC1XX to select ARM_L1_CACHE_SHIFT_6. Acked-by: Ben Dooks <ben-linux@fluff.org> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5933/1: amba-pl011: support hardware flow controlRabin Vincent2010-02-181-0/+19
| | | | | | | | | | | | | | | | | | | | | | Enable/disable automatic hardware flow control as requested by the termios. The controller does not allow us to control the RTS line when auto-RTS is enabled, so we enable auto-RTS only if the kernel has not disabled RTS. Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5930/1: Add PKMAP area description to memory.txt.Fenkart/Bostandzhyan2010-02-151-1/+5
| | | | | | | | | | | | | | | | Also adapts delimiters of neighbouring modules area. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5929/1: Add checks to detect overlap of memory regions.Fenkart/Bostandzhyan2010-02-151-0/+17
| | | | | | | | | | | | | | Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5928/1: Change type of VMALLOC_END to unsigned long.Fenkart/Bostandzhyan2010-02-1530-32/+32
| | | | | | | | | | | | | | | | Makes it consistent with VMALLOC_START Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5927/1: Make delimiters of DMA area globally visibly.Fenkart/Bostandzhyan2010-02-153-11/+17
| | | | | | | | | | | | | | | | Adds DMA area to 'virtual memory map' startup message Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5926/1: Add "Virtual kernel memory..." printout.Fenkart/Bostandzhyan2010-02-151-9/+69
| | | | | | | | | | | | | | | | Code based on parisc and x86_32. Tested-by: H Hartley Sweeten <hsweeten@visionengravers.com> Signed-off-by: Andreas Fenkart <andreas.fenkart@streamunlimited.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5920/1: OMAP4: Enable L2 CacheSantosh Shilimkar2010-02-151-0/+3
| | | | | | | | | | | | | | | | | | This patch enables L2 cache and associated Errata on the OMAP4430 SDP. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5919/1: ARM: L2 : Errata 588369: Clean & Invalidate do not invalidate ↵Santosh Shilimkar2010-02-152-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clean lines This patch implements the work-around for the errata 588369.The secure API is used to alter L2 debug register because of trust-zone. This version updated with comments from Russell and Catalin and generated against 2.6.33-rc6 mainline kernel. Detail comments can be found: http://www.spinics.net/lists/linux-omap/msg23431.html Signed-off-by: Woodruff Richard <r-woodruff2@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5917/1: OMAP4: Add L2 Cache supportSantosh Shilimkar2010-02-153-1/+56
| | | | | | | | | | | | | | | | | | | | This patch adds L2 Cache support for OMAP4. External L2 cache is used in OMAP4 CC: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5916/1: ARM: L2 : Add maintainace by line helper functionsSantosh Shilimkar2010-02-151-10/+26
| | | | | | | | | | | | | | | | | | This patch adds the cache maintainance by line helper functions. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: vfp ptrace: no point flushing hw context for PTRACE_GETVFPREGSRussell King2010-02-153-5/+29
| | | | | | | | | | | | | | | | | | If we're only reading the VFP context via the ptrace call, there's no need to invalidate the hardware context - we only need to do that on PTRACE_SETVFPREGS. This allows more efficient monitoring of a traced task. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: vfp: fix vfp_sync_state()Russell King2010-02-151-20/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The more I look at vfp_sync_state(), the more I believe it's trying to do its job in a really obscure way. Essentially, last_VFP_context[] tracks who owns the state in the VFP hardware. If last_VFP_context[] is the context for the thread which we're interested in, then the VFP hardware has context which is not saved in the software state - so we need to bring the software state up to date. If last_VFP_context[] is for some other thread, we really don't care what state the VFP hardware is in; it doesn't contain any information pertinent to the thread we're trying to deal with - so don't touch the hardware. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: ptrace: get rid of PTRACE_{PEEK,POKE}{TEXT,DATA}Russell King2010-02-151-16/+0
| | | | | | | | | | | | | | The generic ptrace_request() handles these for us, so there's no need to duplicate them in arch code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5912/1: Define a 32-bit Thumb-2 breakpoint instructionDaniel Jacobowitz2010-02-151-0/+31
| | | | | | | | | | | | | | | | Recognize 0xf7f0 0xa000 as a 32-bit breakpoint instruction for Thumb-2. Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5911/1: ARM: Select CPU_32v6K for CPU_V7 only if ARCH_OMAP2 is not selectedTony Lindgren2010-02-151-2/+2
| | | | | | | | | | | | | | | | Otherwise the kernel built with both CPU_V6 and CPU_V7 will not boot on omap2. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5905/1: ARM: Global ASID allocation on SMPCatalin Marinas2010-02-153-14/+126
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current ASID allocation algorithm doesn't ensure the notification of the other CPUs when the ASID rolls over. This may lead to two processes using the same ASID (but different generation) or multiple threads of the same process using different ASIDs. This patch adds the broadcasting of the ASID rollover event to the other CPUs. To avoid a race on multiple CPUs modifying "cpu_last_asid" during the handling of the broadcast, the ASID numbering now starts at "smp_processor_id() + 1". At rollover, the cpu_last_asid will be set to NR_CPUS. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5906/1: arm: change command_line to cmd_lineJeremy Kerr2010-02-151-4/+4
| | | | | | | | | | | | | | | | | | drivers/of/fdt expects a cmd_line symbol, while arm uses command_line. Change to the former, so that we can eventually share with the fdt code. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5897/1: spinlock: don't use deprecated barriers on ARMv7Rabin Vincent2010-02-151-13/+23
| | | | | | | | | | | | | | | | | | | | On ARMv7, the use of the cp15 operations for barriers is deprecated in favour of the isb, dsb, and dmb instructions. Change the locking functions to use the appropriate type of dsb for the architecture being built for. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5889/1: Add atomic64 routines for ARMv6k and above.Will Deacon2010-02-152-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for perf-events support, ARM needs to support atomic64_t operations. v6k and above support the ldrexd and strexd instructions to do just that. This patch adds atomic64 support to the ARM architecture. v6k and above make use of new instructions whilst older cores fall back on the generic solution using spinlocks. If and when v7-M cores are supported by Linux, they will need to fall back on the spinlock implementation too. Signed-off-by: Will Deacon <will.deacon@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: add notify_die() supportRussell King2010-02-152-12/+26
| | | | | | | | | | | | | | | | | | | | | | Kernel debuggers want to be informed of die() events, so that they can take some action to allow the problem to be inspected. Provide the hook in a similar manner to x86. Note that we currently don't implement the individual trap hooks. Acked-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: 5880/1: arm: use generic infrastructure for early paramsJeremy Kerr2010-02-156-90/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ARM setup code includes its own parser for early params, there's also one in the generic init code. This patch removes __early_init (and related code) from arch/arm/kernel/setup.c, and changes users to the generic early_init macro instead. The generic macro takes a char * argument, rather than char **, so we need to update the parser functions a little. Signed-off-by: Jeremy Kerr <jeremy.kerr@canonical.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Move creation of /proc/cpu out of alignment.cRussell King2010-02-153-6/+19
| | | | | | | | | | | | | | Always creating this directory avoids other users having to jump through silly hoops when they want to share this directory. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: move LED support code out of arch/arm/kernel/time.cRussell King2010-02-153-104/+116
| | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: remove old RTC supportRussell King2010-02-152-82/+0
| | | | | | | | | | | | | | | | All RTC drivers have been converted to rtclib, so the old code providing the set_rtc function pointer, save_time_delta() and restore_time_delta() functions is obsolete. Remove it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * ARM: Add caller information to ioremapRussell King2010-02-158-32/+65
| | | | | | | | | | | | | | | | | | This allows the procfs vmallocinfo file to show who created the ioremap regions. Note: __builtin_return_address(0) doesn't do what's expected if its used in an inline function, so we leave __arm_ioremap callers in such places alone. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | Merge branch 'perf' into develRussell King2010-02-2514-64/+2594
|\ \ | | | | | | | | | | | | Conflicts: arch/arm/Kconfig
| * | ARM: 5903/1: arm/perfevents: add support for ARMv7Jean PIHET2010-02-122-5/+933
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds the Performance Events support for ARMv7 processor, using the PMNC unit in HW. Supports the following: - Cortex-A8 and Cortex-A9 processors, - dynamic detection of the number of available counters, based on the PMCR value, - runtime detection of the CPU arch (v6 or v7) and model (Cortex-A8 or Cortex-A9) Tested on OMAP3 (Cortex-A8) only. Signed-off-by: Jean Pihet <jpihet@mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5902/4: arm/perfevents: implement perf event support for ARMv6Jamie Iles2010-02-123-0/+1357
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements support for ARMv6 performance counters in the Linux performance events subsystem. ARMv6 architectures that have the performance counters should enable HW_PERF_EVENTS to get hardware performance events support in addition to the software events. Note: only ARM Ltd ARM cores are supported. This implementation also provides an ARM PMU abstraction layer to allow ARMv7 and others to be supported in the future by adding new a 'struct arm_pmu'. Cc: Jean Pihet <jpihet@mvista.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5900/2: arm: enable support for software perf eventsJamie Iles2010-02-123-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The perf events subsystem allows counting of both hardware and software events. This patch implements the bare minimum for software performance events. Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ingo Molnar <mingo@elte.hu> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5901/2: arm/oprofile: reserve the PMU when startingJamie Iles2010-02-127-64/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that we have access to the performance counters and that they aren't being used by perf events or anything else. Cc: Will Deacon <will.deacon@arm.com> Cc: Jean Pihet <jpihet@mvista.com> Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | ARM: 5899/2: arm: provide a mechanism to reserve performance countersJamie Iles2010-02-124-0/+184
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add support for perf events and to allow the hardware counters to be shared with oprofile, we need a way to reserve access to the pmu (performance monitor unit). Platforms with PMU interrupts should register the interrupts in arch/arm/kernel/pmu.c Signed-off-by: Jamie Iles <jamie.iles@picochip.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | Merge branch 'tmpreg' into develRussell King2010-02-2554-112/+146
|\ \ \ | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig arch/arm/mach-ux500/include/mach/debug-macro.S
| * | | ARM: 5910/1: ARM: Add tmp register for addruart and loadspTony Lindgren2010-02-1248-64/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Otherwise more complicated uart configuration won't be possible. We can use r1 for tmp register for both head.S and debug.S. NOTE: This patch depends on another patch to add the the tmp register into all debug-macro.S files. That can be done with: $ sed -i -e "s/addruart,rx|addruart, rx/addruart, rx, tmp/" arch/arm/*/include/*/debug-macro.S Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 5884/1: arm: Fix DCC console for v7Tony Lindgren2010-01-193-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch arch/arm/compressed/head.S defaults to generic DCC code that does not work for v7. For more information on the v7 DCC, see Cortex-A8 TRM "12.11.1 Debug communications channel". To use it with post 2.6.33-rc1 or later, you need to have: CONFIG_DEBUG_LL=y ONFIG_DEBUG_ICEDCC=y CONFIG_EARLY_PRINTK=y Earlier kernels need commit 93fd03a8c6728b58879f8af20ffd55d9c32a778b backported. Tested on omap3430. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 5883/1: Revert "disable NX support for OABI-supporting kernels"Rabin Vincent2010-01-181-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 14f0aa359365e8a93a77b71e3b840274b9b4dcb1. That commit was needed earlier because system call restarting for OABI (compat) required an executable stack and thus had problems with NX. Since ab72b00734ae4d0b ("ARM: Fix signal restart issues with NX and OABI compat") has reworked the code to not require an executable stack anymore, we can re-enable NX support for kernels with OABI (compat) support. Signed-off-by: Rabin Vincent <rabin@rab.in> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: 5882/1: ARM: Fix uncompress code compile for different defines of ↵Tony Lindgren2010-01-183-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | flush(void) Because of the include of the decompress_inflate.c file from boot/compress/misc.c, there are different flush() defines: In file included from arch/arm/boot/compressed/misc.c:249: arch/arm/boot/compressed/../../../../lib/decompress_inflate.c:138:29: error: macro "flush" passed 2 arguments, but takes just 0 Fix this by removing the define of flush() in misc.c for CONFIG_DEBUG_ICEDCC as it's already defined in mach/uncompress.h, and that is being included unconditionally. Also use a static inline function instead of define for mach-mxc and mach-gemini to avoid similar bug for those platforms. Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | ARM: fix badly placed mach/plat entries in Kconfig & MakefileRussell King2010-01-172-37/+37
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*-------------. \ \ Merge branches 'at91', 'cache', 'cup', 'ep93xx', 'ixp4xx', 'nuc', ↵Russell King2010-02-25963-8185/+28297
|\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'pending-dma-streaming', 'u300' and 'umc' into devel
| | | | | | | | * | | ARM: make_coherent(): fix problems with highpte, part 2Russell King2010-02-201-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | update_mmu_cache() is called with the page table for the faulted-in page still mapped. We need to modify the PTE for this page to ensure coherency with other shared mappings when multiple shared mappings exist within a MM. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | MM: Pass a PTE pointer to update_mmu_cache() rather than the PTE itselfRussell King2010-02-2040-62/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On VIVT ARM, when we have multiple shared mappings of the same file in the same MM, we need to ensure that we have coherency across all copies. We do this via make_coherent() by making the pages uncacheable. This used to work fine, until we allowed highmem with highpte - we now have a page table which is mapped as required, and is not available for modification via update_mmu_cache(). Ralf Beache suggested getting rid of the PTE value passed to update_mmu_cache(): On MIPS update_mmu_cache() calls __update_tlb() which walks pagetables to construct a pointer to the pte again. Passing a pte_t * is much more elegant. Maybe we might even replace the pte argument with the pte_t? Ben Herrenschmidt would also like the pte pointer for PowerPC: Passing the ptep in there is exactly what I want. I want that -instead- of the PTE value, because I have issue on some ppc cases, for I$/D$ coherency, where set_pte_at() may decide to mask out the _PAGE_EXEC. So, pass in the mapped page table pointer into update_mmu_cache(), and remove the PTE value, updating all implementations and call sites to suit. Includes a fix from Stephen Rothwell: sparc: fix fallout from update_mmu_cache API change Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | ARM: make_coherent: avoid recalculating the pfn for the modified pageRussell King2010-01-201-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We already know the pfn for the page to be modified in make_coherent, so let's stop recalculating it unnecessarily. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | ARM: make_coherent: fix problems with highpte, part 1Russell King2010-01-201-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | update_mmu_cache() is called with a page table already mapped. We call make_coherent(), which then calls adjust_pte() which wants to map other page tables. This causes kmap_atomic() to BUG() because the slot its trying to use is already taken. Since do_adjust_pte() modifies the page tables, we are also missing any form of locking, so we're risking corrupting the page tables. Fix this by using pte_offset_map_nested(), and taking the pte page table lock around do_adjust_pte(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | ARM: make_coherent: convert adjust_pte() to use p*d_none_or_clear_bad()Russell King2010-01-201-20/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | ARM: make_coherent: split adjust_pte() in twoRussell King2010-01-201-20/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | adjust_pte() walks the page tables, and do_adjust_pte() does the page table manipulation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| | | | | | | | * | | Merge git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdogLinus Torvalds2010-01-181-1/+44
| | | | | | | | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/wim/linux-2.6-watchdog: [WATCHDOG] iTCO_wdt: Add Intel Cougar Point and PCH DeviceIDs
| | | | | | | | | * | | [WATCHDOG] iTCO_wdt: Add Intel Cougar Point and PCH DeviceIDsSeth Heasley2010-01-181-1/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the Intel Cougar Point and PCH DeviceIDs for iTCO Watchdog. Signed-off-by: Seth Heasley <seth.heasley@intel.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
| | | | | | | | * | | | x86, apic: use logical flat for systems with <= 8 logical cpusSuresh Siddha2010-01-182-19/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can use logical flat mode if there are <= 8 logical cpu's (irrespective of physical apic id values). This will enable simplified and efficient IPI and device interrupt routing on such platforms. This has been tested to work on both Intel and AMD platforms. Exceptions like IBM summit platform which can't use logical flat mode are addressed by using OEM platform checks. Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Yinghai Lu <yinghai@kernel.org> Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Cc: Chris McDermott <lcm@linux.vnet.ibm.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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