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* drm/ttm: call ttm_bo_wait while inside a reservationMaarten Lankhorst2014-09-011-13/+12
| | | | | | | This is the last remaining function that doesn't use the reservation lock completely to fence off access to a buffer. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
* drm/nouveau: require reservations for nouveau_fence_sync and nouveau_bo_fenceMaarten Lankhorst2014-09-012-4/+15
| | | | | | | | This will ensure we always hold the required lock when calling those functions. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Acked-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: add reservation to nouveau_gem_ioctl_cpu_prepMaarten Lankhorst2014-09-011-4/+18
| | | | | | | | | | | | | Apart from some code inside ttm itself and nouveau_bo_vma_del, this is the only place where ttm_bo_wait is used without a reservation. Fix this so we can remove the fence_lock later on. After the switch to rcu the reservation lock will be removed again. Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Acked-by: Ben Skeggs <bskeggs@redhat.com>
* Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-08-283-79/+48
|\ | | | | | | | | | | | | | | | | | | | | into drm-next Just clearing out my -next queue before I go on vacation. Two UVD improvements that depend on the ttm change you just merged. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: preallocate mem for UVD create/destroy msg drm/radeon: allow UVD to use a second 256MB segment
| * drm/radeon: preallocate mem for UVD create/destroy msgChristian König2014-08-271-75/+26
| | | | | | | | | | | | | | | | | | llocating memory for UVD create and destroy messages can fail, which is rather annoying when this happens in the middle of a GPU reset. Try to avoid this condition by preallocating a page for those dummy messages. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: allow UVD to use a second 256MB segmentChristian König2014-08-273-5/+23
|/ | | | | | | This improves concurrent stream decoding. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-08-2815-184/+531
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next More radeon changes for drm-next. Highlights: - UVD support for older asics - Reset rework in preparation for Maarten's fence patches I have a few more patches which depend on Christian's ttm changes, I'll send them out separately once you've merged the ttm changes. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: drop doing resets in a work item drm/radeon: drop RADEON_FENCE_SIGNALED_SEQ v2 drm/radeon: add timeout argument to radeon_fence_wait_seq v2 drm/radeon: handle lockup in delayed work, v5 drm/radeon: take exclusive_lock in read mode during ring tests, v5 drm/radeon: force fence completion only on problematic rings (v2) drm/radeon: wake up all fences on manual reset drm/radeon: add UVD fw names for older asic drm/radeon: enable RB_ARB before resetting the VCPU drm/radeon: 760G/780V/880V don't have UVD drm/radeon: implement UVD hw workarounds for R6xx v3 drm/radeon: add UVD support for older asics v4 drm/radeon: add set_uvd_clocks callback for r6xx v4 drm/radeon: properly init UVD MC bits on R600 drm/radeon: force UVD buffers into VRAM on RS[78]80 v2 drm/radeon: move the IB test after the AGP fallback
| * drm/radeon: drop doing resets in a work itemChristian König2014-08-274-24/+8
| | | | | | | | | | | | | | | | | | | | Blocking completely innocent processes with a GPU reset is a pretty bad idea. Just set needs_reset and let the next command submission or fence wait do the job. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: drop RADEON_FENCE_SIGNALED_SEQ v2Christian König2014-08-272-19/+2
| | | | | | | | | | | | | | | | | | | | | | It's causing issues with VMID handling and comparing the fence value two times actually doesn't make handling faster. v2: rebased on reset changes Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add timeout argument to radeon_fence_wait_seq v2Maarten Lankhorst2014-08-271-20/+28
| | | | | | | | | | | | | | | | | | | | | | This makes it possible to wait for a specific amount of time, rather than wait until infinity. v2 (chk): rebased on other changes Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: handle lockup in delayed work, v5Christian König2014-08-272-78/+124
| | | | | | | | | | | | | | | | | | | | v5 (chk): complete rework, start when the first fence is emitted, stop when the last fence is signalled, make it work correctly with GPU resets, cleanup radeon_fence_wait_seq Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: take exclusive_lock in read mode during ring tests, v5Maarten Lankhorst2014-08-274-23/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This is needed for the next commit, because the lockup detection will need the read lock to run. v4 (chk): split out forced fence completion, remove unrelated changes, add and handle in_reset flag v5 (agd5f): rebase fix Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: force fence completion only on problematic rings (v2)Christian König2014-08-274-15/+8
| | | | | | | | | | | | | | | | | | | | | | | | Instead of resetting all fence numbers, only reset the number of the problematic ring. Split out from a patch from Maarten Lankhorst <maarten.lankhorst@canonical.com> v2 (agd5f): rebase build fix Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: wake up all fences on manual resetChristian König2014-08-271-0/+1
| | | | | | | | | | | | | | | | Wake up all fences when we manually trigger a reset. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add UVD fw names for older asicChristian König2014-08-271-0/+23
| | | | | | | | | | | | | | Activating the UVD support. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: enable RB_ARB before resetting the VCPUChristian König2014-08-271-2/+2
| | | | | | | | | | | | | | | | This fixes "UVD not responding, trying to reset the VCPU" messages on earlier ASICs. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: 760G/780V/880V don't have UVDAlex Deucher2014-08-272-25/+42
| | | | | | | | | | | | | | | | Don't enable UVD on these asics as they don't have UVD hardware. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: implement UVD hw workarounds for R6xx v3Christian König2014-08-272-1/+28
| | | | | | | | | | | | | | | | | | | | Only the essentials, cause this hw generation is really buggy. v2: start supporting RV670,RV620 and RV635 as well v3: activate more workarounds Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add UVD support for older asics v4Christian König2014-08-276-0/+138
| | | | | | | | | | | | | | | | | | v2: cleanup R600 support v3: rebased on current drm-fixes-3.12 v4: rebased on drm-next-3.14 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add set_uvd_clocks callback for r6xx v4Alex Deucher2014-08-272-0/+114
| | | | | | | | | | | | | | | | | | v2: wake up PLL, set [VD]CLK_SRC, cleanup code v3: handle RV670,RV635,RV620 as well v4: merge rv6xx and rs780/rs880 code, fix ref divider mask Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
| * drm/radeon: properly init UVD MC bits on R600Christian König2014-08-272-1/+7
| | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: force UVD buffers into VRAM on RS[78]80 v2Christian König2014-08-271-3/+6
| | | | | | | | | | | | | | v2: only necessary on RS[78]80 Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: move the IB test after the AGP fallbackChristian König2014-08-271-4/+4
| | | | | | | | | | | | | | | | Otherwise we won't test if the fallback to PCIe GART really worked. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Merge branch 'ttm_pfn' of git://people.freedesktop.org/~deathsimple/linux ↵Dave Airlie2014-08-2826-253/+346
|\ \ | |/ |/| | | | | | | | | | | | | into drm-next pull in placement changes radeon requires. * 'ttm_pfn' of git://people.freedesktop.org/~deathsimple/linux: drm/ttm: move fpfn and lpfn into each placement v2
| * drm/ttm: move fpfn and lpfn into each placement v2Christian König2014-08-2726-253/+346
|/ | | | | | | | | This allows us to more fine grained specify where to place the buffer object. v2: rebased on drm-next, add bochs changes as well Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
* Merge branch 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-08-2614-4/+610
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next radeon userptr support. * 'drm-next-3.18' of git://people.freedesktop.org/~agd5f/linux: drm/radeon: allow userptr write access under certain conditions drm/radeon: add userptr flag to register MMU notifier v3 drm/radeon: add userptr flag to directly validate the BO to GTT drm/radeon: add userptr flag to limit it to anonymous memory v2 drm/radeon: add userptr support v8 Conflicts: drivers/gpu/drm/radeon/radeon_prime.c
| * drm/radeon: allow userptr write access under certain conditionsChristian König2014-08-111-7/+12
| | | | | | | | | | | | | | | | It needs to be anonymous memory (no file mappings) and we are requried to install an MMU notifier. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add userptr flag to register MMU notifier v3Christian König2014-08-118-2/+298
| | | | | | | | | | | | | | | | | | | | | | Whenever userspace mapping related to our userptr change we wait for it to become idle and unmap it from GTT. v2: rebased, fix mutex unlock in error path v3: improve commit message Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add userptr flag to directly validate the BO to GTTChristian König2014-08-112-1/+18
| | | | | | | | | | | | | | This way we test userptr availability at BO creation time instead of first use. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add userptr flag to limit it to anonymous memory v2Christian König2014-08-113-1/+13
| | | | | | | | | | | | | | | | | | Avoid problems with writeback by limiting userptr to anonymous memory. v2: add commit and code comments Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add userptr support v8Christian König2014-08-1110-3/+279
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an IOCTL for turning a pointer supplied by userspace into a buffer object. It imposes several restrictions upon the memory being mapped: 1. It must be page aligned (both start/end addresses, i.e ptr and size). 2. It must be normal system memory, not a pointer into another map of IO space (e.g. it must not be a GTT mmapping of another object). 3. The BO is mapped into GTT, so the maximum amount of memory mapped at all times is still the GTT limit. 4. The BO is only mapped readonly for now, so no write support. 5. List of backing pages is only acquired once, so they represent a snapshot of the first use. Exporting and sharing as well as mapping of buffer objects created by this function is forbidden and results in an -EPERM. v2: squash all previous changes into first public version v3: fix tabs, map readonly, don't use MM callback any more v4: set TTM_PAGE_FLAG_SG so that TTM never messes with the pages, pin/unpin pages on bind/unbind instead of populate/unpopulate v5: rebased on 3.17-wip, IOCTL renamed to userptr, reject any unknown flags, better handle READONLY flag, improve permission check v6: fix ptr cast warning, use set_page_dirty/mark_page_accessed on unpin v7: add warning about it's availability in the API definition v8: drop access_ok check, fix VM mapping bits Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> (v4) Reviewed-by: Jérôme Glisse <jglisse@redhat.com> (v4) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | Merge tag 'drm-intel-next-2014-08-08' of ↵Dave Airlie2014-08-2627-398/+1281
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next - Setting dp M2/N2 values plus state checker support (Vandana Kannan) - chv power well support (Ville) - DP training pattern 3 support for chv (Ville) - cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien) - dsi video burst mode support (Shobhit) - piles of other chv fixes all over (Ville et. al.) - cleanup of the ddi translation tables setup code (Damien) - 180 deg rotation support (Ville & Sonika Jindal) * tag 'drm-intel-next-2014-08-08' of git://anongit.freedesktop.org/drm-intel: (59 commits) drm/i915: Update DRIVER_DATE to 20140808 drm/i915: No busy-loop wait_for in the ring init code drm/i915: Add sprite watermark programming for VLV and CHV drm/i915: Round-up clock and limit drain latency drm/i915: Generalize drain latency computation drm/i915: Free pending page flip events at .preclose() drm/i915: clean up PPGTT checking logic drm/i915: Polish the chv cmnlane resrt macros drm/i915: Hack to tie both common lanes together on chv drm/i915: Add cherryview_update_wm() drm/i915: Update DDL only for current CRTC drm/i915: Parametrize VLV_DDL registers drm/i915: Fill out the FWx watermark register defines drm: Resetting rotation property drm/i915: Add rotation property for sprites drm: Add rotation_property to mode_config drm/i915: Make intel_plane_restore() return an error drm/i915: Add 180 degree sprite rotation support drm/i915: Introduce a for_each_intel_encoder() macro drm/i915: Demote the DRRS messages to debug messages ...
| * | drm/i915: Update DRIVER_DATE to 20140808Daniel Vetter2014-08-081-1/+1
| | | | | | | | | | | | Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: No busy-loop wait_for in the ring init codeDaniel Vetter2014-08-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Doing a 1s wait (tops) with the cpu is a bit excessive. Tune it down like everything else in that code. v2: Also insert the missing space Chris spotted. Cc: Naresh Kumar Kachhi <naresh.kumar.kachhi@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat2014-08-082-6/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Program DDL register as part of sprite watermark programming for CHV and VLV. v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK v3: Addressed review comments by Ville - Changed Sprite DDL definitions to more generic to avoid multiple if-else - Changed bit masking to customary form - Changed to bitwise shorthand operator for sprite_dl assignment Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Round-up clock and limit drain latencyGajanan Bhat2014-08-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Round up clock computation and limit drain latency to maximum of 0x7F. Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Generalize drain latency computationGajanan Bhat2014-08-082-37/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify drain latency computation to use it for any plane. Same function can be used for primary, cursor and sprite planes. v2: Adressed review comments by Imre and Ville. - Moved clock round up in separate patch - Added WARN check for clock and pixel size - Simplified bit masking - Use cursor_base instead of reg read v3: Changed to bitwise shorthand operator for plane_dl assignment. Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Free pending page flip events at .preclose()Ville Syrjälä2014-08-083-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there are pending page flips when the fd gets closed those page flips may have events associated to them. When the page flip eventually completes it will queue the event to file_priv->event_list, but that may be too late and file_priv->event_list has already been cleaned up. Thus we leak a bit of kernel memory in the form of the event structure. To avoid such problems clear out such pending events from intel_crtc->unpin_work at ->preclose(). Any event that already made it to file_priv->event_list will get cleaned up by the drm_release_events() a bit later. We can ignore the file_priv->event_space accounting since file_priv is going away. This is already how drm core deals with pending vblank events, which are maintained by the drm core. What saves us from a total disaster (ie. dereferencing and alrady freed file_priv) is the fact that the fb descruction triggers a modeset and there we wait for pending flips. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: clean up PPGTT checking logicJesse Barnes2014-08-083-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sanitize_enable_ppgtt is the function that checks all the conditions, honoring a forced ppgtt status or doing auto-detect as necessary. Just make sure it returns the right value in all cases and use that in the macros instead of the confusing intel_enable_ppgtt() function. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> [danvet: Don't reenable full ppgtt through the backdoor.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä2014-08-082-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the semi-funky cmnlane assert/deassert macros with something a bit more conventional. Also protect the macro arguments properly (also for PHY_POWERGOOD()). Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Hack to tie both common lanes together on chvVille Syrjälä2014-08-081-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It looks like frobbing the cmnreset line on pne PHY disturbs the other PHY on chv. The result is a black screen. On HDMI it's just a flash of black, but DP usually falls over and can't get back up. As a workaround set up the power domains so that both common lane wells power up and down together. I also tried leaving the cmnreset deasserted even the if the power well goes down but that didn't seem acceptable to the PHY. Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Add cherryview_update_wm()Ville Syrjälä2014-08-081-1/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CHV has a third pipe so we need to compute the watermarks for its planes. Add cherryview_update_wm() to do just that. v2: Rebase on top of Imre's cxsr changes v3: Pass crtc to vlv_update_drain_latency() Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Update DDL only for current CRTCGajanan Bhat2014-08-081-16/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of looping through all CRTCs, update DDL for current CRTC for which watermark is being updated. CHV is confirmed to have precision of 32/64 which is same as VLV. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Gajanan Bhat <gajanan.bhat@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Parametrize VLV_DDL registersVille Syrjälä2014-08-082-70/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The VLV/CHV DDL registers are uniform, and neatly enough the register offsets are sane so we can easily unify them to a single set of defines and just pass the pipe as the parameter to compute the register offset. Note that we now fill out the drain latency for pipe C on CHV which we didn't do before. The rest of the pipe C watermarks are still untouched but that will be remedied later by adding a proper cherryview_update_wm() function. v2: Add a note about CHV pipe C changes (Paulo) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Fill out the FWx watermark register definesVille Syrjälä2014-08-082-19/+130
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add defines for all the watermark registers on modernish gmch platforms. VLV has increased the number of bits available for certain watermaks so expand the masks appropriately. Also vlv and chv have added some extra FW registers. Not sure what happened on chv because a new register called FW9 is now at the offset where FW7 was on vlv, while FW7 and FW8 (another new register) have been moved off somewhere else. Oh well, well just need two defines for FW7 then. v2: Fix DSPHOWM1 offset (Paulo) Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm: Resetting rotation propertySonika Jindal2014-08-081-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset rotation property to 0. v2: Resetting after disabling the plane Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Add rotation property for spritesVille Syrjälä2014-08-081-1/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sprite planes support 180 degree rotation. The lower layers are now in place, so hook in the standard rotation property to expose the feature to the users. v2: Moving rotation_property to mode_config Cc: dri-devel@lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm: Add rotation_property to mode_configSonika Jindal2014-08-081-0/+1
| | | | | | | | | | | | | | | | | | | | | Signed-off-by: Sonika Jindal <sonika.jindal@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Dave Airlie <airlied@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Make intel_plane_restore() return an errorVille Syrjälä2014-08-082-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Propagate the error from intel_update_plane() up through intel_plane_restore() to the caller. This will be used for rollback purposes when setting properties fails. Cc: dri-devel@lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * | drm/i915: Add 180 degree sprite rotation supportVille Syrjälä2014-08-083-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sprite planes (in fact all display planes starting from gen4) support 180 degree rotation. Add the relevant low level bits to the sprite code to make use of that feature. The upper layers are not yet plugged in. v2: HSW handles the rotated buffer offset automagically v3: BDW also handles the rotated buffer offset automagically Testcase: igt/kms_rotation_crc Cc: dri-devel@lists.freedesktop.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Sagar Kamble <sagar.a.kamble@intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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