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* clk: Make clk API return per-user struct clk instancesTomeu Vizoso2015-02-029-303/+602
* clk: Remove __clk_registerTomeu Vizoso2015-01-282-44/+0
* clk: Remove unneeded NULL checksTomeu Vizoso2015-01-281-9/+0
* clk: qoriq: Use pr_fmt()Emil Medve2015-01-281-2/+5
* clk: qoriq: Replace kzalloc() with kmalloc()Emil Medve2015-01-281-1/+1
* clk: qoriq: Make local symbol 'static'Emil Medve2015-01-281-1/+1
* clk: qoriq: Fix checkpatch type OOM_MESSAGEEmil Medve2015-01-281-12/+5
* clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCTEmil Medve2015-01-281-2/+2
* clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLYEmil Medve2015-01-281-2/+2
* clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENTEmil Medve2015-01-281-4/+4
* clk: pxa: add pxa3xx clock driverRobert Jarzmik2015-01-272-0/+365
* clk: zynq: Force CPU_2X clock to be ungatedSoren Brinkmann2015-01-271-0/+1
* Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/ker...Michael Turquette2015-01-2718-331/+1092
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| * sunxi: clk: Set sun6i-pll1 n_start = 1Hans de Goede2015-01-251-0/+1
| * clk: sunxi: rewrite sun9i_a80_get_pll4_factors()Hans de Goede2015-01-251-28/+29
| * clk: sunxi: Add driver for A80 MMC config clocks/resetsChen-Yu Tsai2015-01-203-1/+244
| * clk: sunxi: Add mod0 and mmc module clock support for A80Chen-Yu Tsai2015-01-192-2/+37
| * clk: sunxi: Add a common setup function for mmc module clocksChen-Yu Tsai2015-01-141-7/+19
| * clk: sunxi: Remove custom phase functionMaxime Ripard2015-01-142-59/+0
| * mmc: sunxi: Convert MMC driver to the standard clock phase APIMaxime Ripard2015-01-142-28/+53
| * ARM: sunxi: dt: Add sample and output mmc clocksMaxime Ripard2015-01-146-103/+265
| * clk: sunxi: Rework MMC phase clocksMaxime Ripard2015-01-142-67/+77
| * clk: sunxi: Propagate rate changes to parent for mux clocksChen-Yu Tsai2015-01-061-1/+1
| * clk: sunxi: Make the mod0 clk driver also a platform driverHans de Goede2015-01-061-3/+40
| * clk: sunxi: Fix factor clocks usage for sun9i core clocksChen-Yu Tsai2014-12-211-6/+56
| * clk: sunxi: Give sunxi_factors_register a registers parameterHans de Goede2014-12-215-14/+51
| * ARM: dts: sun8i: Add PLL6 and MBUS clock nodesChen-Yu Tsai2014-12-211-8/+24
| * ARM: dts: sun8i: Unify ahb1 clock nodesChen-Yu Tsai2014-12-211-10/+2
| * ARM: dts: sun6i: Unify ahb1 clock nodesChen-Yu Tsai2014-12-211-11/+3
| * clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-dividerChen-Yu Tsai2014-12-212-1/+209
| * clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks listChen-Yu Tsai2014-12-211-1/+0
* | Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/...Michael Turquette2015-01-272-13/+39
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| * | clk: rockchip: add a dummy clock for the watchdog pclk on rk3288Heiko Stuebner2015-01-221-0/+8
| * | clk: rockchip: add PVTM clocks on rk3288huang lin2015-01-221-2/+2
| * | clk: rockchip: use the clock ID for usbphy480m_srcKever Yang2015-01-221-1/+1
| * | Merge branch 'v3.20-clk/new-ids' into v3.20-clk/nextHeiko Stuebner2015-01-221-0/+4
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| | * | clk: rockchip: add id for watchdog pclk on rk3288Heiko Stuebner2015-01-221-0/+1
| | * | clk: rockchip: add clock IDs for the PVTM clocksHuang Lin2015-01-121-0/+2
| | * | clk: rockchip: add clock ID for usbphy480m_srcKever Yang2015-01-121-0/+1
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| * | clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow modeDoug Anderson2014-12-311-0/+14
| * | clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocksDoug Anderson2014-12-211-10/+10
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* | clk: ti: Drop use of clk-private.hStephen Boyd2015-01-274-3/+4
* | clk: ux500: Drop use of clk-private.hStephen Boyd2015-01-272-2/+0
* | clk: Export phase functionsMaxime Ripard2015-01-271-0/+2
* | devicetree: bindings: Document qcom,lccRajendra Nayak2015-01-271-0/+21
* | clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driverStephen Boyd2015-01-274-0/+645
* | clk: qcom: Add IPQ806X LPASS clock controller (LCC) driverRajendra Nayak2015-01-274-0/+495
* | dt-bindings: Add #defines for IPQ806x lpass clock controlRajendra Nayak2015-01-272-1/+30
* | clk: qcom: Add simple regmap based muxesStephen Boyd2015-01-273-0/+89
* | clk: qcom: Add support for regmap divider clocksJosh Cartwright2015-01-273-0/+100
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