| Commit message (Collapse) | Author | Age | Files | Lines |
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"New and/or improved SoC support for this release:
Marvell Berlin:
- Enable standard DT-based cpufreq
- Add CPU hotplug support
Freescale:
- Ethernet init for i.MX7D
- Suspend/resume support for i.MX6UL
Allwinner:
- Support for R8 chipset (used on NTC's $9 C.H.I.P board)
Mediatek:
- SMP support for some platforms
Uniphier:
- L2 support
- Cleaned up SMP support, etc.
plus a handful of other patches around above functionality, and a few
other smaller changes"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
ARM: uniphier: rework SMP operations to use trampoline code
ARM: uniphier: add outer cache support
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helper
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
ARM: sunxi: Add R8 support
ARM: digicolor: select pinctrl/gpio driver
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
...
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The complexity of the boot sequence of UniPhier SoC family is
a PITA due to the following hardware limitations:
[1] No dedicated on-chip SRAM
SoCs in general have small SRAM, on which a tiny firmware or a boot
loader can run before SDRAM is initialized. As UniPhier SoCs do not
have any dedicated SRAM accessible from CPUs, the locked outer cache
is used instead. Due to the ARM specification, to have access to
the outer cache, the MMU must be enabled. This is done for all CPU
cores by the program hard-wired in the boot ROM. The boot ROM code
loads a small amount of program (this is usually SPL of U-Boot) from
a non-volatile device onto the locked outer cache, and the primary
CPU jumps to it. The secondary CPUs stay in the boot ROM until they
are kicked by the primary CPU.
[2] CPUs can not directly jump to SDRAM address space
As mentioned above, the MMU is enable for all the CPUs with the page
table hard-wired in the boot ROM. Unfortunately, the page table only
has minimal sets of valid sections; all the sections of SDRAM address
space are zero-filled. That means all the CPUs, including secondary
ones, can not jump directly to SDRAM address space. So, the primary
CPU must bring up secondary CPUs to accessible address mapped onto
the outer cache, then again kick them to SDRAM address space.
Before this commit, this complex task was done with help of a boot
loader (U-Boot); U-Boot SPL brings up the secondary CPUs to the entry
of U-Boot SPL and they stay there until they are kicked by Linux.
This is not nice because a boot loader must put the secondary CPUs
into a certain state expected by the kernel. It makes difficult to
port another boot loader because the boot loader and the kernel must
work in sync to wake up the secondary CPUs.
This commit reworks the SMP operations so that they do not rely on
particular boot loader implementation; the SMP operations (platsmp.c)
put trampoline code (headsmp.S) on a locked way of the outer cache.
The secondary CPUs jump from the boot ROM to secondary_entry via the
trampoline code. The boot loader no longer needs to take care of SMP.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This commit adds support for UniPhier outer cache controller.
All the UniPhier SoCs are equipped with the L2 cache, while the L3
cache is currently only integrated on PH1-Pro5 SoC.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
Samsung SoC updates for v4.4
- use PWM lookup table with pwm_add_table() for the following boards
: s3c24xx h1940 and rx1950
: s3c64xx smdk6410, crag6410, hmt and smartq
- document: update bootloader interface on exynos542x
* tag 'samsung-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
ARM: S3C24XX: Use PWM lookup table for mach-rx1950
ARM: S3C24XX: Use PWM lookup table for mach-h1940
Signed-off-by: Olof Johansson <olof@lixom.net>
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Update the documentation about:
1. Usage of PMU_SPARE2 register.
Bootloaders on Exynos542x-based boards often use the register
PMU_SPARE2 (0x908) in the same way as on Exynos3250: as a indicator
the secondary CPU was booted on. The bootloader will set this value
to non-zero, after sucessfull power up of secondary CPU. In the same
time this booted CPU will stuck (spin) waiting for software reset.
2. Exynos542x entry address for secondary CPU boot up after system
suspend (with MCPM enabled and in non-secure mode).
See arch/arm/mach-exynos/mcpm-exynos.c for source code.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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Use a PWM lookup table to provide the PWM to the pwm-backlight device.
The driver has a legacy code path that is required only because boards
still use the legacy method of requesting PWMs by global ID. Replacing
these usages allows that legacy fallback to be removed.
Signed-off-by: Thierry Reding <thierry.reding@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
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mvebu soc for 4.4 (part 2)
- Use mac_pton() helper in the oropn5x board instead of duplicating it
- Add the broken-idle option allowing to boot boards with a mistake in
the hardware design
* tag 'mvebu-soc-4.4-2' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helper
Signed-off-by: Olof Johansson <olof@lixom.net>
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The broken-idle option can be activated from the coherency-fabric DT
node. This property allows to disable the idle capability, when the
hardware doesn't support it, like the Seagate Personal Cloud boards.
Signed-off-by: Vincent Donnefort <vdonnefort@gmail.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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Instead of custom approach let's use generic helper function.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Detlef Vollmann <dv@vollmann.ch>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Tested-by: Detlef Vollmann <dv@vollmann.ch> #on DNS-323
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
ARM: tegra: Core SoC changes for v4.4-rc1
A single patch to restore rfkill support on AC100.
* tag 'tegra-for-4.4-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: paz00: use con_id's to refer GPIO's in gpiod_lookup table
Signed-off-by: Olof Johansson <olof@lixom.net>
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Commit 72daceb9a10a ("net: rfkill: gpio: Add default GPIO driver mappings
for ACPI") removed possibility to request GPIO by table index for non-ACPI
platforms without changing its users. As result "shutdown" GPIO request
will fail if request for "reset" GPIO succeeded or "reset" will be
requested instead of "shutdown" if "reset" wasn't defined. Fix it by
making gpiod_lookup_table use con_id's instead of indexes.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Fixes: 72daceb (net: rfkill: gpio: Add default GPIO driver mappings for ACPI)
Cc: <stable@vger.kernel.org> # v3.19+
Acked-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Marc Dietrich <marvin24@gmx.de>
Tested-by: Marc Dietrich <marvin24@gmx.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux into next/soc
More SoC changes for 4.4:
- a great fix for PM/suspend/resume
* tag 'at91-ab-soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
Signed-off-by: Olof Johansson <olof@lixom.net>
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fncpy() requires that the source and the destination are both 8-byte
aligned.
Signed-off-by: Patrick Doyle <pdoyle@irobot.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Fixes: d94e688cae56 ("ARM: at91/pm: move the copying the sram function to the sram initialization phase")
Cc: <stable@vger.kernel.org> # 4.1+
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc
The i.MX SoC updates for 4.4:
- Enable suspend and cpufreq support for i.MX6UL
- Add platform level ENET initialization support for i.MX7D
* tag 'imx-soc-4.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
ARM: imx: add cpufreq device for imx6ul
ARM: imx: add enet init for i.MX7D platform
ARM: imx7d: add imx7d iomux-gpr field define
ARM: imx: add suspend/resume support for i.mx6ul
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add cpufreq device for i.MX6UL. Using the common
cpufreq of i.MX6 SOC.
Signed-off-by: Bai Ping <b51503@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add enet phy fixup, clock source init for i.MX7D platform.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add imx7d iomux-gpr field define.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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This patch adds suspend function for i.MX6UL, it supports
"standby" and "mem" mode, for "standby" mode, SoC will
enter STOP mode only, while for "mem" mode, SoC will
enter STOP mode and DDR IO will be set to low power
mode.
As i.MX6UL contains a "Cortex-A7" ARM core which has no
PL310, so we need to avoid any PL310 operations during
suspend/resume, also, we need to flush Cortex-A7's inernal
L2 cache before suspend.
Signed-off-by: Anson Huang <b20788@freescale.com>
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next/soc
Do the initial setting of the pmic wrap interrupt before requesting the interrupt.
This fixes the corner-case where the pmic is initialized by the bootloader, but
not the pmic watchdog.
Add support for active wakeup to the scpsys. This allows to keep the power of
a scpsys domain during suspend state.
With version v4.3 new subsystem clocks are added to the clock dirver. In late
init the kernel turns off all unused clocks. This can provoke a hang if
the kernel tries to access the venc and venc_lt power domain registers.
Add the necessary parent clocks for this power domains to
the scpsys so that no random hang happens.
The bootloader of mt6589, mt8135 and mt1827 does not turn on the arm-arch-timer.
As there is no opensource bootloader in the near future for this architectures
we enable the arch timer at kernel boot. We need the arch timer for SMP boot.
Add support for SMP on mt6589, mt8127 and mt8135.
* tag 'v4.3-next-soc' of https://github.com/mbgg/linux-mediatek:
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: mediatek: add scpsys support active_wakeup
soc: mediatek: Move the initial setting of pmic wrap interrupt before requesting irq.
Signed-off-by: Olof Johansson <olof@lixom.net>
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Add support for booting secondary CPUs on mt6589, mt8127
and mt8135.
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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We enable GTP6 which ungates the arch timer clock.
In the future this should be done in the bootloader.
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Yingjoe Chen <yingjoe.chen@mediatek.com>
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In kernel late init, it turns off all unused clocks, which
needs to access subsystem registers such as VENC and VENC_LT.
Accessing MT8173 VENC registers needs two top clocks, mm_sel and
venc_sel. Accessing VENC_LT registers needs mm_sel and venclt_sel.
So we need to keep these clocks on before accessing their registers.
This patch keeps venc_sel / venclt_sel clock on when
VENC / VENC_LT's power is on, to prevent system hang up while
accessing its registeres.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Register gpd_dev_ops.active_wakeup function to support keep power
during suspend state. And add flag to each power domain to
decide whether keep power during suspend or not.
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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requesting irq.
The watchdog may not be initialized by the bootloader, even if the rest
of the pwrap is. Move the watchdog initialization out of pwrap_init() to
make sure the watchdog is always initialized and not only when the pwrap
is uninitialized.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc
Allwinner core changes for 4.4
Add support for the Allwinner R8 SoC used in the CHIP.
* tag 'sunxi-core-for-4.4' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
ARM: sunxi: Add R8 support
Signed-off-by: Olof Johansson <olof@lixom.net>
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The R8 is a new Allwinner SoC based on the A13. While both are very
similar, there's still a few differences. Introduce a new compatible to
deal with them.
In order to have a consistent naming, instead of mentioning the Allwinner
A series as the machine name, switch to sun4i/sun5i like what is done for
the other families.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Stephen Boyd <sboyd@codeaurora.org>
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git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Merge "Marvell Berlin SoC for 4.4 take 2" from Sebastian Hesselbarth:
- use the non-self-clearing reset register
- add cpu hotplug support
* tag 'berlin-soc-for-4.4-2' of git://git.infradead.org/users/hesselba/linux-berlin:
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
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Add cpu hotplug support for berlin SoCs such as BG2 and BG2Q. These SoC
don't support power off cpu independently, but we also want cpu hotplug
support in these SoCs. We achieve this goal by putting the dying CPU in
WFI state after the coherency is disabled, then asserting the dying CPU
reset bit to put the CPU in reset state.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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In Berlin SoCs, there are two kinds of cpu reset control registers: the
first one's corresponding bits will be self-cleared after some cycles,
while the second one's bits won't. Previously the first kind of reset
control register is used, this patch uses the second kind one to prepare
for the next hotplug commit.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into next/soc
Merge "ARM Keystone SOC driver updates for 4.4" from Santosh Shilimkar:
Documentation and support to be able to load the PDSP
firmware necessary for accumulator operation.
* tag 'keystone-driver-soc_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone:
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
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acc channels are available only if accumulator PDSP is loaded and
running in the SoC. As this requires firmware and user may not have
firmware in the file system, make the accumulator queue support
available in qmss driver optional. To use accumulator queus user needs
to add firmware to the file system and boot up kernel.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Currently firmware file name is included in the DTS. This is not scalable
as user has to change the DTS if they need upgrade to a new firmware.
Instead, add the firmware file name in the driver itself. As long as there
is no API change, new firmware upgrade is easy and require no driver
change. User is expected to copy the firmware image to the file system
and add a sym link to the new firmware for doing an upgrade. Driver add
a array of firmware file names to search for the available firmware blobs.
This scheme also prepare the driver for future changes to API if ever
happens. In such case it is assumed that driver needs to change to
accommodate the new firmware and new firmware file name will get added to
the array.
Also update the DT document to remove the firmware attribute and add
description about firmware in the driver documentation.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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Add documentation for knav qmss driver.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
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next/soc
Merge "Broadcom soc changes for v4.4 (try 2)" from Florian Fainelli:
This pull request contains the following Broadcom SoC platform and driver changes:
- Brian Norris create a drivers/soc/brcmstb/ stub as a place holder for SoC-specific
code which is coming next
- Florian Fainelli adds support for configuring the BCM7xxx SoCs Bus Interface Unit
with their specific write-pairing setting, which must be saved and restored during
system-wide suspend/resume, and consequently updates the brcmstb machine code to
initialize the BIU
- Jon Mason adds support for the Northstar Plus SoCs by introducing a custom machine
descriptor matching their compatible string and setting up the PL310 L2 cache and
enabling the relevant ARM errata for their Cortex-A9
* tag 'arm-soc/for-4.4/soc' of http://github.com/Broadcom/stblinux:
ARM: brcmstb: Setup BIU control registers during boot
soc: brcmstb: Add Bus Interface Unit control setup
soc: add stubs for brcmstb SoC's
ARM: NSP: Add basic support for Broadcom Northstar Plus SoC
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Call brcmstb_biuctrl_init() in brcmstb's init_irq machine descriptor
callback since we need to setup the Bus Interface Unit before SMP in
particular, but we also need to be able to remap registers.
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Broadcom STB SoCs (brcmstb) require an early setup of their Bus
Interface Unit control register, this needs to happen before SMP is
brought up because it affects how the CPU complex will be interfaced to
the memory controller.
Add support code which properly initializes the BIU registers based on
whether "brcm,write-pairing" is present in Device Tree, and take care of
saving and restoring credit register settings during system-wide
suspend/resume operations.
Acked-by: Gregory Fong <gregory.0xf0@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Used on BCM7xxx Set-Top Box chips (e.g., BCM7445).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Broadcom Northstar Plus family of SoCs are used for switching
control and management applications as well as residential
router/gateway applications. The SoC features dual core Cortex
A9 ARM CPUs, integrating several peripheral interfaces including
multiple Gigabit Ethernet PHYs, DDR3 memory, PCIE Gen-2, USB 2.0
and USB 3.0, serial and NAND flash, SATA and several other IO
controllers.
Signed-off-by: Kapil Hali <kapilh@broadcom.com>
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Acked-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Merge "Marvell SoC for 4.4 take 1" from Sebastian Hesselbarth:
- register cpufreq-dt device
* tag 'berlin-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin:
ARM: berlin: register cpufreq-dt
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The Berlin SoCs use cpufreq-dt for cpufreq. Register a platform device.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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git://git.infradead.org/users/hesselba/linux-berlin into next/soc
Merge "Marvell Berlin ARM64 SoC for 4.4 take 1" from Sebastian Hesselbarth:
- enable ARCH_REQUIRE_GPIOLIB for DW GPIO driver
* tag 'berlin64-soc-for-4.4-1' of git://git.infradead.org/users/hesselba/linux-berlin:
arm64: berlin: enable ARCH_REQUIRE_GPIOLIB
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All berlin SoCs have GPIOs driven by the dwapb GPIO driver. Add GPIOLIB
as a dependency to be able to support them.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
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Merge "mvebu soc for 4.4 (part 1)" from Gregory CLEMENT:
L2 caches optimization for Armada XP
* tag 'mvebu-soc-4.4-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: add support to clear shared L2 bit on Armada XP
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For optimal performance, in a HW I/O coherency context such as the one
used on Armada XP, the shared L2 bit of the CPU configuration register
should be cleared.
This commit adjusts the coherency fabric code used by Marvell EBU
processors to clear this bit on Armada XP. Since it's a per-CPU
register, it's cleared in set_cpu_coherent() for the boot CPU, and
through a CPU notifier for the non-boot CPUs.
[gregory.clement@free-electrons.com: rebasd on 4.3-rc1]
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
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