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* staging: imx-drm-core: replace drm_get_connector_name() with direct name ↵Jani Nikula2014-06-041-1/+1
| | | | | | | | | | | | | | | | | field use Generated using semantic patch: @@ expression E; @@ - drm_get_connector_name(E) + E->name Acked-by: David Herrmann <dh.herrmann@gmail.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/qxl: use surface_id 0 for primary surface on all monitorsDavid Mansfield2014-06-041-0/+4
| | | | | | | | | | | | | | | | | | spice-server and downstream code expect that the primary surface will always have surface_id = 0, while in reality, once allocated, the surface_id in qxl.ko is NEVER 0. In a dual head environment, all monitors render portions of the primary surface. However, when the monitor config events are generated and sent, the primary surface is only mapped to the correct identifier (i.e. 0) for the primary head (where crtc index is 0). The fix is to look at the "primary" flag in the bo and always use id 0, irrespective of which head is being configured. [airlied: qxl hw really needs to be fixed to scanout surfaces] Signed-off-by: Dave Airlie <airlied@redhat.com>
* drm/radeon: rework page flip handling v4Christian König2014-06-043-112/+147
| | | | | | | | | | | | | | Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling v4: update crtc->primary->fb when the flip actually happens Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
* Revert "drm/radeon: rework page flip handling v3"Dave Airlie2014-06-043-150/+115
| | | | | | This reverts commit 1aab5514ca9604e0263f658a067da0189c86a35b. Apply the fixed up version instead.
* Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie2014-06-0340-607/+1135
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into drm-next Highlights: - GPUVM opimtizations - HDMI audio cleanups - Deep color HDMI support - more bug fixes, cleanups * 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux: (29 commits) drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color. drm/edid: Parse and handle HDMI deep color modes. drm/radeon: Limit hdmi deep color bit depth to 12 bpc. drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2) drm/radeon: fix pll setup for hdmi deep color (v7) drm/radeon: use hw cts/n values for deep color drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmi drm/radeon/atom: fix dithering on certain panels drm/radeon: optimize CIK VM handling v2 drm/radeon: optimize SI VM handling drm/radeon: add define for flags used in R600+ GTT drm/radeon: rework page flip handling v3 drm/radeon: separate vblank and pflip crtc handling drm/radeon: split page flip and pending callback drm/radeon: remove drm_vblank_get|put from pflip handling drm/radeon: remove (pre|post)_page_flip callbacks drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devices drm/radeon: fix typo in radeon_connector_is_dp12_capable() radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770 vgaswitcheroo: switch the mux to the igp on power down when runpm is enabled ...
| * drm/edid: Add quirk for Sony PVM-2541A to get 12 bpc hdmi deep color.Mario Kleiner2014-06-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | The Sony PVM-2541A OLED high precision color display supports both 10 bpc and 12 bpc hdmi deep color input, but its edid does not signal any deep color support. Add a quirk to force it being treated as a 12 bpc panel. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/edid: Parse and handle HDMI deep color modes.Mario Kleiner2014-06-022-2/+113
| | | | | | | | | | | | | | | | | | Check the HDMI cea block for deep color mode bits. If available, assign the highest supported bpc for a hdmi display, corresponding to the given deep color modes. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: Limit hdmi deep color bit depth to 12 bpc.Mario Kleiner2014-06-021-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCE-4/5/6 can't support more than 12 bpc deep color over hdmi, so clamp to 12 bpc when a hdmi deep color capable display is connected. This even makes sense on DCE-8+, which could do up to 16 bpc, as driving with more than 12 bpc would only waste video bandwidth as long as we don't support framebuffers with more than 12 bpc depth. On pre-DCE4 we clamp hdmi bit depth to 8 bpc, as those asics don't support hdmi deep color. Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: Setup HDMI_CONTROL for hdmi deep color gcp's (v2)Alex Deucher2014-06-022-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | Program HDMI_CONTROL to send general control packets for hdmi deep color mode signalling at every video frame if bpc > 8. This is only supported on evergreen / DCE-4 and later. v2: rebase Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: fix pll setup for hdmi deep color (v7)Alex Deucher2014-06-021-9/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Need to adjust the pll up for deep color modes. Additionally, the atom bpc defines were wrong in certain cases. v2: set the adjusted clock to the pll clock for hdmi deep color. This fixes display and audio issues with deep color as reported by Andy Furniss <adf.lists@gmail.com> v3: set crtc_clock as well v4: setcrtcinfo on the adjusted mode v5: just use the adjusted clock for setting the pll v6: only use the adjusted clock for hdmi v7: only DCE5 and DCE6 and bpc > 8 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: use hw cts/n values for deep colorAlex Deucher2014-06-021-3/+15
| | | | | | | | | | | | | | I'm not really sure how these should be calculated for deep color. The hw generated values seem to work. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: only apply hdmi bpc pll flags when encoder mode is hdmiAlex Deucher2014-06-021-22/+26
| | | | | | | | | | | | | | May fix display issues with non-HDMI displays. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon/atom: fix dithering on certain panelsAlex Deucher2014-06-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | We need to specify the encoder mode as LVDS for eDP when using the Crtc_Source atom table in order to properly set up the FMT hardware. bug: https://bugs.freedesktop.org/show_bug.cgi?id=73911 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon: optimize CIK VM handling v2Christian König2014-06-021-1/+20
| | | | | | | | | | | | | | | | | | Fill VM page tables from the GART page table if applicable. v2: fix copy&paste error Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: optimize SI VM handlingChristian König2014-06-021-1/+19
| | | | | | | | | | | | | | Fill VM page tables from the GART page table if applicable. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add define for flags used in R600+ GTTChristian König2014-06-022-8/+5
| | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: rework page flip handling v3Christian König2014-06-023-115/+150
| | | | | | | | | | | | | | | | | | | | | | | | Instead of trying to flip inside the vblank period when the buffer is idle, offload blocking for idle to a kernel thread and program the flip directly into the hardware. v2: add error handling, fix EBUSY handling v3: add proper exclusive_lock handling Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: separate vblank and pflip crtc handlingChristian König2014-06-028-26/+56
| | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: split page flip and pending callbackChristian König2014-06-028-15/+88
| | | | | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: remove drm_vblank_get|put from pflip handlingChristian König2014-06-021-17/+0
| | | | | | | | | | | | | | We activate the VBLANK irq manually anyway, so this is unnecessary. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: remove (pre|post)_page_flip callbacksChristian König2014-06-027-128/+2
| | | | | | | | | | | | | | They are doing the same on all generations anyway. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon/dp: fix lane/clock setup for dp 1.2 capable devicesAlex Deucher2014-06-021-2/+15
| | | | | | | | | | | | | | | | | | Only DCE5+ asics support DP 1.2. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon: fix typo in radeon_connector_is_dp12_capable()Alex Deucher2014-06-021-1/+1
| | | | | | | | | | | | | | | | | | We were checking the ext clock rather than the display clock. Noticed by ArtForz on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * radeon: Remove useless quirk for zx1/FireGL X1 combo introduced with fdo #7770Émeric MASCHINO2014-06-021-3/+0
| | | | | | | | | | | | | | | | | | | | Removes useless quirk a7f465f73363fce409870f62173d518b1bc02ae6 introduced with fdo #7770 as a failed attempt to minimize stability issues with hp zx1 chipset/ ATI FireGL X1 graphics adapter configuration (see http://marc.info/?l=linux-ia64&m=140077543819871&w=2 for details/reason) Signed-off-by: Émeric MASCHINO <emeric.maschino@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * vgaswitcheroo: switch the mux to the igp on power down when runpm is enabledAlex Deucher2014-06-021-1/+2
| | | | | | | | | | | | | | | | | | | | Avoids blank screens on muxed systems when runpm is active. bug: https://bugs.freedesktop.org/show_bug.cgi?id=75917 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| * drm/radeon: use NULL instead of zero in clearstate headersMichele CURTI2014-06-023-8/+8
| | | | | | | | | | Signed-off-by: Michele Curti <michele.curti@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: use NULL instead of zero in object functionsMichele CURTI2014-06-022-2/+2
| | | | | | | | | | Signed-off-by: Michele Curti <michele.curti@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon/hdmi: DCE2: simplify audio workaroundRafał Miłecki2014-06-021-60/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Thanks to advanced RE of fglrx we finally know what exactly needs to be handled of AFMT change. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon/hdmi: DCE2: update setmodeRafał Miłecki2014-06-022-37/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231 Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon/hdmi: DCE3: clean ACR controlRafał Miłecki2014-06-022-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon/hdmi: use separated file for DCE 3.1/3.2 codeRafał Miłecki2014-06-025-141/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and DCE 3. The order of setting registers and sets of registers are different. It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they have few differences as well. For now separate DCE 2 and DCE 3 path, so we can work on it without a risk of breaking DCE 3.1+. This has been tested for possible regressions on DCE32 HD4550 (RV710). Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2Christian König2014-06-027-1/+9
| | | | | | | | | | | | | | | | | | | | This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add large PTE support for NI, SI and CIK v5Christian König2014-06-025-9/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements support for VRAM page table entry compression. PTE construction is enhanced to identify physically contiguous page ranges and mark them in the PTE fragment field. L1/L2 TLB support is enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly improving TLB utilization for VRAM allocations. Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn. Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS on default settings at 1920x1200 resolution with vsync disabled. See main comment in radeon_vm.c for a technical description. v2 (chk): rebased and simplified. v3 (chk): add missing hw setup v4 (chk): rebased on current drm-fixes-3.15 v5 (chk): fix comments and commit text Signed-off-by: Jay Cornwall <jay@jcornwall.me> Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| * drm/radeon: add a i2c bus mutexAlex Deucher2014-06-024-8/+37
| | | | | | | | | | | | | | | | The i2c and aux buses use the same pads so add a mutex to protect access to the pads. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com>
* | Merge tag 'drm-intel-next-2014-05-23' of ↵Dave Airlie2014-06-0249-1771/+6778
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm-intel into drm-next - prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) - refactoring and improvements for drm_irq.c merged through drm-intel-next - g4x/ilk reset improvements (Ville) - removal of encoder->mode_set - moved audio state tracking into pipe_config - shuffled fb pinning out of the platform crtc modeset callbacks into core code - userptr support (Chris) - OOM handling improvements from Chris, with now have a neat oom notifier which jumps additional debug information. - topdown allocation of ppgtt PDEs (Ben) - fixes and small improvements all over * tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits) drm/i915: Kill private_default_ctx off drm/i915: s/i915_hw_context/intel_context drm/i915: Split the ringbuffers from the rings (3/3) drm/i915: Split the ringbuffers from the rings (2/3) drm/i915: Split the ringbuffers from the rings (1/3) drm/i915: s/intel_ring_buffer/intel_engine_cs drm/i915: disable GT power saving early during system suspend drm/i915: fix possible RPM ref leaking during RPS disabling drm/i915: remove user GTT mappings early during runtime suspend drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk drm/i915: Fix gen2 and hsw+ scanline counter drm/i915: Draw a picture about video timings drm/i915: Improve gen3/4 frame counter drm/i915: Add a small adjustment to the pixel counter on interlaced modes drm/i915: Hold CRTC lock whilst freezing the planes drm/i915: Only discard backing storage on releasing the last ref drm/i915: Wait for pending page flips before enabling/disabling the primary plane drm/i915: grab the audio power domain when enabling audio on HSW+ drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off drm/i915: move bsd dispatch index somewhere better ...
| * drm/i915: Kill private_default_ctx offOscar Mateo2014-05-223-14/+8
| | | | | | | | | | | | | | It's barely alive now anyway, so give it the "coup de grâce". Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: s/i915_hw_context/intel_contextOscar Mateo2014-05-229-40/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Up until now, contexts had one (and only one) backing object that was used by the hardware to save/restore render ring contexts (via the MI_SET_CONTEXT command). Other rings did not have or need this, so our i915_hw_context struct had a 1:1 relationship with a a real HW context. With Logical Ring Contexts and Execlists, this is not possible anymore: all rings need a backing object, and it cannot be reused. To prepare for that, rename our contexts to the more generic term intel_context. No functional changes. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Split the ringbuffers from the rings (3/3)Oscar Mateo2014-05-224-60/+72
| | | | | | | | | | | | | | | | | | | | | | Manual cleanup after the previous Coccinelle script. Yes, I could write another Coccinelle script to do this but I don't want labor-replacing robots making an honest programmer's work obsolete (also, I'm lazy). Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Split the ringbuffers from the rings (2/3)Oscar Mateo2014-05-226-92/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This refactoring has been performed using the following Coccinelle semantic script: @@ struct intel_engine_cs r; @@ ( - (r).obj + r.buffer->obj | - (r).virtual_start + r.buffer->virtual_start | - (r).head + r.buffer->head | - (r).tail + r.buffer->tail | - (r).space + r.buffer->space | - (r).size + r.buffer->size | - (r).effective_size + r.buffer->effective_size | - (r).last_retired_head + r.buffer->last_retired_head ) @@ struct intel_engine_cs *r; @@ ( - (r)->obj + r->buffer->obj | - (r)->virtual_start + r->buffer->virtual_start | - (r)->head + r->buffer->head | - (r)->tail + r->buffer->tail | - (r)->space + r->buffer->space | - (r)->size + r->buffer->size | - (r)->effective_size + r->buffer->effective_size | - (r)->last_retired_head + r->buffer->last_retired_head ) @@ expression E; @@ ( - LP_RING(E)->obj + LP_RING(E)->buffer->obj | - LP_RING(E)->virtual_start + LP_RING(E)->buffer->virtual_start | - LP_RING(E)->head + LP_RING(E)->buffer->head | - LP_RING(E)->tail + LP_RING(E)->buffer->tail | - LP_RING(E)->space + LP_RING(E)->buffer->space | - LP_RING(E)->size + LP_RING(E)->buffer->size | - LP_RING(E)->effective_size + LP_RING(E)->buffer->effective_size | - LP_RING(E)->last_retired_head + LP_RING(E)->buffer->last_retired_head ) Note: On top of this this patch also removes the now unused ringbuffer fields in intel_engine_cs. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> [danvet: Add note about fixup patch included here.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Split the ringbuffers from the rings (1/3)Oscar Mateo2014-05-222-9/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As advanced by the previous patch, the ringbuffers and the engine command streamers belong in different structs. This is so because, while they used to be tightly coupled together, the new Logical Ring Contexts (LRC for short) have a ringbuffer each. In legacy code, we will use the buffer* pointer inside each ring to get to the pertaining ringbuffer (the actual switch will be done in the next patch). In the new Execlists code, this pointer will be NULL and we will use instead the one inside the context instead. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: s/intel_ring_buffer/intel_engine_csOscar Mateo2014-05-2219-265/+265
| | | | | | | | | | | | | | | | | | | | | | In the upcoming patches we plan to break the correlation between engine command streamers (a.k.a. rings) and ringbuffers, so it makes sense to refactor the code and make the change obvious. No functional changes. Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: disable GT power saving early during system suspendImre Deak2014-05-222-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Atm, we disable GT power saving during the end of the suspend sequence in i915_save_state(). Doing the disabling at that point seems arbitrary. One reason to disable it early though is to have a quiescent HW state before we do anything else (for example save registers). So move the disabling earlier, which also takes care canceling of the deferred RPS enabling work done by intel_disable_gt_powersave(). Note that after the move we'll call intel_disable_gt_powersave() only in case modeset is enabled, but that's anyway the only case where we have it enabled in the first place. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Robert Beckett <robert.beckett@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: fix possible RPM ref leaking during RPS disablingImre Deak2014-05-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit c6df39b5ea6342323a42edfbeeca0a28c643d7ae Author: Imre Deak <imre.deak@intel.com> Date: Mon Apr 14 20:24:29 2014 +0300 drm/i915: get a runtime PM ref for the deferred GT powersave enabling I added an RPM get-ref when enabling RPS from a deferred work, but forgot to add the corresponding put-ref when canceling the work. This may leave RPM disabled. Note that the race is real since we run the rps enabling with a delayed work item after resume, so leaves enough time (in contrived examples) to fit a quick autoresum in. Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Robert Beckett <robert.beckett@intel.com> Testecase: igt/pm_rpm/system-suspend [danvet: Mention testcase and add note.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: remove user GTT mappings early during runtime suspendImre Deak2014-05-221-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently user space can access GEM buffers mapped to GTT through existing mappings concurrently while the platform specific suspend handlers are running. Since these handlers may change the HW state in a way that would break such accesses, remove the mappings before calling the handlers. Spotted by Ville. Also Chris pointed out that the lists that i915_gem_release_all_mmaps() walks through need dev->struct_mutex, so take this lock. There is a potential deadlock against a concurrent RPM resume, resolve this by aborting and rescheduling the suspend (Daniel). v2: - take struct_mutex around i915_gem_release_all_mmaps() (Chris, Daniel) Signed-off-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Robert Beckett <robert.beckett@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elkVille Syrjälä2014-05-222-1/+39
| | | | | | | | | | | | | | | | | | Apparently we need to disable VCP unit clock gating around media reset on g4x. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Fix gen2 and hsw+ scanline counterVille Syrjälä2014-05-223-10/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On gen2 the scanline counter behaves a bit differently from the later generations. Instead of adding one to the raw scanline counter value, we must subtract one. On HSW/BDW the scanline counter requires a +2 adjustment on HDMI outputs. DP outputs on the on the other require the typical +1 adjustment. As the fixup we must apply to the hardware scanline counter depends on several factors, compute the desired offset at modeset time and tuck it away for when it's needed. v2: Clarify HSW+ situation Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: "Akash Goel <akash.goels@gmail.com>" Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78997 Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Draw a picture about video timingsVille Syrjälä2014-05-221-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The docs are a bit lacking when it comes to describing when certain timing related events occur in the hardware. Draw a picture which tries to capture the most important ones. v2: Clarify a few details (Imre) v3: Add HSW+ HDMI scanline counter numbers Acked-by: Imre Deak <imre.deak@intel.com> Reviewed-by: Akash Goel <akash.goels@gmail.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>" Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Improve gen3/4 frame counterVille Syrjälä2014-05-221-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the logic to fix up the frame counter on gen3/4 assumes that start of vblank occurs at vblank_start*htotal pixels, when in fact it occurs htotal-hsync_start pixels earlier. Apply the appropriate adjustment to make the frame counter more accurate. Also fix the vblank start position for interlaced display modes. Reviewed-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: "Akash Goel <akash.goels@gmail.com>" Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>" Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Add a small adjustment to the pixel counter on interlaced modesVille Syrjälä2014-05-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In interlaced modes, the pixel counter counts all pixels, so one field will have htotal more pixels. In order to avoid the reported position from jumping backwards when the pixel counter is beyond the length of the shorter field, just clamp the position the length of the shorter field. This matches how the scanline counter based position works since the scanline counter doesn't count the two half lines. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: "Akash Goel <akash.goels@gmail.com>" Reviewed-by: "Sourab Gupta <sourabgupta@gmail.com>" Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| * drm/i915: Hold CRTC lock whilst freezing the planesChris Wilson2014-05-221-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Daniel keeps on ramping up the warning level of the DRM and our display core to make it complain whenever the locking rules are not followed. This caught commit 24576d23976746cb52e7700c4cadbf4bc1bc3472 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Mar 26 09:25:45 2013 -0700 drm/i915: enable VT switchless resume v3 introducing an unlocked access to the CRTC whilst disabling it for suspend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78114 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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