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* dma-buf: Expose buffer size to userspace (v2)Christopher James Halse Rogers2013-09-102-0/+41
| | | | | | | | | | | | | | | | Each dma-buf has an associated size and it's reasonable for userspace to want to know what it is. Since userspace already has an fd, expose the size using the size = lseek(fd, SEEK_END, 0); lseek(fd, SEEK_CUR, 0); idiom. v2: Added Daniel's sugeested documentation, with minor fixups Signed-off-by: Christopher James Halse Rogers <christopher.halse.rogers@canonical.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
* dma-buf: Check return value of anon_inode_getfileTuomas Tynkkynen2013-09-101-1/+4
| | | | | | | anon_inode_getfile might fail, so check its return value. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Signed-off-by: Sumit Semwal <sumit.semwal@linaro.org>
* Merge tag 'dmaengine-3.12' of ↵Linus Torvalds2013-09-098-248/+146
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/djbw/dmaengine Pull dmaengine update from Dan Williams: "Collection of random updates to the core and some end-driver fixups for ioatdma and mv_xor: - NUMA aware channel allocation - Cleanup dmatest debugfs interface - ioat: make raid-support Atom only - mv_xor: big endian Aside from the top three commits these have all had some soak time in -next. The top commit fixes a recent build breakage. It has been a long while since my last pull request, hopefully it does not show. Thanks to Vinod for keeping an eye on drivers/dma/ this past year" * tag 'dmaengine-3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/djbw/dmaengine: dmaengine: dma_sync_wait and dma_find_channel undefined MAINTAINERS: update email for Dan Williams dma: mv_xor: Fix incorrect error path ioatdma: silence GCC warnings dmaengine: make dma_channel_rebalance() NUMA aware dmaengine: make dma_submit_error() return an error code ioatdma: disable RAID on non-Atom platforms and reenable unaligned copies mv_xor: support big endian systems using descriptor swap feature mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel} dmatest: print message on debug level in case of no error dmatest: remove IS_ERR_OR_NULL checks of debugfs calls dmatest: make module parameters writable
| * dmaengine: dma_sync_wait and dma_find_channel undefinedJon Mason2013-09-091-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | dma_sync_wait and dma_find_channel are declared regardless of whether CONFIG_DMA_ENGINE is enabled, but calling the function without CONFIG_DMA_ENGINE enabled results "undefined reference" errors. To get around this, declare dma_sync_wait and dma_find_channel as inline functions if CONFIG_DMA_ENGINE is undefined. Signed-off-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * MAINTAINERS: update email for Dan WilliamsDan Williams2013-09-091-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | Returned to intel.com Cc: Vinod Koul <vinod.koul@intel.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Jon Mason <jon.mason@intel.com> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Neil Brown <neilb@suse.de> Cc: Shaohua Li <shli@kernel.org> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * dma: mv_xor: Fix incorrect error pathSachin Kamat2013-09-091-4/+2
| | | | | | | | | | | | | | | | | | Return directly if memory allocation fails. There is no need of dma_free_coherent(). Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Cc: Saeed Bishara <saeed@marvell.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * ioatdma: silence GCC warningsPaul Bolle2013-08-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building dma_v3.o triggers a GCC warning: drivers/dma/ioat/dma_v3.c: In function ‘__ioat3_prep_pq16_lock’: drivers/dma/ioat/dma_v3.c:264:11: warning: array subscript is below array bounds [-Warray-bounds] drivers/dma/ioat/dma_v3.c:264:11: warning: array subscript is below array bounds [-Warray-bounds] This warning is caused by pq16_set_src(). It uses "int idx" as an index to an eight element array. Changing "idx" to "unsigned" silences this warning. Apparently GCC can then determine that "idx" will never be negative. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * dmaengine: make dma_channel_rebalance() NUMA awareBrice Goglin2013-08-221-28/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_channel_rebalance() currently distributes channels by processor ID. These IDs often change with the BIOS, and the order isn't related to the DMA channel list (related to PCI bus ids). * On my SuperMicro dual E5 machine, first socket has processor IDs [0-7] (and [16-23] for hyperthreads), second socket has [8-15]+[24-31] => channels are properly allocated to local CPUs. * On Dells R720 with same processors, first socket has even processor IDs, second socket has odd numbers => half the processors get channels on the remote socket, causing cross-NUMA traffic and lower DMA performance. Change nth_chan() to return the channel with min table_count and in the NUMA node of the given CPU, if any. If none, the (non-local) channel with min table_count is returned. nth_chan() is therefore renamed into min_chan() since we don't iterate until the nth channel anymore. In practice, the behavior is the same because first channels are taken first and are then ignored because they got an additional reference. The new code has a slightly higher complexity since we always scan the entire list of channels for finding the minimal table_count (instead of stopping after N chans), and because we check whether the CPU is in the DMA device locality mask. Overall we still have time complexity = number of chans x number of processors. This rebalance is rarely used, so this won't hurt. On the above SuperMicro machine, channels are still allocated the same. On the Dells, there are no locality issue anymore (MEMCPY channel X goes to processor X and to its hyperthread sibling). Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr> Signed-off-by: Dan Williams <djbw@fb.com>
| * dmaengine: make dma_submit_error() return an error codeDan Carpenter2013-08-221-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem here is that the dma_xfer() functions in drivers/ata/pata_arasan_cf.c and drivers/mtd/nand/fsmc_nand.c expect dma_submit_error() to return an error code so they return 1 when they intended to return a negative. So far as I can tell, none of the ->tx_submit() functions ever do return error codes so this patch should have no effect in the current code. I also changed it from a define to an inline. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * ioatdma: disable RAID on non-Atom platforms and reenable unaligned copiesBrice Goglin2013-08-221-23/+1
| | | | | | | | | | | | | | | | | | | | | | Disable RAID on non-Atom platform and remove related fixups such as the 64-byte alignement restriction on legacy DMA operations (introduced in commit f26df1a1 as a workaround for silicon errata). Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr> Acked-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Jon Mason <jon.mason@intel.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * mv_xor: support big endian systems using descriptor swap featureThomas Petazzoni2013-08-222-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv_xor driver had never been used in a big-endian context, and therefore was not using the hardware features to support such an execution environment. The hardware provides a "descriptor swap" bit that automatically swaps the bytes of the DMA descriptors, within blocks of 8 bytes. This requires a different DMA descriptor layout on big-endian systems, as well as enabling this "descriptor swap" bit. This mechanism is exactly identical to the one already used in the mv643xx_eth network driver and the mvneta network driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * mv_xor: use {readl, writel}_relaxed instead of __raw_{readl, writel}Thomas Petazzoni2013-08-221-18/+18
| | | | | | | | | | | | | | | | | | | | In order to support big-endian execution, the mv_xor driver is changed to use the readl_relaxed() and writel_relaxed() accessors that properly convert from the CPU endianess to the device endianess (which in the case of Marvell XOR hardware is always little-endian). Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * dmatest: print message on debug level in case of no errorAndy Shevchenko2013-08-221-1/+5
| | | | | | | | | | | | | | | | | | Let's move the behaviour of printing no error message back to the pre v3.10 times. It means we will use debug level in the described case, and a warning level otherwise. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * dmatest: remove IS_ERR_OR_NULL checks of debugfs callsAndy Shevchenko2013-08-221-12/+5
| | | | | | | | | | | | | | | | There is a really little chance when we are able to create a directory and are not able to create nodes under it. So, this patch just removes those checks. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Dan Williams <djbw@fb.com>
| * dmatest: make module parameters writableAndy Shevchenko2013-08-222-146/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The debugfs interface brought a copy of the test case parameters. This makes different set of values under /sys/module/dmatest/parameters/ and /sys/kernel/debug/dmatest/. The user might be confused by the divergence of values. The proposed solution in this patch is to make module parameters writable and remove them from the debugfs. Though we're still using debugfs to control test runner and getting results. Documentation part is updated accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Suggested-by: Dan Williams <djbw@fb.com> Signed-off-by: Dan Williams <djbw@fb.com>
* | Merge tag 'late-for-linus' of ↵Linus Torvalds2013-09-0969-1082/+6486
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Kevin Hilman: "These are changes that arrived a little late before the merge window, or had dependencies on previous branches. Highlights: - ux500: misc. cleanup, fixup I2C devices - exynos: DT updates for RTC; PM updates - at91: DT updates for NAND; new platforms added to generic defconfig - sunxi: DT updates: cubieboard2, pinctrl driver, gated clocks - highbank: LPAE fixes, select necessary ARM errata - omap: PM fixes and improvements; OMAP5 mailbox support - omap: basic support for new DRA7xx SoCs" * tag 'late-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (60 commits) ARM: dts: vexpress: Add CCI node to TC2 device-tree ARM: EXYNOS: Skip C1 cpuidle state for exynos5440 ARM: EXYNOS: always enable PM domains support for EXYNOS4X12 ARM: highbank: clean-up some unused includes ARM: sun7i: Enable the A20 clocks in the DTSI ARM: sun6i: Enable clock support in the DTSI ARM: sun5i: dt: Use the A10s gates in the DTSI ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: dts: add ADC device tree node for exynos5420/5250 ARM: dts: Add RTC DT node to Exynos5420 SoC ARM: dts: Update the "status" property of RTC DT node for Exynos5250 SoC ARM: dts: Fix the RTC DT node name for Exynos5250 irqchip: mmp: avoid to include irqs head file ARM: mmp: avoid to include head file in mach-mmp irqchip: mmp: support irqchip irqchip: move mmp irq driver ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ...
| * | ARM: dts: vexpress: Add CCI node to TC2 device-treeJon Medhurst (Tixy)2013-08-301-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Versatile Express V2P-CA15_A7 (aka TC2) has a CCI-400 which is needed to get Multi-Cluster Power Management (MCPM) working. Signed-off-by: Jon Medhurst <tixy@linaro.org> Acked-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Olof Johansson <olof@lixom.net>
| * | Merge tag 'omap-for-v3.12/dra7xx-prcm' of ↵Olof Johansson2013-08-2929-15/+5693
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/all From Tony Lindgren: Add basic support for devices on dra7xx by adding the PRCM and hwmod parts the same way as for other omaps. This is still needed in addition to device tree support for things like power management. Via Paul Walmsley <paul@pwsan.com>: This series adds basic TI DRA7xx PRCM and hwmod support. Basic test logs are available here: http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/ Note that DRA7xx could not be tested locally, since I don't have a board. * tag 'omap-for-v3.12/dra7xx-prcm' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: DRA7: Enable PM framework initializations ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC data ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instance ARM: OMAP: DRA7: powerdomain: Handle missing vc/vp ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update header ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update header ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsiters ARM: OMAP: DRA7: CM: Add minimal regbit shifts ARM: OMAP: DRA7: CM: Add DRA7XX register defines ARM: OMAP: DRA7: PRM: Add DRA7XX register definitions ARM: DRA7: Add the build support in omap2plus ARM: DRA7: hwmod: Reuse the soc_ops used for OMAP4/5 ARM: DRA7: id: Add cpu detection support for DRA7xx based SoCs' ARM: DRA7: Kconfig: Make ARCH_NR_GPIO default to 512 ARM: DRA7: board-generic: Add basic DT support ARM: DRA7: Resue the clocksource, clockevent support ARM: DRA7: Reuse io tables and add a new .init_early ARM: DRA7: Reuse all of PRCM and MPUSS SMP infra Signed-off-by: Olof Johansson <olof@lixom.net>
| | * \ Merge tag 'for-v3.12/dra7xx' of ↵Tony Lindgren2013-08-2617-5/+5607
| | |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.12/soc This series adds basic TI DRA7xx PRCM and hwmod support. Basic test logs are available here: http://www.pwsan.com/omap/testlogs/dra7xx_prcm_devel_v3.12/20130823050445/ Note that DRA7xx could not be tested locally, since I don't have a board.
| | | * | ARM: OMAP: DRA7: Enable PM framework initializationsAmbresh K2013-08-232-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialise powerdomains, clockdomains, and hwmod frameworks. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: hwmod: Create initial DRA7XX SoC dataAmbresh K2013-08-233-0/+2726
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding the hwmod data for DRA7XX platforms. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: Reuse the omap44xx_restart and fix the device instanceRajendra Nayak2013-08-233-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The omap44xx_restart used on omap4 and omap5 devices can be reused on dra7 devices as well. The device instance however is different across omap5 and dra7 as compared to omap4. So fix this for omap5 as well as dra7. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: powerdomain: Handle missing vc/vpRajendra Nayak2013-08-231-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DRA7 belongs to the omap4plus devices which reuse the omap4_pwrdm_operations ops for powerdomain control. DRA7 however has no VC/VP while all the earlier omap4plus devices did. So use the .pwrdm_has_voltdm() ops to pass this info on to the core. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: powerdomain: Add DRA7XX data and update headerAmbresh K2013-08-233-0/+456
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the data file to describe all power domains inside the DRA7XX SoC. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: clockdomain: Add DRA7XX data and update headerAmbresh K2013-08-233-0/+742
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the data file to describe all clock domains inside the DRA7XX SoC Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: PRCM: Add DRA7XX local MPU PRCM regsitersAmbresh K2013-08-232-0/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the PRCM MPU registers for DRA7XX platforms Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation to comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: CM: Add minimal regbit shiftsRajendra Nayak2013-08-231-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This header contains minimal regbits that are currently used in code. This header has traditionally been autogenerated on OMAP4+ devices but the autogenerated contents are largely (95%) unused and hence to reduce unsued data in the kernel this header has been cut down (from the autogen output) to whatever is currently needed. This is done by running a cleanup script on top of the existing autogen script. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Ambresh K <ambresh@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: CM: Add DRA7XX register definesAmbresh K2013-08-232-0/+837
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the new defines for DRA7XX CM registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | ARM: OMAP: DRA7: PRM: Add DRA7XX register definitionsAmbresh K2013-08-231-0/+678
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the new defines for DRA7xx prm module registers. Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> [paul@pwsan.com: added generation notation in the comments] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | Merge tag 'omap-for-v3.12/prcm-signed' of ↵Olof Johansson2013-08-297-31/+118
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into late/all From Tony Lindgren: OMAP PRCM and hwmod fixes and improvments via Paul Walmsley <paul@pwsan.com>: Various OMAP PRCM & hwmod fixes and improvements. Notable changes include: - a fix for OMAP4 PLL locking to avoid a bootloader dependency that causes nasty log spew on startup - AM33xx DEBUGSS support fixes in hwmod data - OMAP5 mailbox support in hwmod data Basic test logs are here: http://www.pwsan.com/omap/testlogs/prcm_a_for_v3.12/20130823125002/ Note that the 3530 failure is due to the mysterious transient serial issue affecting 3530 for several releases now, which causes a log parsing failure. PM still seems to work. * tag 'omap-for-v3.12/prcm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: OMAP: AM33xx: clock: Add RNG clock data ARM: OMAP: TI81XX: add always-on powerdomain for TI81XX ARM: OMAP4: clock: Lock PLLs in the right sequence ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSS ARM: OMAP2+: Only write the sysconfig on idle when necessary ARM: OMAP5: hwmod data: Add mailbox data Signed-off-by: Olof Johansson <olof@lixom.net>
| | * \ \ Merge tag 'for-v3.12/omap-prcm-hwmod' of ↵Tony Lindgren2013-08-267-31/+118
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v3.12/prcm Various OMAP PRCM & hwmod fixes and improvements. Notable changes include: - a fix for OMAP4 PLL locking to avoid a bootloader dependency that causes nasty log spew on startup - AM33xx DEBUGSS support fixes in hwmod data - OMAP5 mailbox support in hwmod data Basic test logs are here: http://www.pwsan.com/omap/testlogs/prcm_a_for_v3.12/20130823125002/ Note that the 3530 failure is due to the mysterious transient serial issue affecting 3530 for several releases now, which causes a log parsing failure. PM still seems to work.
| | | | \ \
| | | | \ \
| | | *-. \ \ Merge branches 'hwmod_devel_v3.12', 'prcm_devel_v3.12' and ↵Paul Walmsley2013-08-235-30/+73
| | | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | 'am33xx_devel_v3.12' into prcm_a_for_v3.12
| | | | | * | | ARM: OMAP: AM33xx: clock: Add RNG clock dataLokesh Vutla2013-08-231-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock data for RNG module on AM33xx SoC. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | | * | | ARM: OMAP: AM33XX: hwmod: Add hwmod data for debugSSVaibhav Hiremath2013-08-231-22/+47
| | | |_|/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original hwmod data file, DebugSS entry was disabled, since we didn't (and do not) have SW to control it. This patch enables it back with right data, so that it can be controlled by different ways; and the suggested method it to have modular driver for debugSS as well. Refer to the link for more discussion on handling of debugSS - https://patchwork.kernel.org/patch/2212111/ Signed-off-by: Vaibhav Hiremath <hvaibhav@ti.com> Cc: Paul Walmsley <paul@pwsan.com> Cc: Tony Lindgren <tony@atomide.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | * | | ARM: OMAP: TI81XX: add always-on powerdomain for TI81XXAida Mynzhasova2013-08-232-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds alwon powerdomain support for TI81XX, which is required for stable functioning of a big number of TI81XX subsystems. Signed-off-by: Aida Mynzhasova <aida.mynzhasova@skitlab.ru> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | | * | | ARM: OMAP4: clock: Lock PLLs in the right sequenceRajendra Nayak2013-08-231-8/+12
| | | |/ / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On OMAP4 we have clk_set_rate()s being done for a few DPLL clock nodes, as part of the clock init code, since the bootloaders no longer locks these DPLLs. So we have a clk_set_rate() done for a ABE DPLL node (which inturn locks it) followed by a clk_set_rate() for the USB DPLL. With USB DPLL being in bypass, we have this parent->child relationship thats formed while the clocks get registered. dpll_abe_ck | V dpll_abe_x2_ck | V dpll_abe_m3x2_ck | V usb_hs_clk_div_ck | V dpll_usb_ck This is because usb_hs_clk_div_ck is bypass clock for dpll_usb_ck. So with this parent->child relationship in place, a clk_set_rate() on ABE DPLL results eventually in a clk_set_rate() call on USB DPLL, because CCF does a clk_change_rate() (as part of clk_set_rate()) on all downstream clocks resulting from a rate change on the top clock. So its important that we lock USB DPLL before we lock ABE DPLL. Without which we see these error logs at boot. [These error logs will not be seen if using a bootloader that locks USB DPLL] [ 0.000000] clock: dpll_usb_ck failed transition to 'locked' [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] Division by zero in kernel. [ 0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.10.0-03445-gfb2af00-dirty #7 [ 0.000000] [<c001bfe8>] (unwind_backtrace+0x0/0xf4) from [<c001868c>] (show_stack+0x10/0x14) [ 0.000000] [<c001868c>] (show_stack+0x10/0x14) from [<c02deb28>] (Ldiv0+0x8/0x10) [ 0.000000] [<c02deb28>] (Ldiv0+0x8/0x10) from [<c0477030>] (clk_divider_set_rate+0x10/0x114) [ 0.000000] [<c0477030>] (clk_divider_set_rate+0x10/0x114) from [<c0476ef4>] (clk_change_rate+0x38/0xb8) [ 0.000000] [<c0476ef4>] (clk_change_rate+0x38/0xb8) from [<c0476f5c>] (clk_change_rate+0xa0/0xb8) [ 0.000000] clock: trace_clk_div_ck: could not find divisor for target rate 0 for parent pmd_trace_clk_mux_ck [ 0.000000] Division by zero in kernel. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP2+: Only write the sysconfig on idle when necessaryJon Hunter2013-08-231-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, whenever we idle a device _idle_sysc() is called and writes to the devices SYSCONFIG register to set the idle mode. A lot devices are using the smart-idle mode and so the write to the SYSCONFIG register is programming the same value that is already stored in the register. Writes to the devices SYSCONFIG register can be slow, for example, writing to the DMTIMER SYSCONFIG register takes 3 interface clock cycles and 3 functional clock cycles. If the DMTIMER is using the slow 32kHz functional clock this can take ~100us. Furthermore, during boot on an OMAP4430 panda board, I see that there are 100 calls to _idle_sysc(), however, only 3 out of the 100 calls actually write the SYSCONFIG register with a new value. Therefore, to avoid unnecessary writes to device SYSCONFIG registers when idling the device, only write the value if the value has changed. It should be safe to do this on idle as the context of the register will never be lost while the device is active. Verified that suspend, CORE off and retention states are working with this change on OMAP3430 Beagle board. Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| | | * | | ARM: OMAP5: hwmod data: Add mailbox dataSuman Anna2013-08-201-0/+42
| | |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the hwmod data for the mailbox IP in OMAP5 SoC. This is needed to be able to enable the OMAP mailbox support for OMAP5. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | | Merge tag 'highbank-for-3.12' of git://sources.calxeda.com/kernel/linux into ↵Olof Johansson2013-08-296-24/+33
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | late/all From Rob Herring: Updates for Highbank for 3.12: - A couple of fixes to enable LPAE. - pl08x driver fixes to make it build with ARCH_DMA_ADDR_T_64BIT. - Avoid L2 related smc calls on Midway. - Add selecting of necesssary ARM errata. * tag 'highbank-for-3.12' of git://sources.calxeda.com/kernel/linux: ARM: highbank: clean-up some unused includes ARM: highbank: avoid L2 cache smc calls when PL310 is not present ARM: move outer_cache declaration out of ifdef ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAE DMA: fix printk warning in AMBA PL08x DMA driver DMA: fix AMBA PL08x compilation issue with 64bit DMA address type ARM: highbank: select required errata work-arounds ARM: highbank: select ARCH_HAS_HOLES_MEMORYMODEL ARM: highbank: enable DMA zone for LPAE ARM: use phys_addr_t for DMA zone sizes Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | | | ARM: highbank: clean-up some unused includesRob Herring2013-08-271-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: highbank: avoid L2 cache smc calls when PL310 is not presentRob Herring2013-08-221-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While Midway firmware handles L2 smc calls as nops, the custom smc calls present a problem when running virtualized Midway guest. They aren't needed so just avoid calling them. In the process, cleanup the L2X0 ifdefs and use IS_ENABLED instead. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: move outer_cache declaration out of ifdefRob Herring2013-08-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that outer_cache can be used inside IS_ENABLED condition. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk>
| | * | | | ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAERob Herring2013-08-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ECX-2000 has some 64-bit capable DMA and therefore needs dma_addr_t to be a 64-bit size. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | DMA: fix printk warning in AMBA PL08x DMA driverAndre Przywara2013-08-221-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Rob's recent pull request the patch ARM: highbank: select ARCH_DMA_ADDR_T_64BIT for LPAE promotes dma_addr_t to 64bit, so printk generates a warning about an incorrect type. Fix this by casting it to u64 and using %llx. Fixing long lines on the way. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | DMA: fix AMBA PL08x compilation issue with 64bit DMA address typeAndre Przywara2013-08-221-6/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When dma_addr_t is 64 bits long, compilation of the AMBA PL08x DMA driver breaks due to a missing 64bit%8bit modulo operation. Looking more closely the divisor in these operations can only be 1, 2 or 4, so the full featured '%' modulo operation is overkill and can be replaced with simple bit masking. Change from v1: Replace open-coded function with existing IS_ALIGNED macro and use a macro around that to avoid a line becoming too long. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Acked-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: highbank: select required errata work-aroundsRob Herring2013-08-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ensure necessary errata work-arounds are always enabled for Highbank and Midway platforms. Highbank requires 764369 and 764369. Midway requires 798181, but only the first half of the work-around (no IPI). Support for skipping the IPI is introduced in another commit. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: highbank: select ARCH_HAS_HOLES_MEMORYMODELRob Herring2013-08-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Midway, the first 4G of memory starts at 0 and the rest of memory (4GB+) starts at 0x2_00000000, so we need to enable pfn_valid checks by selecting ARCH_HAS_HOLES_MEMORYMODEL. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: highbank: enable DMA zone for LPAERob Herring2013-08-172-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices are restricted to 32-bit DMA. Thus the platform dma_zone_size needs to be set. Otherwise dma-mapping code is complaining, e.g. calxedaxgmac fff50000.ethernet: coherent DMA mask 0xffffffff is smaller than system GFP_DMA mask 0xffffffffffffffff Signed-off-by: Andreas Herrmann <andreas.herrmann@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| | * | | | ARM: use phys_addr_t for DMA zone sizesRob Herring2013-08-132-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to specify a DMA zone size of 4GB on LPAE systems, the sizes need to be 64-bit. So make machine_desc.dma_zone_size and arm_dma_zone_size be phys_addr_t instead of unsigned long. Signed-off-by: Rob Herring <rob.herring@calxeda.com>
| * | | | | Merge tag 'at91-soc' of git://github.com/at91linux/linux-at91 into late/allOlof Johansson2013-08-294-1/+25
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From Nicolas Ferre: AT91 SoC update for 3.12 take 1 - enable kernel uncompress information output for SoC where it was missing: at91sam9n12 and sama5d3 - addition of at91rm9200 to the generic at91_dt_defconfig * tag 'at91-soc' of git://github.com/at91linux/linux-at91: ARM: at91: at91_dt_defconfig: enable rm9200 support ARM: at91: sam9n12: enable kernel uncompress info output ARM: at91: sama5: enable kernel uncompress info output ARM: at91: include sama5d3.h into hardware.h ARM: at91: sama5d3: add definition for usart base address
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