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* ARM: l2c: provide common PL310 early resume codeRussell King2014-05-302-1/+59
| | | | | | | | | Provide a common assembly implementation for PL310 resume code. Certain platforms need to re-initialise the L2C cache early as it may preserve data across a S2RAM cycle, and therefore must be enabled along with the L1 cache and MMU. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add platform independent core L2 cache OF initialisationRussell King2014-05-302-0/+15
| | | | | | | | | Add a hook into the core ARM code to perform L2 cache initialisation in a platform independent manner. Platforms still get to indicate their auxiliary control register values and mask, but the initialisation call will now be made from generic code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: always enable non-secure access to lockdown registersRussell King2014-05-301-2/+21
| | | | | | | | Since we always write to these during the cache initialisation, it is a good idea to always have the non-secure access bit set. Set it in core code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: always enable low power modesRussell King2014-05-301-0/+12
| | | | | | Always enable the L2C low power modes on L2C-310 R3P0 and newer parts. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove platforms/SoCs setting early BRESPRussell King2014-05-3011-20/+19
| | | | | | | | | | | Since we now automatically enable early BRESP in core L2C-310 code when we detect a Cortex-A9, we don't need platforms/SoCs to set this bit explicitly. Instead, they should seek to preserve the value of bit 30 in the auxiliary control register. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add automatic enable of early BRESPRussell King2014-05-301-3/+22
| | | | | | | | | | | | | The AXI bus protocol requires that a write response should only be sent back to the master when the last write has been accepted. Early BRESP allows the L2C-310 to send the write response as soon as the store buffer accepts the write address. Cortex-A9 processors can signal to the L2C-310 that they wish to be notified early, and if this optimisation is enabled, the L2C-310 can signal an early write response. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move L2 cache register saving to a more sensible locationRussell King2014-05-301-12/+22
| | | | | | | | | Move the L2 cache register saving to a more sensible location - after the cache has been enabled, and fixups have been run. We move the saving of the auxiliary control register into the ->save function as well which makes everything operate in a sane and maintainable way. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: check that DT files specify the required "cache-unified" propertyRussell King2014-05-301-0/+4
| | | | | | This is a required property, and should always be specified. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: fix register namingRussell King2014-05-3014-95/+118
| | | | | | | | | | | | | We have a mixture of different devices with different register layouts, but we group all the bits together in an opaque mess. Split them out into those which are L2C-310 specific and ones which refer to earlier devices. Provide full auxiliary control register definitions. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 752271 in core L2C codeRussell King2014-05-301-1/+17
| | | | | | | | Rather than having SoCs work around L2C erratum themselves, move them into core code. This erratum affects the double linefill feature which needs to be disabled for r3p0 to r3p1-50rel0. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic hook to intercept writes to secure registersRussell King2014-05-302-13/+34
| | | | | | | | | | | | | When Linux is running in the non-secure world, any write to a secure L2C register will generate an abort. Platforms normally have to call firmware to work around this. Provide a hook for them to intercept any L2C secure register write. l2c_write_sec() avoids writes to secure registers which are already set to the appropriate value, thus avoiding the overhead of needlessly calling into the secure monitor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move errata configuration options to arch/arm/mm/KconfigRussell King2014-05-302-51/+51
| | | | | | | Move the L2C-310 errata configuration options to arch/arm/mm/Kconfig along side the option which enables support for this device. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move way size calculation data into l2c_init_dataRussell King2014-05-301-9/+20
| | | | | | | Move the way size calculation data (base of way size) out of the switch statement into the provided initialisation data. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add decode for L2C-220 cache waysRussell King2014-05-301-0/+1
| | | | | | | Rather than assuming these are always 8-way, it can be decoded from the auxillary register in the same manner as L2C-210. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move type string into l2c_init_data structureRussell King2014-05-301-7/+13
| | | | | | | | | | Rather than decoding this from the ID register, store it in the l2c_init_data structure. This simplifies things some more, and allows us to better provide further details as to how we're driving the cache. We print the cache ID value anyway should we need to precisely identify the cache hardware. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove obsolete l2x0 ops for non-OF initRussell King2014-05-301-206/+0
| | | | | | | | | | | | | | | | | | | | | | non-OF initialisation has never been used with any cache controller which isn't an ARM cache controller, so we can safely get rid of the old (and buggy) l2x0_*-based operations structure. This is also the last reference to: - l2x0_clean_line() - l2x0_inv_line() - l2x0_flush_line() - l2x0_flush_all() - l2x0_clean_all() - l2x0_inv_all() - l2x0_inv_range() - l2x0_clean_range() - l2x0_flush_range() - l2x0_enable() - l2x0_resume() so kill those functions too. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: convert Broadcom L2C-310 to new codeRussell King2014-05-301-16/+11
| | | | | | | | The Broadcom L2C-310 devices use ARMs L2C-310 R2P3 or later. These require no errata workarounds, and so we can directly call the l2c210 functions from their methods. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add L2C-220 specific handlersRussell King2014-05-301-10/+157
| | | | | | | | | | | | The L2C-220 is different from the L2C-210 and L2C-310 in that every operation is a background operation: this means we have to use spinlocks to protect all operations, and we have to wait for every operation to complete. Should a second operation be attempted while a previous operation is in progress, the response will be an imprecise abort. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: use L2C-210 handlers for L2C-310 errata-less implementationsRussell King2014-05-301-22/+36
| | | | | | | | Where no errata affect the L2C-310 handlers, they are functionally equivalent to L2C-210. Re-use the L2C-210 handlers for the L2C-310 part. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 588369 as a method overrideRussell King2014-05-301-0/+69
| | | | | | | | | Implement L2C-310 erratum 588369 by overriding the invalidate range and flush range methods in the outer_cache operations structure. This allows us to sensibly contain the erratum code in one place without affecting other locations/implemetations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement L2C-310 erratum 727915 as a method overrideRussell King2014-05-301-0/+20
| | | | | | | | | Implement L2C-310 erratum 727915 by overriding the flush_all method in the outer_cache operations structure. This allows us to sensibly contain the erratum code in one place without affecting other locations or implementations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add L2C-210 specific handlersRussell King2014-05-301-1/+122
| | | | | | | | | | | Add L2C-210 specific cache operation handlers. These are tailored to the requirements of the L2C-210 cache controller, which doesn't require any workarounds. We avoid using the way operations during normal operation, which means we can avoid locking: the only time we use the way operations are during initialisation, and when disabling the cache. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move pl310_set_debug() into l2c-310 codeRussell King2014-05-301-8/+6
| | | | | | | Move the pl310_set_debug() into the l2c-310 code area, and don't hide it with ifdefs. Rename it to l2c310_set_debug(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: simplify l2x0 unlocking codeRussell King2014-05-301-17/+8
| | | | | | | The l2x0 unlocking code is only called from l2x0_enable() now, so move the logic entirely into that function and simplify it. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up save/resume functionsRussell King2014-05-301-57/+52
| | | | | | | | | | Rename the pl310 save/resume functions to have a l2c310 prefix - this is it's official name. Use a local cached copy of the l2x0_base virtual address, and also realise that many of the resume function tails are the same as the enable functions, so make a call to the enable function instead of duplicating that code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move and add ARM L2C-2x0/L2C-310 save/resume code to non-OFRussell King2014-05-301-74/+77
| | | | | | | | Add the save/resume code hooks to the non-OF implementations as well. There's no reason for the non-OF implementations to be any different from the OF implementations. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up L2 cache initialisation messagesRussell King2014-05-301-3/+4
| | | | | | Make one of them purely "English", and the other purely technical. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: implement fixups for L2 cache controller quirks/errataRussell King2014-05-301-11/+101
| | | | | | | | | Rather than putting quirk handling in __l2c_init(), move it out to a separate function which individual implementations can specify. This helps to localise the quirks to those implementations which require them. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move aurora broadcast setup to enable functionRussell King2014-05-301-13/+15
| | | | | | | | Rather than having this hacked into the OF initialiation function, we can handle this via the enable function instead. While here, clean up that code and comments a little. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: only write the auxiliary control register if requiredRussell King2014-05-301-1/+3
| | | | | | | | Avoid unnecessary writes to the auxiliary control register if the register already contains the required value. This allows us to avoid invoking the platforms secure monitor code unnecessarily. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: write auxctrl register before unlockingRussell King2014-05-301-5/+5
| | | | | | | | We should write the auxillary control register before unlocking: the write may be necessary to enable non-secure access to the lock registers. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide enable methodRussell King2014-05-301-18/+62
| | | | | | | | Providing an enable method gives L2 cache controllers a chance to do special handling at enable time. This allows us to remove a hack in l2x0_unlock() for Marvell Aurora L2 caches. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: group implementation specific code togetherRussell King2014-05-301-251/+251
| | | | | | | | | | | | | | | | Back in the mists of time, someone decided that it would be a good idea to group like functions together - so all the save functions in one place, all the resume functions in another, all the OF parsing functions some place else. This makes it difficult to get an overview on what a particular implementation is doing - grouping an implementations specific functions together makes more sense, because you can see what it's doing without the clutter of other implementations. Organise it according to implementation. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: move l2c save function to __l2c_init()Russell King2014-05-301-3/+7
| | | | | | | There's no reason this functionality should be specific to DT, so move it into the common initialisation function. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: pass iomem address into data->save functionRussell King2014-05-301-16/+16
| | | | | | | Pass the iomem address into this function so we don't have to keep accessing it from a global. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: clean up OF initialisation a bitRussell King2014-05-301-26/+40
| | | | | | | | | | | | | | | | Rather than having a boolean and other tricks to disable some bits of l2x0_init(), split this function into two parts: a common part shared between OF and non-OF, and the non-OF part. The common part can take a block of function pointers, and the cache ID (to cope with Aurora's DT specified ID.) Eliminate the redundant setting of l2x0_base in the OF case, moving it to the non-OF init function. This allows us to localise the OF-specific initialisation handling from the non-OF handling. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add and use L2C revision constantsRussell King2014-05-302-11/+21
| | | | | | | The revision namespace is specific to the L2 cache part, so don't name these with generic identifiers, use a part specific identifier. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: rename cache_wait_way()Russell King2014-05-301-3/+3
| | | | | | | | | | cache_wait_way() is actually used to wait for a particular mask to report clear; it's not really got much to do with cache ways at all. Indeed, it gets used to wait for the C bit to clear on older caches. Rename this with a more generic function name which better reflects its purpose: l2c_wait_mask(). Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic helper for way-based operationsRussell King2014-05-301-6/+9
| | | | | | | | | Provide a generic helper function for way based operations. These are always background operations, and thus have to be waited for before a new operation is commenced. This helper extracts that requirement from several locations in the code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: split out cache unlock codeRussell King2014-05-301-7/+16
| | | | | | | Split the cache unlock code out of l2x0_unlock(). We want to be able to re-use this functionality later. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: provide generic function for calling set_debug methodRussell King2014-05-301-1/+11
| | | | | | | | Provide a generic function which always calls the set_debug method. This will be used later in the series as some work-arounds require that the debug register be written. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: rename OF specific things, making l2x0_of_data available to allRussell King2014-05-301-32/+32
| | | | | | | | | Rename a few things to help distinguish their function(s): l2x0_of_data -> l2c_init_data setup -> of_parse add of_ prefix to OF specific data Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: tidy up l2x0_of_data declarationsRussell King2014-05-301-16/+14
| | | | | | | Remove NULL initialisers, make these all __initconst structures, and order their members in the same order as the structure declaration. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: add helper for L2 cache controller DT IDsRussell King2014-05-301-13/+10
| | | | | | Make it easier to declare L2 cache controller DT IDs by using a macro. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: outer cache: add WARN_ON() to outer_disable()Russell King2014-05-303-5/+22
| | | | | | | Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: outer cache: add documentation of outer cache functionsRussell King2014-05-221-1/+47
| | | | | | | | | Add some documentation to cover the outer cache functions so that their requirements can be better understood. Of particular note are the flush_all() and disable() methods which must not be called except in very specific circumstances. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove unnecessary UL-suffix to mask valuesRussell King2014-05-227-7/+7
| | | | | | | | They're u32, they're not unsigned long. The UL suffix is not required here. Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: omap2: remove ES1.0 supportRussell King2014-05-221-17/+8
| | | | | | | | | | | Santosh says: > But we should kill all of that since we long back decided to remove > ES1.0 related code. The mach-omap code alreasy has removed the ES1.0 > compatibility so feel free to remove any specific ES1.0 > related stuff. That silicon is long dead. Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: avoid calling outer_flush_all() unnecessarily (Spear)Russell King2014-05-221-5/+14
| | | | | | | | | Spear calls outer_flush_all() from it's SMP bringup function. This is potentially dangerous as the L2C set/way operations which implement this don't take kindly to concurrent operations. Besides, there's better solutions to this, as implemented on other platforms. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* ARM: l2c: remove unnecessary call to outer_flush_all()Russell King2014-05-221-1/+0
| | | | | | | | | | outer_disable() is defined to safely turn the L2 cache off without data loss: this means that outer_flush_all() should never be called unless you need to implement some special L2 cache disabling, and even then only from your replacement L2 cache disable function. Acked-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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