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* sh64: update for IRQ flag handling naming changes.Paul Mundt2010-10-271-8/+8
| | | | | | | irq_32.c was updated for the new API, while irq_64.c was overlooked. This syncs them up and gets things building again. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* rtc: rtc-rs5c313: ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-10-271-17/+17
| | | | | | | The ctrl_xxx routines are deprecated, switch over to the __raw_xxx versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-se: irq_data conversion.Paul Mundt2010-10-274-31/+32
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* input: hp680_ts_input: ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-10-271-8/+8
| | | | | | | The ctrl_xxx routines are deprecated, switch over to the __raw_xxx versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* input: jornada680_kbd: ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-10-271-14/+14
| | | | | | | The ctrl_xxx routines are deprecated, switch over to the __raw_xxx versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: hd64461: irq_data conversion.Paul Mundt2010-10-271-8/+11
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-x3proto: irq_data conversion.Paul Mundt2010-10-271-3/+4
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-systemh: irq_data conversion.Paul Mundt2010-10-271-36/+21
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: imask IRQs irq_data conversion.Paul Mundt2010-10-271-5/+9
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-microdev: irq_data conversion.Paul Mundt2010-10-271-19/+11
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-landisk: irq_data conversion.Paul Mundt2010-10-271-8/+7
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: IPR IRQs irq_data conversion.Paul Mundt2010-10-271-13/+12
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: mach-dreamcast: irq_data conversion.Paul Mundt2010-10-271-7/+10
| | | | Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: maple: ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-10-271-10/+10
| | | | | | | The ctrl_xxx routines are deprecated, switch over to the __raw_xxx versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* cdrom: gdrom: ctrl_in/outX to __raw_read/writeX conversion.Paul Mundt2010-10-271-38/+38
| | | | | | | The ctrl_xxx routines are deprecated, switch over to the __raw_xxx versions. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Fix the sparsemem disabled build.Paul Mundt2010-10-271-0/+1
| | | | | | | | The introduction of MAX_PHYSMEM_BITS in to the initial cpuinfo struct causes a build error when sparsemem is disabled and asm/sparsemem.h is not brought in by other means. Include it explicitly. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Switch dynamic IRQ creation to generic irq allocator.Paul Mundt2010-10-264-84/+9
| | | | | | | | | | | Now that the genirq code provides an IRQ bitmap of its own and the necessary API to manipulate it, there's no need to keep our own version around anymore. In the process we kill off some unused IRQ reservation code, with future users now having to tie in to the genirq API as normal. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Tidy up genirq Kconfig bits.Paul Mundt2010-10-261-10/+3
| | | | | | Now that there's a HAVE_GENERIC_HARDIRQS, switch over. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Sanitize sparse irqThomas Gleixner2010-10-263-22/+17
| | | | | | | Switch over to the new allocator functions. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* sh: Expose physical addressing mode through cpuinfo.Paul Mundt2010-10-263-0/+6
| | | | | | | | | | | CPUs can be in either the legacy 29-bit or 32-bit physical addressing modes. This follows the x86 approach of tracking the phys bits in cpuinfo and exposing it to userspace through procfs. This change was requested to permit kexec-tools to detect the physical addressing mode in order to determine the appropriate address mangling. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
* Merge branch 'for-next' of git://android.git.kernel.org/kernel/tegraLinus Torvalds2010-10-2535-629/+4917
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'for-next' of git://android.git.kernel.org/kernel/tegra: spi: tegra: fix error setting on timeout spi: add spi_tegra driver tegra: harmony: enable PCI Express tegra: add PCI Express support tegra: add PCI Express clocks [ARM] tegra: Add APB DMA support [ARM] tegra: Add cpufreq support [ARM] tegra: common: Update common clock init table [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanups [ARM] tegra: Add support for reading fuses [ARM] tegra: gpio: Add suspend and wake support [ARM] tegra: pinmux: add safe values, move tegra2, add suspend [ARM] tegra: add suspend and mirror irqs to legacy controller [ARM] tegra: Add legacy irq support [ARM] tegra: update iomap
| * spi: tegra: fix error setting on timeoutErik Gilling2010-10-251-4/+4
| | | | | | | | | | | | | | avoids derefencing an uninitialized pointer Change-Id: Icf528441ae481e9f6f5ddc0be32c7c217fa49701 Signed-off-by: Erik Gilling <konkers@android.com>
| * spi: add spi_tegra driverErik Gilling2010-10-213-0/+626
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | v2 changes: from Thierry Reding: * add "select TEGRA_SYSTEM_DMA" to Kconfig from Grant Likely: * add oneline description to header * inline references to DRIVER_NAME * inline references to BUSY_TIMEOUT * open coded bytes_per_word() * spi_readl/writel -> spi_tegra_readl/writel * move transfer validation to spi_tegra_transfer * don't request_mem_region iomem as platform bus does that for us * __exit -> __devexit v3 changes: from Russell King: * put request_mem_region back int from Grant Likely: * remove #undef DEBUG * add SLINK_ to register bit defines * remove unused bytes_per_word * make spi_tegra_readl/writel static linine * various refactoring for clarity * mark err if BSY bit is not cleared after 1000 retries * move spinlock to protect setting of RDY bit * subsys_initcall -> module_init v3 changes: from Grant Likely: * update spi_tegra to use PTR_ERRless dma API v4 changes: from Grant Likely: * remove empty spi_tegra_cleanup fucntion * allow device ids of -1 Signed-off-by: Erik Gilling <konkers@android.com> Acked-by: Grant Likely <grant.likely@secretlab.ca> Cc: Thierry Reding <thierry.reding@avionic-design.de> Cc: Russell King <linux@arm.linux.org.uk> spi: tegra: cleanups from upstream review Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25 Signed-off-by: Erik Gilling <konkers@android.com>
| * tegra: harmony: enable PCI ExpressMike Rapoport2010-10-212-0/+58
| | | | | | | | | | | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> CC: Olof Johansson <olof@lixom.net> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * tegra: add PCI Express supportMike Rapoport2010-10-216-1/+936
| | | | | | | | | | | | | | | | | | Change-Id: Ibd0bcd46895eb88952b9db29e1f68572d39aae01 Signed-off-by: Mike Rapoport <mike@compulab.co.il> Acked-by: Arnd Bergmann <arnd@arndb.de> CC: Russell King <linux@arm.linux.org.uk> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * tegra: add PCI Express clocksMike Rapoport2010-10-211-0/+48
| | | | | | | | | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> CC: Gary King <GKing@nvidia.com> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add APB DMA supportColin Cross2010-10-215-0/+922
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APB DMA block handles DMA transfers to and from some peripherals in the Tegra SOC. It reads from sequential addresses on the memory bus, and writes repeatedly to the same address on the APB bus. Two transfer modes are supported, oneshot for transferring a known size to or from a peripheral, and continuous for streaming data. In continuous mode, a callback occurs when the buffer is half full to allow the existing data to be handled and a new request queued.x v2 changes: dma API no longer uses PTR_ERR Signed-off-by: Erik Gilling <konkers@android.com> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add cpufreq supportColin Cross2010-10-213-0/+187
| | | | | | | | | | | | | | | | | | Implement cpufreq support for the Tegra SOC. DVFS is handled by the core virtual cpu clock. The frequencies of the two cores are tied together, the highest frequency requested by either core determines the actual frequency. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: common: Update common clock init tableColin Cross2010-10-211-2/+2
| | | | | | | | | | | | Renames clocks in the clock init table to match the datasheet names Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: clock: Add dvfs support, bug fixes, and cleanupsColin Cross2010-10-217-210/+1005
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add drivers to clock lookup table - Add new pll_m entries - Support I2C U16 divider - Fix rate reporting on 32.768kHz clock - Call propagate rate only if set_rate succeeds - Add support for audio_sync clock - Add 24MHz to PLLA frequency list - Correct i2s1/2/spdifout mux - Add suspend support - Fix enable/disable parent clocks in set_parent - Add max_rate parameter to all clocks - DVFS support - Add virtual cpu clock with dvfs - Support clk_round_rate - Fix requesting very high periph frequencies - Add quirks for PLLU: PLLU is slightly different from the rest of the PLLs. The lock enable bit is at bit 22 instead of 18 in the MISC register, and the post divider field is a single bit with reversed values from other PLLs. - Simplify recalculating clock rates - Fix UART divider flags - Remove unused clock ops Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: Add support for reading fusesColin Cross2010-10-214-0/+111
| | | | | | | | | | | | | | | | The Tegra SOC contains fuses to identify the CPU type and bin, and a unique id. The CPU info is required to determine the correct voltages for each cpu and core frequency. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: gpio: Add suspend and wake supportColin Cross2010-10-212-13/+95
| | | | | | | | | | | | | | Includes checkpatch fixes and TEGRA_NR_GPIOS changes from Mike Rapoport <mike@compulab.co.il> Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: pinmux: add safe values, move tegra2, add suspendColin Cross2010-10-215-396/+603
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - the reset values for some pin groups in the tegra pin mux can result in functional errors due to conflicting with actively-configured pin groups muxing from the same controller. this change adds a known safe, non- conflicting mux for every pin group, which can be used on platforms where the pin group is not routed to any peripheral - also add each pin group's I/O voltage rail, to enable platform code to map from the pin groups used by each interface to the regulators used for dynamic voltage control - add routines to individually configure the tristate, pin mux and pull- ups for a pingroup_config array, so that it is possible to program individual values at run-time without modifying other values. this allows driver power-management code to reprogram individual interfaces into lower power states during idle / suspend, or to reprogram the pin mux to support multiple physical busses per internal controller (e.g., sharing a single I2C or SPI controller across multiple pin groups) - move chip-specific data like pingroups and drive-pingroups out of the common code and into chip-specific code - fix debug output for group with no pullups - add a TEGRA_MUX_SAFE function. Setting a pingroup to TEGRA_MUX_SAFE will automatically select a mux setting that is guaranteed not to conflict with any of the hardware blocks. Signed-off-by: Gary King <gking@nvidia.com>
| * [ARM] tegra: add suspend and mirror irqs to legacy controllerGary King2010-10-212-0/+139
| | | | | | | | | | | | | | | | | | | | mirror IRQ enable and disable operations on the legacy PPI system interrupt controller, since the legacy controller is responsible for responding to wakeup interrupts when the CPU is in LP2 idle mode save the irq controller state on suspend and restore on resume Signed-off-by: Gary King <gking@nvidia.com>
| * [ARM] tegra: Add legacy irq supportColin Cross2010-10-213-1/+146
| | | | | | | | | | | | | | | | The "legacy irq controller" duplicates the functionality of the GIC, but remains powered during the cpu suspend and idle modes that power down the CPU and the GIC. Signed-off-by: Colin Cross <ccross@android.com>
| * [ARM] tegra: update iomapColin Cross2010-10-213-6/+39
| | | | | | | | | | | | | | | | Add missing io address map entries from datasheet. Add the IRAM area to the statically mapped io regions. Correct the onewire, USB, and statmon addresses Signed-off-by: Colin Cross <ccross@android.com>
* | Merge branch 'for-linus' of ↵Linus Torvalds2010-10-2549-216/+513
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/vapier/blackfin: Blackfin: fix inverted anomaly 05000481 logic Blackfin: drop unused irq_panic()/DEBUG_ICACHE_CHECK Blackfin: ppi/spi/twi headers: add missing __BFP undef Blackfin: update defconfigs Blackfin: bfin_twi.h: start a common TWI header netdev: bfin_mac: push settings to platform resources
| * | Blackfin: fix inverted anomaly 05000481 logicMike Frysinger2010-10-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | No one uses these MMRs so we didn't notice when the anomaly handling logic was inverted. Reported-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: drop unused irq_panic()/DEBUG_ICACHE_CHECKMike Frysinger2010-10-253-118/+0
| | | | | | | | | | | | | | | | | | | | | | | | This code was useful during early port development when our icache code wasn't solid, but that ship has sailed long ago, and no code calls this function anymore (irq_panic). So punt it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: ppi/spi/twi headers: add missing __BFP undefMike Frysinger2010-10-253-0/+6
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: update defconfigsMike Frysinger2010-10-2526-26/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - enable pm for ADI boards - drop security option as no one uses it - enable uninitialized mmap for everyone - disable wireless by default as no one uses it - disable cfq io sched as noop is fine Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: bfin_twi.h: start a common TWI headerMike Frysinger2010-10-251-0/+43
| | | | | | | | | | | | | | | | | | Start one place for TWI definitions. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | netdev: bfin_mac: push settings to platform resourcesSonic Zhang2010-10-2516-71/+421
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move all the pin settings out of the Kconfig and into the platform resources (MII vs RMII). This clean up also lets us push out the phy settings so that board porters may control the layout. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Acked-by: David S. Miller <davem@davemloft.net> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblazeLinus Torvalds2010-10-2556-201/+1038
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next' of git://git.monstr.eu/linux-2.6-microblaze: (42 commits) microblaze: Fix build with make 3.82 fbdev/xilinxfb: Microblaze driver support microblaze: Support C optimized lib functions for little-endian microblaze: Separate library optimized functions microblaze: Support timer on AXI lite microblaze: Add support for little-endian Microblaze microblaze: KGDB little endian support microblaze: Add PVR for endians plus detection net: emaclite: Add support for little-endian platforms microblaze: trivial: Add comment for AXI pvr microblaze: pci-common cleanup microblaze: Support early console on uart16550 microblaze: Do not compile early console support for uartlite if is disabled microblaze: Setup early console dynamically microblaze: Rename all uartlite early printk functions microblaze: remove early printk uarlite console dependency from header microblaze: Remove additional compatible properties microblaze: Remove hardcoded asm instraction for PVR loading microblaze: Use static const char * const where possible microblaze: Define VMALLOC_START/END ...
| * | | microblaze: Fix build with make 3.82Thomas Backlund2010-10-221-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running make headers_install_all on x86_64 and make 3.82 I hit this: arch/microblaze/Makefile:80: *** mixed implicit and normal rules. Stop. make: *** [headers_install_all] Error 2 So split the rules to satisfy make 3.82. Signed-off-by: Thomas Backlund <tmb@mandriva.org> Cc: Stable <stable@kernel.org> Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | fbdev/xilinxfb: Microblaze driver supportMichal Simek2010-10-211-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DCR bus is natively used for PowerPC. Microblaze has no infrastructure for compile DCR that's why is necessary to exclude it. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Grant Likely <grant.likely@secretlab.ca> CC: Andrei Konovalov <akonovalov@ru.mvista.com> CC: "David S. Miller" <davem@davemloft.net> CC: linux-kernel@vger.kernel.org
| * | | microblaze: Support C optimized lib functions for little-endianMichal Simek2010-10-212-6/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimized C library functions can rapidly speedup the kernel. memset doesn't need to be optimized because there is no difference in behavior on little/big endian cpu. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Separate library optimized functionsMichal Simek2010-10-213-15/+46
| | | | | | | | | | | | | | | | | | | | | | | | memcpy/memmove/memset Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Support timer on AXI liteMichal Simek2010-10-212-6/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | New microblaze systems uses two buses. One for memories and flashes and the second for low-speed peripherals which can run on different CLK. This is the reason why the kernel is trying to read clock-frequency directly from node. If there is then the kernel will work with it. If not then cpu CLK is used. Signed-off-by: Michal Simek <monstr@monstr.eu>
| * | | microblaze: Add support for little-endian MicroblazeMichal Simek2010-10-2110-18/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Microblaze little-endian toolchain exports __MICROBLAZEEL__ which is used in the kernel to identify little/big endian. The most of the changes are in loading values from DTB which is always big endian. Little endian platforms are based on new AXI bus which has impact to early uartlite initialization. Signed-off-by: Michal Simek <monstr@monstr.eu>
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