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* ARM: OMAP2+: devices: Fixes for McPDMPeter Ujfalusi2011-11-041-14/+3
| | | | | | | | | | | | | | | | | Commit f718e2c034bf6ff872106344935006230764cb12 (ARM: OMAP2+: devices: Remove all omap_device_pm_latency structures) removed these structures. Commit 3528c58eb9e818b7821501afa2916eb12131994a (OMAP: omap_device: when building return platform_device instead of omap_device) now returns platform_device instead of omap_device. Fix up the omap-mcpdm init function since this part comes via sound tree, and there has been changes regarding to hwmod/omap_device_build. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> CC: Benoit Cousson <b-cousson@ti.com> CC: Kevin Hilman <khilman@ti.com> [tony@atomide.com: updated comments] Signed-off-by: Tony Lindgren <tony@atomide.com>
* ARM: OMAP: Fix errors and warnings when building for one boardSanjeev Premi2011-11-042-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When customizing omap2plus_defconfig to build for only one board (omap3evm), I came across these warnings and errors (filenames truncated): arch/arm/mach-omap2/board-generic.c:76:20: warning: 'omap4_init' defined but not used arch/arm/mach-omap2/built-in.o: In function `omap2420_init_early': arch/arm/mach-omap2/io.c:364: undefined reference to `omap2_set_globals_242x' arch/arm/mach-omap2/io.c:366: undefined reference to `omap2xxx_voltagedomains_init' arch/arm/mach-omap2/io.c:367: undefined reference to `omap242x_powerdomains_init' arch/arm/mach-omap2/io.c:368: undefined reference to `omap242x_clockdomains_init' arch/arm/mach-omap2/io.c:369: undefined reference to `omap2420_hwmod_init' arch/arm/mach-omap2/built-in.o: In function `omap2430_init_early': arch/arm/mach-omap2/io.c:376: undefined reference to `omap2_set_globals_243x' arch/arm/mach-omap2/io.c:378: undefined reference to `omap2xxx_voltagedomains_init' arch/arm/mach-omap2/io.c:379: undefined reference to `omap243x_powerdomains_init' arch/arm/mach-omap2/io.c:380: undefined reference to `omap243x_clockdomains_init' arch/arm/mach-omap2/io.c:381: undefined reference to `omap2430_hwmod_init' arch/arm/mach-omap2/built-in.o: In function `omap4430_init_early': arch/arm/mach-omap2/io.c:436: undefined reference to `omap2_set_globals_443x' arch/arm/mach-omap2/io.c:438: undefined reference to `omap44xx_voltagedomains_init' arch/arm/mach-omap2/io.c:439: undefined reference to `omap44xx_powerdomains_init' arch/arm/mach-omap2/io.c:440: undefined reference to `omap44xx_clockdomains_init' arch/arm/mach-omap2/io.c:441: undefined reference to `omap44xx_hwmod_init' This patch fixes them. Signed-off-by: Sanjeev Premi <premi@ti.com> Acked-by: Thomas Weber <weber@corscience.de> [tony@atomide.com: updated to fix warnings for board-generic.c] Signed-off-by: Tony Lindgren <tony@atomide.com>
* Merge branch 'for_3.2/pm-cleanup-2' of ↵Tony Lindgren2011-11-043-39/+53
|\ | | | | | | git://github.com/khilman/linux-omap-pm into fixes
| * ARM: OMAP3: PM: restrict erratum i443 handling to OMAP3430 onlyPaul Walmsley2011-10-071-9/+11
| | | | | | | | | | | | | | | | | | | | | | Based on the documents that I have here, there doesn't appear to be an equivalent to erratum i443 for OMAP3630, so restrict this one to OMAP34xx chips. Also, explicitly restrict this erratum to EMU and HS devices. Signed-off-by: Paul Walmsley <paul@pwsan.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP3: PM: fix I/O wakeup and I/O chain clock control detectionPaul Walmsley2011-10-073-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way that we detect which OMAP3 chips support I/O wakeup and software I/O chain clock control is broken. Currently, I/O wakeup is marked as present for all OMAP3 SoCs other than the AM3505/3517. The TI81xx family of SoCs are at present considered to be OMAP3 SoCs, but don't support I/O wakeup. To resolve this, convert the existing blacklist approach to an explicit, whitelist support, in which only SoCs which are known to support I/O wakeup are listed. (At present, this only includes OMAP34xx, OMAP3503, OMAP3515, OMAP3525, OMAP3530, and OMAP36xx.) Also, the current code incorrectly detects the presence of a software-controllable I/O chain clock on several chips that don't support it. This results in writes to reserved bitfields, unnecessary delays, and console messages on kernels running on those chips: http://www.spinics.net/lists/linux-omap/msg58735.html Convert this test to a feature test with a chip-by-chip whitelist. Thanks to Dave Hylands <dhylands@gmail.com> for reporting this problem and doing some testing to help isolate the cause. Thanks to Steve Sakoman <sakoman@gmail.com> for catching a bug in the first version of this patch. Thanks to Russell King <linux@arm.linux.org.uk> for comments. Signed-off-by: Paul Walmsley <paul@pwsan.com> Cc: Dave Hylands <dhylands@gmail.com> Cc: Steve Sakoman <sakoman@gmail.com> Tested-by: Steve Sakoman <sakoman@gmail.com> Cc: Russell King - ARM Linux <linux@arm.linux.org.uk> Signed-off-by: Kevin Hilman <khilman@ti.com>
| * ARM: OMAP3: PM: fix pwrdm_post_transition call sequenceCharulatha V2011-10-071-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The context lost count is modified in omap_sram_idle() path when pwrdm_post_transition() is called. But pwrdm_post_transition() is called only after omap_gpio_resume_after_idle() is called. Correct this so that context lost count is modified before calling omap_gpio_resume_after_idle(). This would be useful when OMAP GPIO save/restore context is called by the OMAP GPIO driver itself. Signed-off-by: Charulatha V <charu@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* | Merge branch 'prcm_scm_misc_fixes_3.2' of git://git.pwsan.com/linux-2.6 into ↵Tony Lindgren2011-11-042-9/+12
|\ \ | | | | | | | | | fixes
| * | ARM: OMAP: AM35x: remove hwmods that aren't genericAbhilash K V2011-10-071-5/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Removing modules iva, sr1_hwmod, sr2_hwmod, mailbox from the base omap3xxx_hwmods list, so that they can be excluded for am35x. This removes quite a few warnings on boot for AM35x. Signed-off-by: Abhilash K V <abhilash.kv@ti.com> [paul@pwsan.com: dropped 'mailbox class' comments; updated changelog] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fieldsArchit Taneja2011-10-071-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The OMAP4430 Public TRM vV has these fields mentioned correctly. Signed-off-by: Archit Taneja <archit@ti.com> Acked-by: Benoit Cousson <b-cousson@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | Merge branch 'omap_clock_fixes_3.2' of git://git.pwsan.com/linux-2.6 into fixesTony Lindgren2011-11-046-28/+142
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| * | | ARM: OMAP3+: Update DPLL Fint range for OMAP36xx and OMAP4xxx devicesJon Hunter2011-10-071-16/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The OMAP36xx and OMAP4xxx DPLLs have a different internal reference clock frequency (fint) operating range than OMAP3430. Update the dpll_test_fint() function to check for the correct frequency ranges for OMAP36xx and OMAP4xxx. For OMAP36xx and OMAP4xxx devices, DPLLs fint range is 0.5MHz to 2.5MHz for j-type DPLLs and otherwise it is 32KHz to 52MHz for all other DPLLs. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP4: clock: Add missing clock divider for OCP_ABE_ICLKJon Hunter2011-10-071-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The parent clock of the OCP_ABE_ICLK is the AESS_FCLK and the parent clock of the AESS_FCLK is the ABE_FCLK... ABE_FCLK --> AESS_FCLK --> OCP_ABE_ICLK The AESS_FCLK and OCP_ABE_ICLK clocks both have dividers which determine their operational frequency. However, the dividers for the AESS_FCLK and OCP_ABE_ICLK are controlled via a single bit, which is the CM1_ABE_AESS_CLKCTRL[24] bit. When this bit is set to 0, the AESS_FCLK divider is 1 and the OCP_ABE_ICLK divider is 2. Similarly, when this bit is set to 1, the AESS_FCLK divider is 2 and the OCP_ABE_ICLK is 1. The above relationship between the AESS_FCLK and OCP_ABE_ICLK dividers ensure that the OCP_ABE_ICLK clock is always half the frequency of the ABE_CLK... OCP_ABE_ICLK = ABE_FCLK/2 The divider for the OCP_ABE_ICLK is currently missing so add a divider that will ensure the OCP_ABE_ICLK frequency is always half the ABE_FCLK frequency. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP4460: Clock: Adding support for 4460 specific clocksPaul Walmsley2011-10-071-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4460 specific clocks are not getting added as the cpu_is_omap44xx is choosing only OMAP4430 specific clock nodes. Changing it to add to OMAP4460 specific clocks also. This is clocks are required of temperature sensor. Signed-off-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com> Cc: paul@pwsan.com [paul@pwsan.com: updated to apply] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP3+: dpll: use DPLLs recalc function instead of omap2_get_dpll_rateJon Hunter2011-10-071-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a continuation of Mike Turquette's patch "OMAP3+: use DPLL's round_rate when setting rate". omap3_noncore_dpll_set_rate() and omap3_noncore_dpll_enable() call omap2_get_dpll_rate() explicitly. It may be necessary for some DPLLs to use a different function and so use the DPLLs recalc() function pointer instead. An example is the DPLL_ABE on OMAP4 which can have a 4X multiplier in addition to the usual MN multipler and dividers and therefore uses a different round_rate and recalc function. Signed-off-by: Jon Hunter <jon-hunter@ti.com> Cc: Mike Turquette <mturquette@ti.com> Cc: Misael Lopez Cruz <misael.lopez@ti.com> [paul@pwsan.com: merged this patch with Mike's "use clock's recalc in DPLL handling" patch; also reported by Misael] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP3+: dpll: assign clk rate from rounded rate during rate setMike Turquette2011-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rounded rate can differ from target rate, so to better reflect reality set clk->rate equal to the rounded rate when setting DPLL frequency. This avoids issues where the DPLL frequency is slightly different than what debugfs clock tree reports using the old target rate. An example of a clock that requires this is DPLL_ABE on OMAP4 which can have a 4x multiplier on top of the usual MN dividers depending on register settings. This requires a special round_rate function that might yield a rate different from the initial target. Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP3+: dpll: use DPLL's round_rate when setting rateMike Turquette2011-10-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap3_noncore_dpll_set_rate uses omap2_dpll_round_rate explicitly. Instead use the struct clk pointer's round_rate function to allow for DPLL's with special needs. An example of a clock that requires this is DPLL_ABE on OMAP4 which can have a 4x multiplier on top of the usual MN dividers depending on register settings. This requires a special round_rate function that might yield a rate different from the initial target. Signed-off-by: Mike Turquette <mturquette@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: split rate assignment portion into a separate patch] Signed-off-by: Paul Walmsley <paul@pwsan.com>
| * | | ARM: OMAP4: clock: round_rate and recalc functions for DPLL_ABEMike Turquette2011-10-074-2/+80
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | OMAP4 DPLL_ABE can enable a 4X multipler on top of the normal MN multipler and divider. This is achieved by setting CM_CLKMODE_DPLL_ABE.DPLL_REGM4XEN bit in CKGEN module of CM1. From the OMAP4 TRM: Fdpll = Fref x 2 x (4 x M/(N+1)) in case REGM4XEN bit field is set (only applicable to DPLL_ABE). Add new round_rate() and recalc() functions for OMAP4, that check the setting of REGM4XEN bit and handle this appropriately. The new functions are a simple wrapper on top of the existing omap2_dpll_round_rate() and omap2_dpll_get_rate() functions to handle the REGM4XEN bit. The REGM4XEN bit is only implemented for the ABE DPLL on OMAP4 and so only dpll_abe_ck uses omap4_dpll_regm4xen_round_rate() and omap4_dpll_regm4xen_recalc() functions. Signed-off-by: Mike Turquette <mturquette@ti.com> Tested-by: Jon Hunter <jon-hunter@ti.com> Signed-off-by: Jon Hunter <jon-hunter@ti.com> [paul@pwsan.com: fixed attempt to return a negative from a fn returning unsigned; pass along errors from omap2_dpll_round_rate(); added documentation; added Jon's S-o-b] Signed-off-by: Paul Walmsley <paul@pwsan.com>
* | | Merge branch 'next/soc' of git://git.linaro.org/people/arnd/arm-socLinus Torvalds2011-11-0181-14/+5778
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'next/soc' of git://git.linaro.org/people/arnd/arm-soc: (21 commits) MAINTAINERS: add ARM/FREESCALE IMX6 entry arm/imx: merge i.MX3 and i.MX6 arm/imx6q: add suspend/resume support arm/imx6q: add device tree machine support arm/imx6q: add smp and cpu hotplug support arm/imx6q: add core drivers clock, gpc, mmdc and src arm/imx: add gic_handle_irq function arm/imx6q: add core definitions and low-level debug uart arm/imx6q: add device tree source ARM: highbank: add suspend support ARM: highbank: Add cpu hotplug support ARM: highbank: add SMP support MAINTAINERS: add Calxeda Highbank ARM platform ARM: add Highbank core platform support ARM: highbank: add devicetree source ARM: l2x0: add empty l2x0_of_init picoxcell: add a definition of VMALLOC_END picoxcell: remove custom ioremap implementation picoxcell: add the DTS for the PC7302 board picoxcell: add the DTS for pc3x2 and pc3x3 devices ... Fix up trivial conflicts in arch/arm/Kconfig, and some more header file conflicts in arch/arm/mach-omap2/board-generic.c (as per an ealier merge by Arnd).
| * \ \ Merge branch 'imx/imx6q' into next/socArnd Bergmann2011-11-0234-80/+3662
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: Documentation/devicetree/bindings/arm/fsl.txt arch/arm/Kconfig arch/arm/Kconfig.debug arch/arm/plat-mxc/include/mach/common.h
| | * | | MAINTAINERS: add ARM/FREESCALE IMX6 entryShawn Guo2011-10-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds maintainer for ARM/FREESCALE IMX6. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx: merge i.MX3 and i.MX6Sascha Hauer2011-10-314-19/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch merges the build of imx3 and imx6. The Kconfig symbol ARCH_IMX_V6_V7 is introduced to replace ARCH_MX3 and ARCH_MX6. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add suspend/resume supportShawn Guo2011-10-314-1/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds suspend/resume support for imx6q. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add device tree machine supportShawn Guo2011-10-314-2/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds generic device tree based machine support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add smp and cpu hotplug supportShawn Guo2011-10-317-0/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds smp and cpu hotplug support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add core drivers clock, gpc, mmdc and srcShawn Guo2011-10-316-0/+2263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds a number of core drivers support for imx6q, including clock, General Power Controller (gpc), Multi Mode DDR Controller(mmdc) and System Reset Controller (src). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx: add gic_handle_irq functionShawn Guo2011-10-314-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a plain translation of assembly gic irq handler to C function for CONFIG_MULTI_IRQ_HANDLER support on imx family. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add core definitions and low-level debug uartShawn Guo2011-10-3112-3/+118
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds the core definitions and low-level debug uart support for imx6q. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | arm/imx6q: add device tree sourceShawn Guo2011-10-313-0/+643
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It adds device tree source and documentation for imx6q platform. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | Merge branch 'cross-platform/debug_ll' into imx/imx6qArnd Bergmann2011-10-315-69/+122
| | |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig.debug
| | * \ \ \ Merge branch 'imx/devel' into imx/imx6qArnd Bergmann2011-10-31137-5256/+4008
| | |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/plat-mxc/include/mach/memory.h
| | * \ \ \ \ Merge branch 'dt/gic' into imx/imx6qArnd Bergmann2011-10-31157-1513/+1177
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| | * \ \ \ \ \ Merge branch 'depends/rmk/devel-stable' into imx/imx6qArnd Bergmann2011-10-31406-1550/+7175
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| | * \ \ \ \ \ \ Merge branch 'depends/rmk/smp' into tmpArnd Bergmann2011-10-2016-13/+298
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| | * \ \ \ \ \ \ \ Merge branch 'depends/rmk/debug' into tmpArnd Bergmann2011-10-201-30/+59
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| * | | | | | | | | Merge branch 'picoxcell/soc' into next/socArnd Bergmann2011-11-0226-0/+1341
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| | * | | | | | | | | picoxcell: add a definition of VMALLOC_ENDJamie Iles2011-10-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nicolas Pitre's vmalloc cleanup series didn't get merged in this cycle so picoxcell is missing a VMALLOC_END definition. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| | * | | | | | | | | picoxcell: remove custom ioremap implementationJamie Iles2011-09-263-49/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nicolas Pitre's generic ioremap() patch set means that we don't need this any more. Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| | * | | | | | | | | picoxcell: add the DTS for the PC7302 boardJamie Iles2011-09-262-0/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PC7302 board can be populated with either a PC3X2 or PC3X3 device. Add DTS files for both variants of the PC7302. v3: - remove bootargs from dts files Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| | * | | | | | | | | picoxcell: add the DTS for pc3x2 and pc3x3 devicesJamie Iles2011-09-262-0/+614
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This describes the basic hierarchy of picoxcell pc3x3 devices including clocks and bus interconnect. Some onchip devices are currently omitted as there haven't been bindings created for them. v2: - change timer compatible strings to be more soc specific - split vic node into 2 devices Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| | * | | | | | | | | picoxcell: support for Picochip picoxcell devicesJamie Iles2011-09-2622-0/+584
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | picoXcell is a family of femtocell devices with an ARM application processor and picoArray DSP processor array. This patch adds support for picoXcell boards to be booted using the device tree registering the VIC's, UART's and timers. v3: - fixup vic compatible string in binding v2: - cleanup empty mach headers - convert to of_platform_populate() - simplify uncompress.h - split vic node into 2 devices - add missing __initconst attributes Signed-off-by: Jamie Iles <jamie@jamieiles.com>
| * | | | | | | | | | Merge branch 'highbank/soc' into next/socArnd Bergmann2011-11-02303-2057/+2996
| |\ \ \ \ \ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/mach-mxs/include/mach/gpio.h arch/arm/mach-omap2/board-generic.c arch/arm/plat-mxc/include/mach/gpio.h
| | * | | | | | | | | | ARM: highbank: add suspend supportRob Herring2011-10-312-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the platform suspend ops for highbank. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | ARM: highbank: Add cpu hotplug supportMartin Bogomolni2011-10-312-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds cpu hotplug for highbank. On highbank, a core is always reset and boots up the same path as a cold boot. Signed-off-by: Martin Bogomolni <martin@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | ARM: highbank: add SMP supportRob Herring2011-10-314-1/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables SMP support on highbank processor. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | MAINTAINERS: add Calxeda Highbank ARM platformRob Herring2011-10-311-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding maintainer for arch/arm/mach-highbank/ Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | ARM: add Highbank core platform supportRob Herring2011-10-3122-1/+444
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds basic support for the Calxeda Highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | ARM: highbank: add devicetree sourceRob Herring2011-10-312-0/+206
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds the devicetree source and documentation for the Calxeda highbank platform. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Reviewed-by: Jamie Iles <jamie@jamieiles.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | ARM: l2x0: add empty l2x0_of_initRob Herring2011-10-311-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add empty version of l2x0_of_init for when CONFIG_CACHE_L2X0 is not selected. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Barry Song <21cnbao@gmail.com> Reviewed-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | | | | | | | Merge branch 'dt/gic' into highbank/socArnd Bergmann2011-10-31559-3065/+8639
| | |\ \ \ \ \ \ \ \ \ \ | | | | |_|_|_|_|/ / / / | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: arch/arm/Kconfig
| | * | | | | | | | | | Merge branch 'depends/rmk/debug' into highbank/socArnd Bergmann2011-10-311-30/+59
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