| Commit message (Collapse) | Author | Age | Files | Lines |
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git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev
Pull libata changes from Jeff Garzik:
"Minor libata updates, nothing notable.
1) Apply -- and then revert -- the FUA feature. Caused disk
corruption in linux-next, proving it cannot be turned on by
default.
Net effect to upstream tree: zero
2) New AHCI platform driver sata_highbank
3) Improve SCSI MODE SENSE handling; support MODE SELECT
4) AHCI: support aggressive device sleep (power mgmt)
5) sata_fsl: minor fix
6) pata_arasan: clk support"
* tag 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jgarzik/libata-dev:
sata_mv: Fix warnings when no PCI
[libata] Makefile: Fix build error in sata_highbank
[libata] export ata_dev_set_feature()
libata-core: use ATA_LBA in ata_build_rw_tf()
ata/ahci_platform: Add clock framework support
pata_arasan: add Device Tree probing capability
pata_arasan: Add clk_{un}prepare() support
ata: add platform driver for Calxeda AHCI controller
sata_fsl: add workaround for data length mismatch on freescale V2 controller
ahci: implement aggressive SATA device sleep support
ata: define enum constants for IDENTIFY DEVICE
Revert "libata: enable SATA disk fua detection on default"
[libata] scsi: implement MODE SELECT command
[libata] scsi: support MODE SENSE request for changeable and default parameters
[libata] scsi: Remove unlikely() from FUA check
libata: enable SATA disk fua detection on default
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Dove can be configured without PCI. We then get a number of warnings:
warning: 'msi' defined but not used
warning: 'mv5_sht' defined but not used
warning: 'mv_dump_pci_cfg' defined but not used.
Move around variables and add #ifdef as necassary to fix the warnings.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Allow sata_highbank to build even if no other users of libahci.o are built.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Since READ/WRITE FPDMA QUEUED commands are 48-bit, bit 6 of the device register
means LBA, the same as for READ/WRITE DMA EXT commands. So use ATA_LBA instead
of the bare number in ata_build_rw_tf()'s branch dedicated to the NCQ commands.
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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On many architectures, drivers are supposed to prepare/unprepare &
enable/disable functional clock of device. This patch adds clock support for
ahci_platform.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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SPEAr platforms now support DT and so must convert all drivers to support DT.
This patch adds DT probing support for Arasan Compact Flash controller and
updates its documentation too.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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clk_{un}prepare is mandatory for platforms using common clock framework. Since
this driver is used by SPEAr platform, which supports common clock framework,
add clk_{un}prepare() support for it.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Calxeda highbank SATA phy has intermittent problems bringing up a link
with Gen3 drives. Retrying the phy hard reset can work-around this issue,
but each reset also disables spread spectrum support. The reset function
also needs to reprogram the phy to enable spread spectrum support.
Create a new driver based on ahci_platform to support the Calxeda Highbank
SATA controller.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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The freescale V2 SATA controller checks if the received data length matches
the programmed length 'ttl', if not, it assumes that this is an error.
In ATAPI, the 'ttl' is based on max allocation length and not the actual
data transfer length, controller will raise 'DLM' (Data length Mismatch)
error bit in Hstatus register. Along with 'DLM', DE (Device error) and
FE (fatal Error) bits are also set in Hstatus register, 'E' (Internal Error)
bit is set in Serror register and CE (Command Error) and DE (Device error)
registers have the corresponding bit set. In this condition, we need to
clear errors in following way: in the service routine, based on 'DLM' flag,
HCONTROL[27] operation clears Hstatus, CE and DE registers, clear Serror
register.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Anju Bhartiya <Anju.Bhartiya@freescale.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Device Sleep is a feature as described in AHCI 1.3.1 Technical Proposal.
This feature enables an HBA and SATA storage device to enter the DevSleep
interface state, enabling lower power SATA-based systems.
Aggressive Device Sleep enables the HBA to assert the DEVSLP signal as
soon as there are no commands outstanding to the device and the port
specific Device Sleep idle timer has expired. This enables autonomous
entry into the DevSleep interface state without waiting for software
in power sensitive systems.
This patch enables Aggressive Device Sleep only if both host controller
and device support it.
Tested on AMD reference board together with Device Sleep supported device
sample.
Signed-off-by: Shane Huang <shane.huang@amd.com>
Reviewed-by: Aaron Lu <aaron.lwe@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Define enumeration constants for IDENTIFY DEVICE words.
Signed-off-by: Shane Huang <shane.huang@amd.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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It caused several reported regressions.
This reverts commit 91895b786e631ab47b618c901231f22b5a44115b.
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The cache_type file in sysfs lets users configure the disk cache in
write-through or write-back modes. However, ata disks do not support
writing to the file because they do not implement the MODE SELECT
command.
This patch adds a translation from MODE SELECT (for the caching page
only) to the ATA SET FEATURES command. The set of changeable parameters
answered by MODE SENSE is also adjusted accordingly.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Since the next patch will introduce support for MODE SELECT, it
makes sense to start advertising which bits are actually changeable.
For now, the answer is none.
Default parameters can also be reported, they are simply the same
as the current parameters.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Some other unlikely() should probably be removed as well. A fresh look
reveals an over-enthusiasm for unlikely() in libata-scsi.c.
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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Currently, SATA disk fua detection is disabled on default because most of
devices don't support this feature at that time. With the development of
technology, more and more SATA disks support this feature. So now we can enable
this detection on default.
Although fua detection is defined as a kernel module parameter, it is too hard
to set its value because it must be loaded and set before system starts up.
That needs to modify initrd file. So it is inconvenient for administrator who
needs to manage a huge number of servers.
Signed-off-by: Zheng Liu <wenqing.lz@taobao.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc
Pull spi updates from Mark Brown:
"No framework work here, only a bunch of driver updates of varying
sizes:
- Factoring out of the core hardware support from the MXS MMC driver
by Marek Vasut to allow the hardware to also be used for SPI.
- Lots of error handling cleanups from Guenter Roeck
- Removal of the existing Tegra driver which is quite comprehensively
broken as detailed in the changelog for the removal.
- DT suppport for the PL022 and GPIO drivers.
- pinctrl support for OMAP and PL022."
Pulling from Mark Brown as Grant Likely is still busy moving.
* tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc: (53 commits)
spi: remove completely broken Tegra driver
spi/imx: set the inactive state of the clock according to the clock polarity
spi/pl022: get/put resources on suspend/resume
spi/pl022: use more managed resources
spi/pl022: Devicetree support w/o platform data
spi/s3c64xx: Don't free controller_data on non-dt platforms
spi: omap2-mcspi: add pinctrl support
spi/pl022: adopt pinctrl support
spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function
spi/gpio: Fix stub for spi_gpio_probe_dt()
spi/mxs: Make the SPI block clock speed configurable via DT
spi: spi-sh-hspi: drop frees of devm_ alloc'd data
spi/pl022: Fix chipselects pointer computation
spi: spi-tle62x0: Use module_spi_driver macro
mxs/spi: Rework the mxs_ssp_timeout to be more readable
mxs/spi: Decrement the DMA/PIO border
mxs/spi: Increment the transfer length only if transfer succeeded
mxs/spi: Fix issues when doing long continuous transfer
spi: spi-gpio: Add DT bindings
spi: spi-gpio: store chipselect information in private structure
...
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The current SPI driver has many issues. Examples are:
* Segfaulting on most transfers due to expecting all transfers to have
both RX and TX buffers.
* Hanging on TX transfers since the whole driver flow is driven by RX
DMA completion, but the HW is only told to enable RX for RX transfers.
* Use of clk_disable_unprepare() from atomic context.
* Once those and other minor issues are fixed, the driver still doesn't
actually work.
* The driver also implements a deprecated API to the SPI core.
For this reason, simply remove the driver completely. This has two
advantages:
1) This will remove the last use of Tegra's <mach/dma.h>, which will
allow that file to be removed, which is required for single zImage
work.
2) The downstream driver is significaly different from the current
code. I believe a patch to re-add the downstream driver (with
appropriate cleanup) will be much simpler to review if it's a new
file rather than randomly interspered with essentially unrelated
existing code.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Linux 3.6-rc6
Conflicts (overlap between moving code that accesses registers around
and factoring the register access out into a SSP layer):
drivers/mmc/host/mxs-mmc.c
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Add "clock-frequency" property, which allows configuring the SPI block's
base speed.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Rework the mxs_ssp_timeout() function to make it a bit more readable
and hopefully less error prone. Also, have only one successful exit
from the function and one failing exit instead of two.
Finally, discard the udelay() from this function altogether, as this
tightloop is quick enough it's pointless.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This driver checks the length of transfer to be made and based
on this information, either chooses to transfer data via DMA or
PIO. Decrement this border further to gain better performace eg.
during SPI flash writes.
Empiric measurement shows that this gives extra 3kB/s write speed
with a M25P80 flash clocked at 40MHz.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The transfer function incremented (struct spi_message)->actual_length
unconditionally, even if the transfer failed. Rectify this by incrementing
this only if transfer succeeded.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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When doing long continuous transfer, eg. from SPI flash via /dev/mtd,
the driver dies. This is caused by a bug in the DMA chaining. Rework
the DMA transfer code so that this issue does not happen any longer.
This involves proper allocation of correct amount of sg-list members.
Also, this means proper creation of DMA descriptors. There is actually an
important catch to this, the data transfer descriptors must be interleaved
with PIO register write descriptor, otherwise the transfer stalls. This
can be done in one descriptor, but due to the limitation of the DMA API,
it's not possible.
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation about about
the PIO transfer that is used.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Lastly, this code lends code from drivers/mtd/nand/omap2.c, which solves
trouble when the buffer supplied to the DMA transfer was vmalloc()'d. So
with this patch, it's safe to use /dev/mtdblockX interface again.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The call sequence spi_alloc_master/spi_register_master/spi_unregister_master
is complete; it reduces the device reference count to zero, which results in
device memory being freed. The remove function accesses the freed memory after
the call to spi_unregister_master(), _and_ it calls spi_master_put on the freed
memory.
Acquire a reference to the SPI master device and release it after cleanup is
complete (with the existing spi_master_put) to solve the problem.
Also, the device subsystem ensures that the remove function is only called once,
and resets device driver data to NULL. Remove the unnecessaary calls to
platform_set_drvdata().
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Marek Vasut <marex@denx.de>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The init_completion() call does reinit not only the variable carrying
the flag that the completion finished, but also initialized the
waitqueue associated with the completion. On the contrary, the
INIT_COMPLETION() call only reinits the flag.
In case there was anything still stuck in the waitqueue, subsequent call
to init_completion() would be able to create possible race condition. This
patch uses the proper function and moves init_completion() into .probe() call
of the driver, to be issued only once.
Note that such scenario is impossible, since two threads can never enter the
mxs_spi_txrx_dma(), since whole this section is protected by mutex in SPI core.
This by no means allows this issue to exit though.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chris Ball <cjb@laptop.org>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Restart the SSP block in case the SSP transfer failed in any way.
The block hung in some cases otherwise.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chris Ball <cjb@laptop.org>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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These parts will be used by the MXS SPI driver too.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This is slightly reworked version of the SPI driver.
Support for DT has been added and it's been converted
to queued API.
Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Pull out the MMC clock configuration function and make it
into SSP clock configuration function, so it can be used by
the SPI driver too.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Abstract out the common part of private data shared between MMC
and SPI. These shall later allow to use common clock configuration
function.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Add missing register bits and registers into mxs-spi.h .
These will be used by the SPI driver.
Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Since the SSP controller can act as both SPI and MMC host,
renaming the enum to properly reflect the naming seems
appropriate.
Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Move the definitions into separate file so separate SPI driver can be
implemented. The SSP controller in MXS can act both as a MMC host and
as a SPI host.
Based on previous attempt by:
Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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There are SPI devices which need a SPI clock with active low polarity and
high inactive state.
Add the setting of the inactive state ECSPIx_CONFIGREG:SCLK CTL
according to the clock polarity ECSPIx_CONFIGREG:SCLK POL:
DT without "spi-cpol" = 0 = clock active high polarity = inactive state low
DT with "spi-cpol" = 1 = clock active low polarity = inactive state high
Signed-off-by: Knut Wohlrab <knut.wohlrab@de.bosch.com>
Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This factors out the resource handling in runtime
suspend/resume and also calls it from the ordinary suspend
and resume hooks.
The semantics require that ordinary PM op suspend is called
with runtime PM in resumed mode, so that ordinary suspend
can assume that it will e.g. decrease the clock reference
counter to 0, runtime resume having previously increased it
to 1.
Cc: Vipul Kumar Samar <vipulkumar.samar@st.com>
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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This switches the PL022 SPI driver to use devm_* managed resources
for IRQ, clocks, ioremap and GPIO. Prior to this, the GPIOs would
even leak.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Linux 3.6-rc6
Conflicts:
drivers/spi/spi-omap2-mcspi.c
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Even with devicetree support, we needed platform data to provide some data,
leading to mixed device tree and platform data. This patch makes it possible to
provide all that information via device tree. Now, the data must be provided
via platform data _or_ device tree completely.
Only in case of DMA where a callback specification is necessary (dma_filter()),
platform data is the only option.
Signed-off-by: Roland Stigge <stigge@antcom.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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When s3c64xx-spi is instantiated from device tree an instance of
struct s3c64xx_spi_csinfo is dynamically allocated in the driver.
For non-dt platform it is passed from board code through
spi_register_board_info(). On error path in s3c64xx_spi_setup()
function there is an attempt to free this data struct
s3c64xx_spi_csinfo object as it would have been allocated in the
driver for both, dt and non-dt based platforms. This leads to
following bug when gpio request fails:
spi spi1.0: Failed to get /CS gpio [21]: -16
kernel BUG at mm/slub.c:3478!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
Modules linked in:
CPU: 0 Not tainted (3.6.0-rc5-00092-g9b0b493-dirty #6111)
PC is at kfree+0x148/0x158
LR is at s3c64xx_spi_setup+0xac/0x290
pc : [<c00a513c>] lr : [<c0227014>] psr: 40000013
sp : ee043e10 ip : c032883c fp : c0481f7c
r10: ee0abd80 r9 : 00000063 r8 : 00000000
r7 : ee129e78 r6 : ee104a00 r5 : fffffff0 r4 : c047bc64
r3 : 40000400 r2 : c047bc64 r1 : c04def60 r0 : 0004047b
Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment kernel
Control: 10c5387d Table: 4000404a DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xee0422f0)
Stack: (0xee043e10 to 0xee044000)
...
[<c00a513c>] (kfree+0x148/0x158) from [<c0227014>] (s3c64xx_spi_setup+0xac/0x290)
[<c0227014>] (s3c64xx_spi_setup+0xac/0x290) from [<c02251a4>] (spi_setup+0x34/0x4c)
[<c02251a4>] (spi_setup+0x34/0x4c) from [<c02258d0>] (spi_add_device+0x98/0x128)
[<c02258d0>] (spi_add_device+0x98/0x128) from [<c02259d4>] (spi_new_device+0x74/0xa8)
[<c02259d4>] (spi_new_device+0x74/0xa8) from [<c0225a2c>] (spi_match_master_to_boardinfo+0x24/0x44)
[<c0225a2c>] (spi_match_master_to_boardinfo+0x24/0x44) from [<c0225b40>] (spi_register_master+0xf4/0x2a8)
[<c0225b40>] (spi_register_master+0xf4/0x2a8) from [<c043fe0c>] (s3c64xx_spi_probe+0x34c/0x42c)
[<c043fe0c>] (s3c64xx_spi_probe+0x34c/0x42c) from [<c01fc198>] (platform_drv_probe+0x18/0x1c)
There should be no attempt to kfree controller_data when it was
externally provided through the board code. Fix this by freeing
controller_data only when dev->of_node is not null.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Adds pinctrl support to support OMAP platforms that boot from DT
and rely on pinctrl support to set pinmuxes.
Signed-off-by: Matt Porter <mporter@ti.com>
Acked-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Amend the PL022 pin controller to optionally take a pin control
handle and set the state of the pins to "default" on boot and
runtime resume, and to "sleep" at runtime suspend. This way we
will dynamically save power on the SPI busses, for example some
electronic designs may be able to ground the pins when unused
instead of pull-up. Some pin controllers may want to set the
pins as wake-up sources when sleeping.
Effect on platforms using the PL022 driver:
- If the platform does not use pin control - no semantic effect,
the pinctrl stubs will kick in and resolve the situation.
- Platforms using this driver and have pin control but no
function defined for the PL022 need to either supply a
"default" function in their map or enable pinctrl dummies
so the driver is satisfied.
- Platforms using this driver with hogs for setting up the PL022
pin control - stop using hogs to take the pl022 pin control
handle, let the driver handle this.
I'be looked at some platforms that may be affected:
- SPEAr: appears to define the proper functions in their device
trees and not hogging them, so things should be smooth, the
driver will simply start to take its pins.
- Ux500: the proper function is defined and will be taken properly
by the driver. New sleep states introduced by a separate patch to
ux500 but no regression, since the default state is sufficient.
- U300: old hog deleted as part of this patch.
- LPC32xx: does not appear to be using pinctrl.
- ARM Integrator IMPD1, RealView & Versatile: does not use pinctrl.
Tested-by: Roland Stigge <stigge@antcom.de>
Signed-off-by: Patrice Chotard <patrice.chotard@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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Currently in omap2_mcspi_txrx_dma the tx and the rx support is
interleaved. Make the rx related code in omap2_mcspi_rx_dma
and the tx related code omap2_mcspi_tx_dma and call the functions.
While at it remove the braces in the if statements which has only
one line.
Also fix ["foo * bar" to "foo *bar"] warn for the rx and tx variables.
Only a cleanup no functional change.
Signed-off-by: Shubhrajyoti D <shubhrajyoti@ti.com>
Tested-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The gpio_ was missing from the name. Add a name for the parameter while
we're at it since GCC warns.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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devm free functions should not have to be explicitly used.
A semantic match that finds this problem is as follows:
(http://coccinelle.lip6.fr/)
// <smpl>
@@
@@
(
* devm_kfree(...);
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* devm_free_irq(...);
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* devm_iounmap(...);
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* devm_release_region(...);
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* devm_release_mem_region(...);
)
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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The new chip select handling via GPIO introduced a pointer computation bug:
(int *) pl022 + sizeof(struct pl022)
doesn't point to the data immediately after the actual struct pl022 (as was
intended) but to a multiple of bytes after it because of the (int *) type.
Replacing the kludgy pointer arithmetic with managed memory allocation for the
chip selects.
Reported-by: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Signed-off-by: Roland Stigge <stigge@antcom.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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