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* Merge tag 'imx-soc-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Arnd Bergmann2013-06-2039-234/+1374
|\ | | | | | | | | | | | | | | into next/dt This is a dependency for imx/dt Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * ARM: imx_v6_v7_defconfig: Enable Vybrid VF610Fabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | Let VF610 SoC support be built by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: Enable imx-wm8962 by defaultNicolin Chen2013-06-171-0/+2
| | | | | | | | | | | | | | Enable imx-wm8962 and PM_RUNTIME, essential for WM8962 CODEC driver. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: clk-imx6qdl: Add clko1 configuration for imx6qdl-sabresdNicolin Chen2013-06-172-0/+44
| | | | | | | | | | | | | | WM8962 needs 24MHz clock for its MCLK, so choose PLL4 as the parent of clko1. Signed-off-by: Nicolin Chen <b42378@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: Enable PWM and backlight optionsFabio Estevam2013-06-171-0/+3
| | | | | | | | | | | | | | These options are useful for controlling backlight contrast via PWM. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: Remove mxc specific ulpi access opsMarkus Pargmann2013-06-175-141/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | There are ulpi access ops implemented in drivers/usb/phy/phy-ulpi.c. mxc access ops implement the same access operations within mach-imx. This patch removes the mxc ulpi file and uses phy-ulpi instead for imx_otg_ulpi_create. phy-ulpi successfully tested with i.MX27 Phytec phyCARD-S (pca100). Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add initial support for VF610Jingchang Lu2013-06-173-0/+65
| | | | | | | | | | | | | | Add initial support for Freescale Vybrid VF610 SoC. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add VF610 clock supportJingchang Lu2013-06-173-0/+508
| | | | | | | | | | | | | | | | | | Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx_v6_v7_defconfig: enable parallel displayRogerio Pimentel2013-06-171-0/+2
| | | | | | | | | | | | | | | | Enable paralell display by default Signed-off-by: Rogerio Pimentel <rogerio.pimentel@freescale.com> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: clk: No need to initialize phandle structFabio Estevam2013-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | commit 84344b43c (ARM: i.MX5: Allow DT clock providers) introduce the following sparse warning: arch/arm/mach-imx/clk.c:12:43: warning: Using plain integer as NULL pointer There is no need to initialize phandle, so remove it. Cc: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: irq-common: Include header to avoid sparse warningFabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | | | | | Fix the following sparse warning: arch/arm/mach-imx/irq-common.c:24:5: warning: symbol 'mxc_set_irq_fiq' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: Enable mx6 solo-lite supportFabio Estevam2013-06-171-0/+1
| | | | | | | | | | Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6: use common of_clk_init() call to initialize clocksShawn Guo2013-06-175-16/+10
| | | | | | | | | | | | | | | | Instead of explicitly calling clock initialization functions, we can declare the functions with CLK_OF_DECLARE() and then call common of_clk_init() to have them invoked properly. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: call of_clk_init() to register fixed rate clocksShawn Guo2013-06-171-14/+5
| | | | | | | | | | | | | | As the fixed rate clocks are defined in device tree, we can just call of_clk_init() to register them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: imx_v6_v7_defconfig: Select CONFIG_DRM_IMX_TVEFabio Estevam2013-06-171-0/+1
| | | | | | | | | | | | | | Let the mx53 TVE driver be built by default. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: clk: add different DualLite MLB clock configDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite reuses the gpu2d_core bits for the MLB clock configuration. Signed-off-by: Dirk Behme <dirk.behme@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX5: Add S/PDIF clocksPhilipp Zabel2013-06-172-1/+39
| | | | | | | | | | | | | | | | | | This patch adds the S/PDIF clocks for i.MX51 and i.MX53. Tested on i.MX53. The i.MX51 has a second set of spdif_root clock dividers, and on i.MX53 there is an additional input to the spdif_xtal mux. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM i.MX53: Add SATA clockSascha Hauer2013-06-172-1/+3
| | | | | | | | | | | | Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6q: clk: add the eim_slow clockHuang Shijie2013-06-172-1/+3
| | | | | | | | | | | | | | Add the eim_slow clock, since the weim needs it. Signed-off-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: remove MLB PLL from pllv3Jiada Wang2013-06-172-11/+0
| | | | | | | | | | | | | | | | | | MLB PLL should be handled internally in MLB driver, so remove it from pllv3. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: disable pll8_mlb in mx6q_clksJiada Wang2013-06-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | The MLB PLL clock's operation doesn't fit for clock framework and it should be handled internally in MLB driver. Remove initialization of pll8_mlb clock device but leave its declaration in mx6q_clks to avoid affecting imx6q clock numbering. Signed-off-by: Jiada Wang <jiada_wang@mentor.com> CC: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add initial support for imx6slShawn Guo2013-06-174-0/+72
| | | | | | | | | | | | Add initial support for i.MX6 SoloLite. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: enable low-level debug support for imx6slShawn Guo2013-06-172-2/+21
| | | | | | | | | | | | | | Enable low-level debug support for i.MX6 SoloLite by adding the debug port definitions for the SoC. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: add clock support for imx6slShawn Guo2013-06-173-0/+428
| | | | | | | | | | | | | | | | | | Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: create mxc_arch_reset_init_dt() for DT bootShawn Guo2013-06-177-9/+26
| | | | | | | | | | | | | | | | | | | | The mxc_arch_reset_init() uses static mapping and calls clk_get_sys() to get clock. It's suitable for non-DT boot but not for DT boot where dynamic mapping and of_clk_get() should be used instead. Create mxc_arch_reset_init_dt() as the DT variant of mxc_arch_reset_init(), and change DT platforms to use it. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: move clk_prepare() out from mxc_restart()Shawn Guo2013-06-1712-18/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's inappropriate to call clk_prepare() in mxc_restart(), because the restart routine could be called in atomic context. Move clk_get() and clk_prepare() into mxc_arch_reset_init() and only have the atomic part clk_enable() be called in mxc_restart(). As a result, mxc_arch_reset_init() needs to be called after clk gets initialized. While there, it also changes printk(KERN_ERR ...) to pr_err() and adds __init annotation for mxc_arch_reset_init(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: include <asm/io.h> in hardware.hShawn Guo2013-06-171-0/+1
| | | | | | | | | | | | | | As IOMEM is referenced in hardware.h, <asm/io.h> should be included there. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: clk: add i.MX6 DualLite differencesDirk Behme2013-06-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CCM_CBCMR register (address 0x02C4018) has different meaning between the i.MX6 Quad/Dual and the i.MX6 Solo/DualLite. Compared to the i.MX6 Quad/Dual, the CCM_CBCMR register in the i.MX6 Solo/DualLite doesn't have a gpu3d_shader configuration and moves the gpu2_core configuration at that place. Handle these i.MX6 Quad/Dual vs. i.MX6 Solo/DualLite clock differences by using cpu_is_mx6dl(). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: i.MX6: add i.MX6 specific L2 cache configurationDirk Behme2013-06-171-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To improve the performance and power consumption add an i.MX6 specific L2 cache initialization. This configuration is taken from Freescale's kernel patch "ENGR00153601 [MX6]Adjust L2 cache parameter" [1] with two additional improvements: a) The L2X0_POWER_CTRL has only the two bits we set. So no need to read the register before. Remove the register read done in Freescale's patch. b) In the L2X0_PREFETCH_CTRL register, besides the double linefill (bit[30]), additionally enable the instruction and data prefetch (bit[29-28]). Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> [1] http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/arch/arm/mach-mx6/mm.c?h=imx_3.0.35_12.09.01&id=814656410b40c67a10b25300e51b0477b2bb96d1
| * ARM: i.MX5: Allow DT clock providersMartin Fuzzey2013-06-173-36/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently clock providers defined in the DT are not registered on i.MX5 platforms since of_clk_init() is not called. This is not a problem for the SOC's own clocks, which are registered in code, but prevents the DT being used to define clocks for external hardware. Fix this by calling of_clk_init() and actually using the DT to obtain the 4 SOC fixed clocks. These are already defined in the DT but were previously just used to manually obtain the rate. Fall back to the old scheme for non DT platforms. Since the same method may be useful for other i.MX platforms implement the imx_obtain_fixed_clock() function in common code. Actually changing other i.MX platforms to use this should be done later by someone with access to the appropriate hardware. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Tested-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | Merge tag 'mxs-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6 ↵Arnd Bergmann2013-06-20251-1878/+3206
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into next/dt From Shawn Guo: mxs device tree changes for 3.11: * A couple of new board support, cfa10055 and cfa10057 * A few updates on cfa10036 device tree source * Some auart pinctrl data addition * Adopt soc bus infrastructure for mach-mxs * tag 'mxs-dt-3.11' of git://git.linaro.org/people/shawnguo/linux-2.6: ARM: mxs: dt: Add Crystalfontz CFA-10057 device tree ARM: mxs: dt: Add the Crystalfontz CFA-10055 device tree ARM: cfa10049: Switch the chip select pin of the LCD controller ARM: cfa10036: Add USB0 OTG port ARM: dts: apf28dev: Add touchscreen support for APF28dev ARM: mxs: Fix UARTs on M28EVK ARM: cfa10036: dt: Change i2c0 clock frequency ARM: dts: cfa10036: Change the OLED display to SSD1306 ARM: mx28: add auart4 2 pins pinmux to imx28.dtsi ARM: mx28: add auart3 2 pins pinmux to imx28.dtsi ARM: mx28: add auart2 2 pins pinmux to imx28.dtsi ARM: mxs: Use soc bus infrastructure ARM: dts: mx28: Adjust the digctl compatible string ARM: mxs: Remove init_irq declaration in machine description Includes an update to 3.10-rc6 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | ARM: mxs: dt: Add Crystalfontz CFA-10057 device treeBrian Lilly2013-06-173-1/+194
| | | | | | | | | | | | | | | | | | | | | | | | | | | The CFA-10057 is a breakout board for the CFA-10036 that has Ethernet, USB and a 4.3" LCD screen on it. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: dt: Add the Crystalfontz CFA-10055 device treeBrian Lilly2013-06-173-10/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CFA-10055 is yet another breakout board for the CFA-10036, and is basically a CFA-10037, with the screen and LCD controller found on the CFA-10049. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: cfa10049: Switch the chip select pin of the LCD controllerBrian Lilly2013-06-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The early prototypes had the chip select pin for the LCD controller wired on the GPIO 3-23, while the production run of the CFA-10049 have this chip select on the GPIO 3-5. Signed-off-by: Brian Lilly <brian@crystalfontz.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: cfa10036: Add USB0 OTG portMaxime Ripard2013-06-171-0/+23
| | | | | | | | | | | | | | | Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: dts: apf28dev: Add touchscreen support for APF28devGwenhael Goavec-Merou2013-06-171-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: Fix UARTs on M28EVKMarek Vasut2013-06-171-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of RTS/CTS lines on AUART0 and register AUART1 and AUART2 which are routed onto a pin header. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: cfa10036: dt: Change i2c0 clock frequencyMaxime Ripard2013-06-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The OLED display can work faster. Change the i2c controller clock frequency to remove the tearing effect that can be seen on the display. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: dts: cfa10036: Change the OLED display to SSD1306Maxime Ripard2013-06-172-11/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SSD1307 was used in an early prototype that will never get distributed. The final board now has a SSD1306 instead, that has its own power generation unit and thus doesn't need any PWM. The panel attached to it also changed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mx28: add auart4 2 pins pinmux to imx28.dtsiEric Bénard2013-06-171-0/+11
| | | | | | | | | | | | | | | | | | | | | Add auart4 2 pins configuration on SSP3 pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mx28: add auart3 2 pins pinmux to imx28.dtsiEric Bénard2013-06-171-0/+11
| | | | | | | | | | | | | | | | | | | | | Add auart3 2 pins configuration on its main pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mx28: add auart2 2 pins pinmux to imx28.dtsiEric Bénard2013-06-171-0/+11
| | | | | | | | | | | | | | | | | | | | | Add auart2 2 pins configuration on its main pads Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: Use soc bus infrastructureFabio Estevam2013-06-172-1/+117
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using the soc bus infrastructure is helpful for reporting several SoC related information such as: family, machine, SoC name and SoC revision. $ cat /sys/bus/soc/devices/soc0/family Freescale MXS Family $ cat /sys/bus/soc/devices/soc0/machine Freescale i.MX28 Evaluation Kit $ cat /sys/bus/soc/devices/soc0/soc_id i.MX28 $ cat /sys/bus/soc/devices/soc0/revision TO1.2 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: dts: mx28: Adjust the digctl compatible stringFabio Estevam2013-06-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | MX28 has the same DIGCTL block as MX23, so adjust the compatible string to reflect that. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: mxs: Remove init_irq declaration in machine descriptionMaxime Ripard2013-06-171-2/+0
| |/ | | | | | | | | | | | | | | | | | | Commit ebafed7a ("ARM: irq: Call irqchip_init if no init_irq function is specified") removed the need to explictly setup the init_irq field in the machine description when using only irqchip_init. Remove that declaration for mxs as well. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * Linux 3.10-rc6v3.10-rc6Linus Torvalds2013-06-151-1/+1
| |
| * Merge tag 'fixes-for-linus' of ↵Linus Torvalds2013-06-1513-29/+96
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC fixes from Olof Johansson: "These are a little later than I planned on since I got caught up with handling merges for 3.11 most of the week. Another week, another batch of fixes for arm-soc platforms. Again, nothing controversial. A few more than would be ideal, but all are valid fixes. In particular the prima2 panic patch is critical since it fixes a problem where multiplatform kernels panic on all but prima2 hardware." * tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: ARM: SAMSUNG: pm: Adjust for pinctrl- and DT-enabled platforms ARM: prima2: fix incorrect panic usage arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant(). ARM: omap3: clock: fix wrong container_of in clock36xx.c ARM: dts: OMAP5: Fix missing PWM capability to timer nodes ARM: dts: omap4-panda|sdp: Fix mux for twl6030 IRQ pin and msecure line ARM: dts: AM33xx: Fix properties on gpmc node arm: omap2: fix AM33xx hwmod infos for UART2 ARM: OMAP3: Fix iva2_pwrdm settings for 3703
| | * Merge tag 'fixes-3.10-4' of git://git.infradead.org/users/jcooper/linux into ↵Olof Johansson2013-06-113-6/+9
| | |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | fixes From Jason Cooper, mvebu fixes for v3.10 round 4: - mvebu - fix PCIe ranges property so NOR flash is visible - kirkwood - fix identification of 88f6282 so MPPs can be set correctly * tag 'fixes-3.10-4' of git://git.infradead.org/users/jcooper/linux: arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe range ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant(). Signed-off-by: Olof Johansson <olof@lixom.net>
| | | * arm: mvebu: armada-xp-{gp,openblocks-ax3-4}: specify PCIe rangeThomas Petazzoni2013-06-062-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ranges DT entry needed by the PCIe controller is defined at the SoC .dtsi level. However, some boards have a NOR flash, and to support it, they need to override the SoC-level ranges property to add an additional range. Since PCIe and NOR support came separately, some boards were not properly changed to include the PCIe range in their ranges property at the .dts level. This commit fixes those platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | | * ARM: Kirkwood: handle mv88f6282 cpu in __kirkwood_variant().Nicolas Schichan2013-06-061-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPP_F6281_MASK would be previously be returned when on mv88f6282, which would disallow some valid MPP configurations. Commit 830f8b91 (arm: plat-orion: fix printing of "MPP config unavailable on this hardware") made this problem visible as an invalid MPP configuration is now correctly detected and not applied. Signed-off-by: Nicolas Schichan <nschichan@freebox.fr> Cc: <stable@vger.kernel.org> # v3.9.x Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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