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* ARM: shmobile: r8a7779: Add clock index macros for DT sourcesSimon Horman2014-05-271-0/+64
| | | | | | | | | | | Add macros usable by device tree sources to reference r8a7779 clocks by index. Based on work for the r8a7791 SoC by Laurent Pinchart. Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: Fix overflow in clk_divider_bestdivTomasz Figa2014-05-271-1/+1
| | | | | | | | | | | | | | | | | Commit c686078 ("clk: divider: Add round to closest divider") introduced a helper function to check whether given divisor is the best one instead of direct check. However due to int type used instead of unsigned long for passing calculated rates to this function in certain cases an overflow could occur, for example when trying to obtain maximum possible clock rate by calling clk_round_rate(..., UINT_MAX). This patch fixes this issue by changing the type of rate, now and best arguments of the function to unsigned long, which is the type that should be used for clock rates. Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: u300: Terminate of match tableStephen Boyd2014-05-271-0/+1
| | | | | | | | | Failure to terminate this match table can lead to boot failures depending on where the compiler places the match table. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* MAINTAINERS: add AT91 Clock Support entryBoris BREZILLON2014-05-271-0/+5
| | | | | | Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: bcm/kona: implement determine_rate()Alex Elder2014-05-271-1/+53
| | | | | | | | | | | | | | | Implement the clk->determine_rate method for Broadcom Kona peripheral clocks. This allows a peripheral clock to be re-parented in order to satisfy a rate change request. This takes the place of the previous kona_peri_clk_round_rate() functionality, though that function remains because it is used by the new one. The parent clock that allows the peripheral clock to produce a rate closest to the one requested is the one selected, though the current parent is used by default. Signed-off-by: Alex Elder <elder@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: qcom: Fix blsp2_ahb_clk register offsetGeorgi Djakov2014-05-231-1/+1
| | | | | | | | The address of the blsp2_ahb_clk register is incorrect. Fix it. Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s2mps11: Add support for S2MPS14 clocksKrzysztof Kozlowski2014-05-232-20/+52
| | | | | | | | | | | | This patch adds support for S2MPS14 PMIC clocks (BT and AP) to the s2mps11 clock driver. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Yadwinder Singh Brar <yadi.brar@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s2mps11: Remove useless check for clk_tableKrzysztof Kozlowski2014-05-231-13/+11
| | | | | | | | | | There is no need for checking if 'clk_table' is not NULL twice (first after allocation and second at the end of probe()). Also move allocation of this 'clk_table' to probe from s2mps11_clk_parse_dt as this is logical place for it. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: s2mps11: Add missing of_node_put and of_clk_del_providerKrzysztof Kozlowski2014-05-231-5/+11
| | | | | | | | Add of_clk_del_provider to remove previously registered clock provider. Add of_node_put to decrement the ref count of clock nodes. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-231-1/+1
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| * clk: divider: Fix table round up functionMaxime COQUELIN2014-05-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 1d9fe6b97 ("clk: divider: Fix best div calculation for power-of-two and table dividers") introduces a regression in its _table_round_up function. When the divider passed to this function is greater than the max divider available in the table, this function returns table's max divider. Problem is that it causes an infinite loop in clk_divider_bestdiv() because _next_div() will never return a value greater than maxdiv. Instead of returning table's max divider, this patch returns INT_MAX. Reported-by: Fabio Estevam <festevam@gmail.com> Reported-by: Shawn Guo <shawn.guo@freescale.com> Tested-by: Fabio Estevam <festevam@gmail.com> Tested-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* | Merge remote-tracking branch 'linaro/clk-next' into clk-nextMike Turquette2014-05-2369-813/+3389
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| * clk: Neaten clk_summary outputGeert Uytterhoeven2014-05-231-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Limit ruler to 80 characters (was: 81), - Widen rate column by 1 for nicer spacing, - Right-align numbers and their column headers, - Move a newline to reduce the number of seq_printf() calls, - Use set_puts() for fixed strings. Before: clock enable_cnt prepare_cnt rate accuracy --------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 After: clock enable_cnt prepare_cnt rate accuracy -------------------------------------------------------------------------------- extal 2 2 20000000 0 thermal 1 1 20000000 0 cp 0 0 10000000 0 tpu0 0 0 10000000 0 tmu0 0 0 10000000 0 main 1 1 20000000 0 pll3 0 0 1600000000 0 ddr 0 0 200000000 0 zb3d2 0 0 200000000 0 zb3 0 0 400000000 0 pll1 4 4 1560000000 0 oscclk 0 0 126953 0 rclk 1 1 31738 0 cmt1 0 0 31738 0 cmt0 1 1 31738 0 imp 0 0 390000000 0 Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: divider: add CLK_DIVIDER_READ_ONLY flagHeiko Stuebner2014-05-232-1/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Heiko Stuebner <heiko@sntech.de> Similar to muxes which already have a read-only flag there sometimes exist dividers which should not be changed by the clock framework but whose value still should be readable. Therefore add a READ_ONLY flag similar to the mux-one to clk-divider Signed-off-by: Heiko Stuebner <heiko@sntech.de> [changed flag bit to BIT(5) as suggested by Tomasz Figa] Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Max Schwarz <max.schwarz@online.de> Tested-by: Max Schwarz <max.schwarz@online.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: shmobile: Add R8A7740-specific clock supportUlrich Hecht2014-05-233-0/+241
| | | | | | | | | | | | | | | | | | | | Driver for the R8A7740's clocks that are too specific to be supported by a generic driver. Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: tegra: Initialize xusb clocksAndrew Bresticker2014-05-222-1/+12
| | | | | | | | | | | | | | | | | | Initialize the XUSB-related clocks with appropriate parents and rates for both Tegra114 and Tegra124. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: tegra: Fix xusb_hs_src clock hierarchyAndrew Bresticker2014-05-226-22/+21
| | | | | | | | | | | | | | | | | | | | | | Currently the Tegra1x4 clock init code hard-codes the mux setting for xusb_hs_src and treats it as a fixed-factor clock. It is, however, a mux which can be parented by either xusb_ss_src/2 or pll_u_60M. Add the fixed-factor clock xusb_ss_div2 and put an entry in periph_clks[] for the xusb_hs_src mux. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: tegra: Fix xusb_fs_src muxJim Lin2014-05-221-1/+3
| | | | | | | | | | | | | | | | | | The parent-to-index mapping for xusb_fs_src is incorrect. Fix it by adding a mux table. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: tegra: Enable hardware control of PLLEJim Lin2014-05-221-1/+32
| | | | | | | | | | | | | | | | | | | | Enable hardware control of PLLE spread-spectrum, IDDQ, and enable controls when enabling PLLE. The hardware (e.g. XUSB) using PLLE will use these controls for power-saving optimizations. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Andrew Bresticker <abrestic@chromium.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Add clock driver for AXM55xx SoCAnders Berg2014-05-223-0/+645
| | | | | | | | | | | | | | | | | | | | Add clk driver to support clock blocks found on the AXM55xx devices. The driver provides clock implementations for three different types of clock devices on the AXM55xx device: PLL clock, a clock divider and a clock mux. Signed-off-by: Anders Berg <anders.berg@lsi.com> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: shmobile: mstp: Fix the is_enabled() operationLaurent Pinchart2014-05-221-1/+1
| | | | | | | | | | | | | | | | | | The MSTP[SC]R registers have clock stop bits, not clock enable bits. The bit value should thus be inverted in the is_enabled() operation. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: Add of_clk_get_by_clkspec() helperSylwester Nawrocki2014-05-222-7/+28
| | | | | | | | | | | | | | | | | | | | This patch adds of_clk_get_by_clkspec() helper function, which does only a struct clk lookup from the clock providers. It is used in the subsequent patch where parsing of a clock from device tree and the lookup from providers needed to be split. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * clk: impd1: add pclk clocksLinus Walleij2014-05-211-7/+29
| | | | | | | | | | | | | | | | | | | | The IM-PD1 PrimeCells all have pclk assignments though this clock cannot be controlled, and we need to provide this as a dummy clock for the PL061 GPIO driver to probe, so let's assign it to all the cells on the board. Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * Merge tag 'zynq-clk-for-3.16' of git://git.xilinx.com/linux-xlnx into ↵Mike Turquette2014-05-202-1/+13
| |\ | | | | | | | | | | | | | | | | | | | | | | | | clk-next-zynq arm: Xilinx Zynq clk patches for v3.16 - Keep debug clocks in bootup state - Fix email address in si570
| | * clk: si570: Fix email address specifictionMichal Simek2014-05-201-1/+1
| | | | | | | | | | | | | | | | | | Just fix missing ">" in the email. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| | * clk: zynq: Leave debug clocks in bootup stateSoren Brinkmann2014-04-221-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Make sure debug clocks stay enabled if the bootloader enabled them. Otherwise debug HW may crash due to bus-hangs caused by stopped clocks. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * | clk: qcom: Fix msm8660 GCC probeStephen Boyd2014-05-161-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When consolidating the msm8660 GCC probe code I forgot to keep around these temporary clock registrations. Put them back so the clock tree is not entirely orphaned. Fixes: 49fc825f0cc2 (clk: qcom: Consolidate common probe code) Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-161-1/+1
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| * | | Documentation: clock: fixed-clock: Remove unsupported 'gpios' propertyFabio Estevam2014-05-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the 'gpios' property from the documentation as this is something that the current fixed clock driver does not handle. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk/versatile: export symbols for impd1Arnd Bergmann2014-05-142-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The impd1 code on mach-integrator can be a loadable module, so we have to export icst_clk_register, integrator_impd1_clk_init and integrator_impd1_clk_exit. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | Merge tag 'clk-hisi-for-v3.16' of ↵Mike Turquette2014-05-147-5/+231
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | https://git.kernel.org/pub/scm/linux/kernel/git/hzhuang1/linux into clk-next-hisilicon enable hix5hd2 clock
| | * | | clk: hisi: add clk-hix5hd2.cZhangfei Gao2014-05-125-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Haifeng Yan <haifeng.yan@linaro.org> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| | * | | clk: hisi: add hisi_clk_register_gateZhangfei Gao2014-05-122-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hisi_clk_register_gate register clk gate table Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| | * | | clk: hisi: use clk_register_mux_table in hisi_clk_register_muxZhangfei Gao2014-05-122-5/+9
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | Platform hix5hd2 use mux table, so use clk_register_mux_table instead Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
| * | | clk: sunxi: Fixup clk_sunxi_mmc_phase_control to take a clk rather then a hw_clkHans de Goede2014-05-142-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __clk_get_hw is supposed to be used by clk providers, not clk consumers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | Merge tag 'clk-mvebu-3.16' of git://git.infradead.org/linux-mvebu into ↵Mike Turquette2014-05-134-0/+223
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next-mvebu clk mvebu changes for v3.16 - orion5x: brand new driver
| | * | | clk: mvebu: add Orion5x clock driverThomas Petazzoni2014-04-264-0/+223
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds a core clock driver for the Orion5x SoC, with support for the tclk, the CPU frequency and the DDR frequency. All the details about the Sample-At-Reset register were extracted from the U-Boot sources for Orion5x. Note that Orion5x does not have gatable clocks, so this core clock driver is sufficient to support clocking on Orion5x platforms. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Link: https://lkml.kernel.org/r/1398202002-28530-5-git-send-email-thomas.petazzoni@free-electrons.com Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * | | clk: shmobile: r8a7779: Add MSTP clock supportSimon Horman2014-05-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MSTP clock support for the r8a7779 SoC The only change required appears to be to note a new compatibility string in the bindings. Cc: devicetree@vger.kernel.org Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | clk: shmobile: r8a7779: Add clocks supportSimon Horman2014-05-124-0/+211
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The R8A7779 SoC has several clocks that are too custom to be supported in a generic driver. Those clocks are all fixed rate clocks with multiplier and divisor set according to boot mode configuration. Based on work for R-Car Gen2 SoCs by Laurent Pinchart. Cc: devicetree@vger.kernel.org Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | Merge tag 'socfpga-clk-update-for-v3.16' of ↵Mike Turquette2014-05-123-4/+23
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.rocketboards.org/linux-socfpga-next into clk-next-socfpga Adds support getting the divider registers for the MAIN PLL that was once thought to be hidden.
| | * | | clk: socfpga: add divider registers to the main pll outputsDinh Nguyen2014-05-123-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The C0(mpu_clk), C1(main_clk), and C2(dbg_base_clk) outputs from the main PLL go through a pre-divider before coming into the system. These registers were hidden for the CycloneV platform, but are now used for the ArriaV platform. This patch updates the clock driver to read the div-reg property for the socfpga-periph-clk clocks. Also moves the div_mask define to clk.h for re-use. Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
| * | | | clk: Improve clock-indices binding documentationGeert Uytterhoeven2014-05-121-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve the wording for the clock-indices binding documentation. Also replace "empty nodes" by "empty strings", as reported before by Sergei Shtylyov. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Improve clk_ops documentationGeert Uytterhoeven2014-05-122-24/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | General: - Add parameter names to .round_rate() and .set_rate(). Documentation/clk.txt: - Add missing parameter for .set_rate(), - Add missing .debug_init(). include/linux/clk-provider.h: - Add parent rate documentation for .round_rate(), - Reorder documentation to match implementation order, - Add missing documentation for .init(). Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | clk: Fixup spacing in commentsGeert Uytterhoeven2014-05-121-44/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove spaces in front of TABs, - Correct indentation for some CLK_* flag descriptions. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | Merge branch 'clk-fixes' into clk-nextMike Turquette2014-05-122-3/+8
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| * | | | | clk: sunxi: Implement MMC phase controlEmilio López2014-05-052-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HdG: add header exporting clk_sunxi_mmc_phase_control Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | clk: sunxi: factors: automatic reparenting supportEmilio López2014-05-051-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements .determine_rate, so that our factor clocks can be reparented when needed. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | clk: qcom: Various fixes for MSM8960's global clock controllerKumar Gala2014-04-303-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Remove CE2_SLEEP_CLK, doesn't exist on 8960 family SoCs * Fix incorrect offset for PMIC_SSBI2_RESET * Fix typo: SIC_TIC -> SPS_TIC_H SFAB_ADM0_M2_A_CLK -> SFAB_ADM0_M2_H_CLK * Fix naming convention: SFAB_CFPB_S_HCLK -> SFAB_CFPB_S_H_CLK SATA_SRC_CLK -> SATA_CLK_SRC Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
| * | | | | clk: qcom: Add basic support for APQ8064 global clock controller clocksKumar Gala2014-04-303-5/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The APQ8064 and MSM8960 share a significant amount of clock data and code between the two SoCs. Rather than duplicating the data we just add support for a unqiue APQ8064 clock table into the MSM8960 code. For now add just enough clocks to get a basic serial port going on an APQ8064 device. Signed-off-by: Kumar Gala <galak@codeaurora.org> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: trivial conflict due to missing ipq8064 support]
| * | | | | clk: qcom: Consolidate common probe codeStephen Boyd2014-04-308-337/+196
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the probe code is the same between all the different clock controllers. Consolidate the code into a common.c file. This makes changes to the common probe parts easier and reduces chances for bugs. Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
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