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* clk: samsung: exynos5420: update clocks for FSYS and FSYS2 blocksShaik Ameer Basha2014-05-141-12/+25
| | | | | | | | | This patch adds more clocks from FSYS and FSYS2 blocks and uses GATE_IP_* registers for gating IPs. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for WCORE blockShaik Ameer Basha2014-05-141-0/+25
| | | | | | | | This patch adds missing clocks for WCORE block. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for PERIS and GEN blocksShaik Ameer Basha2014-05-142-31/+48
| | | | | | | | | | This patch fixes some parent-child relationships according to the latest datasheet and adds more clocks related to PERIS and GEN blocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for PERIC blockShaik Ameer Basha2014-05-143-62/+58
| | | | | | | | | | | | | This patch includes, 1] renaming of the HSI2C clocks 2] renaming of spi clocks according to the datasheet 3] fixes for child-parent relationships 4] adding of more clocks related to PERIC block 5] use GATE_IP_* offsets instead of GATE_BUS_* Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for DISP1 blockShaik Ameer Basha2014-05-142-18/+41
| | | | | | | | | This patch corrects some child-parent clock relationships, and updates the clocks according to the latest datasheet. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for G2D and G3D blocksShaik Ameer Basha2014-05-142-7/+13
| | | | | | | | | This patch adds missing clocks of G2D block. It also removes the aclkg3d alias from G3D block clocks. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: fix parent clocks for mscl sysmmuShaik Ameer Basha2014-05-141-3/+6
| | | | | | | | This patch fixes the parent clocks for mscl sysmmu. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: update clocks for GSCL and MSCL blocksShaik Ameer Basha2014-05-142-28/+47
| | | | | | | | | This patch adds the missing GSCL and MSCL block clocks and corrects some wrong parent-child relationships. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: add clocks for ISP blockShaik Ameer Basha2014-05-142-0/+93
| | | | | | | | | This patch adds minimum set of clocks to gate ISP block for power saving. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: Rename mux parent arraysShaik Ameer Basha2014-05-141-173/+186
| | | | | | | | | | This patch renames the mux parent arrays as per the naming convension followed by the other exynos specific clock drivers. And it also renames "mout_cpu_kfc" clock to "mout_kfc". Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Shaik Ameer Basha <shaik.ameer@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: Add clock IDs needed by GPUArun Kumar K2014-05-142-2/+4
| | | | | | | | Adds IDs for the clocks needed by the ARM Mali GPU in exynos5420. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos4: export sclk_hdmiphy clockTomasz Stanislawski2014-05-142-1/+2
| | | | | | | Export sclk_hdmiphy clock to be usable from DT. Signed-off-by: Tomasz Stanislawski <t.stanislaws@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250: Add clocks for G3DArun Kumar K2014-05-142-2/+17
| | | | | | | | | This patch adds the required clocks for ARM Mali IP in Exynos5250. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> [t.figa: Changed clock ID to avoid conflict with CLK_SSS] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos4: Use single clock ID for CLK_MDMA gate clocksSylwester Nawrocki2014-05-142-2/+1
| | | | | | | | | | | | | | Exynos4210 and Exynos4x12 SoCs have the PL330 MDMA IP block clock defined exactly in same way in documentation. Using different names for these clocks is a bit misleading. Since there is no users of CLK_MDMA2 in existing dts files this patch drops CLK_MDMA2 and replaces it with CLK_MDMA in the driver. This ensures PL330 MDMA has correct clock assigned on Exynos4x12 SoCs. Suggested-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: fixed compiler warning [-Wpointer-to-int-cast]Pankaj Dubey2014-05-141-1/+1
| | | | | | | | | | | When compiled using ARM64 cross compiler, gcc complains as drivers/clk/samsung/clk.c:293:18: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5420: Fix VPLL lock offsetSachin Kamat2014-05-141-1/+1
| | | | | | | Set it as per the user manual. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: exynos5250/5420: Add gate clock for SSS moduleNaveen Krishna Chatradhi2014-05-143-0/+6
| | | | | | | | | This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk: samsung: Initialize clock table with error pointersTomasz Figa2014-05-141-1/+6
| | | | | | | | | | Before this patch, the driver was simply zeroing the clock table, which is incorrect, because invalid clock numbers returned NULL instead of error pointers. This patch fixes this by changing the driver to initialize the array with PTR_ERR(-ENOENT). Signed-off-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
* clk/exynos5260: add clock file for exynos5260Rahul Sharma2014-05-143-0/+2440
| | | | | | | | Add support for exynos5260 clocks in clock driver. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/exynos5260: add macros and documentation for exynos5260Rahul Sharma2014-05-142-0/+659
| | | | | | | | Add macros which are used as Clock IDs in DT and clock file. It also adds the documentation for the exynos5260 clocks. Signed-off-by: Rahul Sharma <Rahul.Sharma@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/samsung: add support for pll2650xxRahul Sharma2014-05-142-0/+102
| | | | | | | | | | | Add support for pll2650xx in samsung pll file. This PLL variant is close to pll36xx but uses CON2 registers instead of CON1. Aud_pll in Exynos5260 is pll2650xx and uses this code. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/samsung: add support for pll2550xxPankaj Dubey2014-05-142-0/+109
| | | | | | | | | | | exynos5260 use pll2550xx and it has different bit fields for P,M,S values as compared to pll2550. Support for pll2550xx is added here. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* clk/samsung: add support for multiple clock providersRahul Sharma2014-05-1411-205/+279
| | | | | | | | | | | | | | | | | | Samsung CCF helper functions do not provide support to register multiple Clock Providers for a given SoC. Due to this limitation, SoC platforms are not able to use these helpers for registering multiple clock providers and are forced to bypass this layer. This layer is modified accordingly to enable the support for multiple clock providers. Clock file for exynos4, exynos5250, exynos5420, exynos5440, S3c64xx, S3c24xx are also modified as per changed helper functions. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> [t.figa: Modified s3c2410 clock driver as well] Signed-off-by: Tomasz Figa <t.figa@samsung.com>
* ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversionHeiko Stuebner2014-05-139-160/+0
| | | | | | | | This finally removes all remaining SAMSUNG_CLOCK conditional code from s3c24xx architectures. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: remove legacy clock codeHeiko Stuebner2014-05-1313-1122/+0
| | | | | | | | | | | With the move to the common clock framework completed for s3c2410, s3c2440 and s3c2442, the legacy clock code for these machines can go away too. This also includes the legacy dclk code, as all legacy users are converted. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: convert s3c2410 to common clock frameworkHeiko Stuebner2014-05-1312-34/+67
| | | | | | | | | | | | Convert the machines using the s3c2410 to use the new driver based on the common clock framework instead of the legacy Samsung clock driver. As with the s3c244x, machines using the clkout output will need a fixup from someone with the hardware. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock frameworkHeiko Stuebner2014-05-1312-36/+73
| | | | | | | | | | | | | Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Some of the more esotheric machines will probably need a fixup, as they do strange things to the clkout outputs, that I did not really understand nor have the hardware to check. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: add platform code for conversion to the common clock frameworkHeiko Stuebner2014-05-136-1/+51
| | | | | | | | | | | | | This adds the necessary init functions to init the clocks from the common clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy clock code. This also includes empty stubs for the *_setup_clocks functions that are called from the cpufreq driver on resume. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442Heiko Stuebner2014-05-133-0/+540
| | | | | | | | | | | | | | | | | | | | This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* dt-bindings: add documentation for s3c2410 clock controllerHeiko Stuebner2014-05-131-0/+50
| | | | | | | | Describe the clock controller of s3c2410, s3c2440 and s3c2442. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: enable usage of common dclk if common clock framework is enabledHeiko Stuebner2014-05-139-5/+60
| | | | | | | | | | | | | | | | | Add platform device and select the correct implementation automatically depending on wether the old samsung_clock or the common clock framework is enabled. This is only done for machines already using the old dclk implementation, as everybody else should move to use dt anyway. The machine-specific settings for the external clocks will have to be set by somebody with knowledge about the specific hardware. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> [pebolle@tiscali.nl: pointed out typo and fixed] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add clock driver for external clock outputsHeiko Stuebner2014-05-092-0/+441
| | | | | | | | | | | | | | This adds a driver for controlling the external clock outputs of s3c24xx architectures including the dclk muxes and dividers. The driver at the moment only supports the legacy non-dt boards using these clock outputs. The clock-output control itself is part of the system-controller mainly controlled by the pinctrl drivers. So it should most likely be integrated there for dt platforms. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccfHeiko Stuebner2014-05-093-0/+10
| | | | | | | | | | | | | | | | | | | | The s3c24xx cpufreq driver needs to change the mpll speed and was doing this by writing raw values from a translation table into the MPLLCON register. Change this to use a regular clk_set_rate call when using the common clock framework and only write the raw value in the samsung_clock case. The s3c cpufreq driver does already aquire the mpll, so simply add a reference to struct s3c_cpufreq_config to let set_fvco access it. While struct clk is opaque the differenciation between samsung clock and common clock is kept, as the samsung-clock mpll clk does not implement a real set_rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: convert s3c2412 to common clock frameworkHeiko Stuebner2014-04-159-813/+40
| | | | | | | | | Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add clock controller driver for s3c2412Heiko Stuebner2014-04-153-0/+343
| | | | | | | | | | | | | This driver can handle the clock controller in the s3c2412 soc. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* dt-bindings: add documentation for s3c2412 clock controllerHeiko Stuebner2014-04-151-0/+50
| | | | | | | Describe the clock controller of the s3c2412. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add plls used by the early s3c24xx cpusHeiko Stuebner2014-04-152-0/+185
| | | | | | | | | | | | | The manuals do not give them explicit names like in later socs, so more generic names with a s3c2410-prefix were used for them. As it was common to do so in the previous implementation, functionality to change the pll rate is already included. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: only store clock registers when old clock code is activeHeiko Stuebner2014-04-151-3/+10
| | | | | | | | | | The Samsung ccf driver already handles the save and restore of the clock registers on suspend and resume. The architecture code should not duplicate this when the ccf is active. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock frameworkHeiko Stuebner2014-04-1510-1114/+41
| | | | | | | | | | | This converts the mentioned platforms to use the newly introduced driver for the common clock framework for them. With this the whole legacy clock structure can go away too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: dts: add clock data for s3c2416Heiko Stuebner2014-04-152-0/+55
| | | | | | | | | This adds the clock controller itself, the xti clock on the smdk2416 as well as the clock references in the individual device nodes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socsHeiko Stuebner2014-04-152-0/+6
| | | | | | | | | | | | | | | As the conversion to the common-clock-framework is done in multiple steps, it is necessary to prevent conflicts between the different struct clk implementations. For this include the s3c24xx_setup_clocks function only when SAMSUNG_CLOCK is selected and make the socs we don't convert this time explicitly depend on SAMSUNG_CLOCK, which gets only selected automatically if COMMON_CLK is not enabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450Heiko Stuebner2014-04-154-0/+561
| | | | | | | | | | | | | | | | | | The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* dt-bindings: add binding for clock-controller of s3c2443 and followingHeiko Stuebner2014-04-151-0/+56
| | | | | | | | | | Starting with the s3c2443 the s3c24xx series got a new clock tree compared to the previous s3c24xx socs. This binding describes the clock controller found in the s3c2443, s3c2416 and s3c2450 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add plls used by the s3c2443Heiko Stuebner2014-04-152-0/+74
| | | | | | | | | | The s3c2443 uses different plls that are not present yet. Therefore add the two needed types. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* clk: samsung: add pll_6552 variant for s3c2416Heiko Stuebner2014-04-152-2/+11
| | | | | | | | | | | | | | | | | | | According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553 and while the pll_6553 matches exactly the one already implemented the pll_6552 differs to the one from the s3c64xx series. The change is solely in the bit locations of the mdiv and pdiv values. All calculations are the same for both implementatons and even the proposed divider-values for specific frequencies in the manuals are the same. Therefore implement a variant that simply uses the changed bit locations if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Linux 3.15-rc1v3.15-rc1Linus Torvalds2014-04-131-2/+2
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* mm: Initialize error in shmem_file_aio_read()Geert Uytterhoeven2014-04-131-1/+1
| | | | | | | | | | | | | | | | | Some versions of gcc even warn about it: mm/shmem.c: In function ‘shmem_file_aio_read’: mm/shmem.c:1414: warning: ‘error’ may be used uninitialized in this function If the loop is aborted during the first iteration by one of the two first break statements, error will be uninitialized. Introduced by commit 6e58e79db8a1 ("introduce copy_page_to_iter, kill loop over iovec in generic_file_aio_read()"). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* cifs: Use min_t() when comparing "size_t" and "unsigned long"Geert Uytterhoeven2014-04-131-1/+1
| | | | | | | | | | | | | | | | On 32 bit, size_t is "unsigned int", not "unsigned long", causing the following warning when comparing with PAGE_SIZE, which is always "unsigned long": fs/cifs/file.c: In function ‘cifs_readdata_to_iov’: fs/cifs/file.c:2757: warning: comparison of distinct pointer types lacks a cast Introduced by commit 7f25bba819a3 ("cifs_iovec_read: keep iov_iter between the calls of cifs_readdata_to_iov()"), which changed the signedness of "remaining" and the code from min_t() to min(). Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'slab/next' of ↵Linus Torvalds2014-04-135-84/+128
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/penberg/linux Pull slab changes from Pekka Enberg: "The biggest change is byte-sized freelist indices which reduces slab freelist memory usage: https://lkml.org/lkml/2013/12/2/64" * 'slab/next' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/linux: mm: slab/slub: use page->list consistently instead of page->lru mm/slab.c: cleanup outdated comments and unify variables naming slab: fix wrongly used macro slub: fix high order page allocation problem with __GFP_NOFAIL slab: Make allocations with GFP_ZERO slightly more efficient slab: make more slab management structure off the slab slab: introduce byte sized index for the freelist of a slab slab: restrict the number of objects in a slab slab: introduce helper functions to get/set free object slab: factor out calculate nr objects in cache_estimate
| * mm: slab/slub: use page->list consistently instead of page->lruDave Hansen2014-04-113-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 'struct page' has two list_head fields: 'lru' and 'list'. Conveniently, they are unioned together. This means that code can use them interchangably, which gets horribly confusing like with this nugget from slab.c: > list_del(&page->lru); > if (page->active == cachep->num) > list_add(&page->list, &n->slabs_full); This patch makes the slab and slub code use page->lru universally instead of mixing ->list and ->lru. So, the new rule is: page->lru is what the you use if you want to keep your page on a list. Don't like the fact that it's not called ->list? Too bad. Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com> Acked-by: Christoph Lameter <cl@linux.com> Acked-by: David Rientjes <rientjes@google.com> Cc: Pekka Enberg <penberg@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Pekka Enberg <penberg@kernel.org>
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