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| * drm/i915: don't call intel_disable_pch_pll on Haswell/LPTPaulo Zanoni2012-11-111-1/+0
| * drm/i915: implement timing override workarounds on LPTPaulo Zanoni2012-11-111-0/+10
| * drm/i915: use CPU and PCH transcoders on lpt_disable_pch_transcoderPaulo Zanoni2012-11-111-10/+8
| * drm/i915: Add SURFLIVE register definitionsVille Syrjälä2012-11-111-0/+7
| * drm/i915: use PIPECONF_INTERLACE_MASK_HSW on lpt_enable_pch_transcoderPaulo Zanoni2012-11-111-1/+2
| * drm/i915: don't assert_pch_ports_disabled on LPTPaulo Zanoni2012-11-111-3/+0
| * drm/i915: don't rely on previous values when setting LPT TRANSCONFPaulo Zanoni2012-11-111-3/+2
| * drm/i915: use CPU and PCH transcoders on lpt_enable_pch_transcoderPaulo Zanoni2012-11-111-15/+9
| * drm/i915: don't assert_pch_pll_enabled on lpt_enable_pch_transcoderPaulo Zanoni2012-11-111-6/+0
| * drm/i915: remove IBX code from lpt_enable_pch_transcoderPaulo Zanoni2012-11-111-14/+1
| * drm/i915: remove Haswell code from ironlake_enable_pch_transcoderPaulo Zanoni2012-11-111-4/+0
| * drm/i915: fork lpt version of ironlake_{en, dis}able_pch_transcoderPaulo Zanoni2012-11-111-2/+75
| * drm/i915: rename intel_{en, dis}able_transcoderPaulo Zanoni2012-11-111-8/+8
| * drm/i915: use the CPU and PCH transcoders on lpt_pch_enablePaulo Zanoni2012-11-111-9/+10
| * drm/i915: don't assert_panel_unlocked on LPTPaulo Zanoni2012-11-111-2/+1
| * drm/i915: don't call ironlake_enable_pch_pll on lpt_pch_enablePaulo Zanoni2012-11-111-9/+0
| * drm/i915: rename intel_enable_pch_pll to ironlake_enable_pch_pllPaulo Zanoni2012-11-111-4/+4
| * drm/i915: remove ironlake bits from lpt_pch_enablePaulo Zanoni2012-11-111-68/+1
| * drm/i915: remove Haswell/LPT bits from ironlake_pch_enablePaulo Zanoni2012-11-111-6/+2
| * drm/i915: add lpt_pch_enablePaulo Zanoni2012-11-111-1/+110
| * drm/i915: use intel_ddi_get_hw_state on CRT encoder tooPaulo Zanoni2012-11-111-1/+4
| * drm/i915: don't set ADPA pipe select on LPTPaulo Zanoni2012-11-111-1/+3
| * drm/i915: move encoder->mode_set calls to crtc_mode_setDaniel Vetter2012-11-111-15/+15
| * drm/i915: Introduce intel_crtc_update_sarea_pos()Ville Syrjälä2012-11-111-15/+28
| * drm/i915: Bad pixel formats can't reach the sprite codeVille Syrjälä2012-11-111-6/+2
| * drm/i915: pixel_size == cppVille Syrjälä2012-11-111-16/+3
| * drm/i915: Check the framebuffer offsetVille Syrjälä2012-11-111-0/+4
| * drm/i915: Check framebuffer stride more thoroughlyVille Syrjälä2012-11-111-0/+8
| * drm/i915: Fix display pixel format handlingVille Syrjälä2012-11-112-37/+74
| * drm/i915: move more pte encoding to pte encodeBen Widawsky2012-11-111-29/+27
| * drm/i915: Extract PPGTT pte encodingBen Widawsky2012-11-111-5/+16
| * drm/i915: introduce gtt_pte_tBen Widawsky2012-11-111-6/+8
| * drm/i915: Add dev to ppgttBen Widawsky2012-11-112-2/+4
| * drm/i915: No LLC_MLC for HSW.Ben Widawsky2012-11-111-3/+7
| * drm/i915/ringbuffer: exclude last 2 cachelines on 845g on all callpathsMika Kuoppala2012-11-111-1/+1
| * drm/i915: create the DDI encoderPaulo Zanoni2012-11-114-100/+144
| * drm/i915: add intel_ddi_connector_get_hw_statePaulo Zanoni2012-11-114-2/+50
| * drm/i915: add port field to intel_digital_portPaulo Zanoni2012-11-114-26/+25
| * drm/i915: reset intel_encoder->type when DP or HDMI is detectedPaulo Zanoni2012-11-112-0/+8
| * drm/i915: split intel_dp_init into encoder and connector piecesPaulo Zanoni2012-11-111-57/+67
| * drm/i915: split intel_hdmi_init into encoder and connector piecesPaulo Zanoni2012-11-111-43/+53
| * drm/i915: create intel_digital_port and use itPaulo Zanoni2012-11-113-36/+78
| * drm/i915: add intel_dp_to_dev and intel_hdmi_to_devPaulo Zanoni2012-11-112-23/+34
| * drm/i915: simplify assignments inside intel_dp.cPaulo Zanoni2012-11-111-20/+21
| * drm/i915: Fix HSW power well control state readZhenyu Wang2012-11-111-1/+1
| * drm/i915: Flush using only the correct base address registerDamien Lespiau2012-11-111-2/+4
| * drm/i915: implement WaDisableRenderCachePipelinedFlushDaniel Vetter2012-11-112-0/+9
| * drm/i915: implement WaIssueDummyWriteToWakeupFromRC6Daniel Vetter2012-11-111-0/+13
| * drm/i915: adjust sprite base addressDamien Lespiau2012-11-113-27/+41
| * drm/i915: Fix sprite offset on HSWDamien Lespiau2012-11-112-1/+10
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