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* ARM: kprobes: Migrate ARM space_cccc_0110__1 to decoding tablesJon Medhurst2011-07-131-126/+91
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add emulate_rd12rn16rm0_rwflags_nopc()Jon Medhurst2011-07-131-0/+27
| | | | | | | | This is the emulation function for the instruction format used by the ARM media instructions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Migrate ARM space_cccc_001x to decoding tablesJon Medhurst2011-07-131-66/+50
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Migrate ARM space_cccc_000x to decoding tablesJon Medhurst2011-07-131-136/+116
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Migrate ARM LDRD and STRD to decoding tablesJon Medhurst2011-07-131-17/+20
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add emulate_ldrdstrd()Jon Medhurst2011-07-131-0/+29
| | | | | | | This is an emulation function for the LDRD and STRD instructions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Migrate ARM data-processing (register) instructions to ↵Jon Medhurst2011-07-131-48/+63
| | | | | | | decoding tables Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add emulate_rd12rn16rm0rs8_rwflags()Jon Medhurst2011-07-131-0/+35
| | | | | | | | This is the emulation function for the instruction format used by the ARM data-processing instructions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add BLX macroJon Medhurst2011-07-131-0/+7
| | | | | | | | | | This is for use by inline assembler which will be added to kprobes-arm.c It saves memory when used on newer ARM architectures and also provides correct interworking should ARM probes be required on Thumb kernels in the future. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add alu_write_pc()Jon Medhurst2011-07-132-0/+43
| | | | | | | | | | | | | | | | | | | This writes a new value to PC which was obtained as the result of an ARM ALU instruction. For ARMv7 and later this performs interworking. On ARM kernels we shouldn't encounter any ALU instructions trying to switch to Thumb mode so support for this isn't strictly necessary. However, the approach taken in all other instruction decoding is for us to avoid unpredictable modification of the PC for security reasons. This is usually achieved by rejecting insertion of probes on problematic instruction, but for ALU instructions we can't do this as it depends on the contents of the CPU registers at the time the probe is hit. So, as we require some form of run-time checking to trap undesirable PC modification, we may as well simulate the instructions correctly, i.e. in the way they would behave in the absence of a probe. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Migrate ARM space_1111 to decoding tablesJon Medhurst2011-07-131-31/+25
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb multiply and absolute difference instructionsJon Medhurst2011-07-131-0/+49
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb long multiply and divide instructionsJon Medhurst2011-07-131-0/+55
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb data-processing (register) instructionsJon Medhurst2011-07-131-0/+108
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb load/store single data item instructionsJon Medhurst2011-07-131-0/+153
| | | | | | | | We will reject probing of unprivileged load and store instructions. These rarely occur and writing test cases for them is difficult. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb memory hint instructionsJon Medhurst2011-07-131-0/+33
| | | | | | | | We'll treat the preload instructions as nops as they are just performance hints. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Reject 32-bit Thumb coprocessor and SIMD instructionsJon Medhurst2011-07-131-0/+16
| | | | | | | | | The kernel doesn't currently support VFP or Neon code, and probing of code with CP15 operations is fraught with bad consequences. So we will just reject probing these instructions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb branch instructionsJon Medhurst2011-07-131-2/+63
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit miscellaneous control instructionsJon Medhurst2011-07-131-0/+31
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb data-processing (plain binary immediate) ↵Jon Medhurst2011-07-131-0/+95
| | | | | | | instructions Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb data-processing (modified immediate) ↵Jon Medhurst2011-07-131-0/+58
| | | | | | | instructions Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb data-processing (shifted register) ↵Jon Medhurst2011-07-131-0/+93
| | | | | | | instructions Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb table branch instructionsJon Medhurst2011-07-131-0/+25
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb load/store dual and load/store exclusive ↵Jon Medhurst2011-07-131-0/+56
| | | | | | | | | | | | instructions We reject probing of load/store exclusive instructions because any emulation routine could never succeed in gaining exclusive access as the exception framework clears the exclusivity monitor when a probes breakpoint is hit. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb load/store multiple instructionsJon Medhurst2011-07-131-0/+48
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Optimise emulation of LDM and STMJon Medhurst2011-07-131-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch improves the performance of LDM and STM instruction emulation. This is desirable because. - jprobes and kretprobes probe the first instruction in a function and, when the frame pointer is omitted, this instruction is often a STM used to push registers onto the stack. - The STM and LDM instructions are common in the body and tail of functions. - At the same time as being a common instruction form, they also have one of the slowest and most complicated simulation routines. The approach taken to optimisation is to use emulation rather than simulation, that is, a modified form of the instruction is run with an appropriate register context. Benchmarking on an OMAP3530 shows the optimised emulation is between 2 and 3 times faster than the simulation routines. On a Kirkwood based device the relative performance was very significantly better than this. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add common decoding function for LDM and STMJon Medhurst2011-07-133-51/+80
| | | | | | | | | | | | | | | | | The encoding of these instructions is substantially the same for both ARM and Thumb, so we can have common decoding and simulation functions. This patch moves the simulation functions from kprobes-arm.c to kprobes-common.c. It also adds a new simulation function (simulate_ldm1_pc) for the case where we load into PC because this may need to interwork. The instruction decoding is done by a custom function (kprobe_decode_ldmstm) rather than just relying on decoding table entries because we will later be adding optimisation code. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add load_write_pc()Jon Medhurst2011-07-132-0/+39
| | | | | | | | | This writes a value to PC which was obtained as the result of a LDR or LDM instruction. For ARMv5T and later this must perform interworking. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 32-bit Thumb hint instructionsJon Medhurst2011-07-131-1/+27
| | | | | | | | | | | | | | For hints which may have observable effects, like SEV (send event), we use kprobe_emulate_none which emulates the hint by executing the original instruction. For NOP we simulate the instruction using kprobe_simulate_nop, which does nothing. As probes execute with interrupts disabled this is also used for hints which may block for an indefinite time, like WFE (wait for event). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Reject 16-bit Thumb SETEND, CPS and BKPT instructionsJon Medhurst2011-07-131-0/+4
| | | | | | | | | | | | | These are very rare and/or problematic to emulate so we will take the easy option and disallow probing them (as does the existing ARM implementation). Rejecting these instructions doesn't actually require any entries in the decoding table as it is the default case for instructions which aren't found. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb branch instructionsJon Medhurst2011-07-131-0/+38
| | | | | | | | | | | | | | | | We previously changed the behaviour of probes so that conditional instructions don't fire when the condition isn't met. For ARM branches, and Thumb branches in IT blocks, this means they don't fire if the branch isn't taken. For consistency, we implement the same for Thumb conditional branch instructions. This involves setting up insn_check_cc to point to the relevant condition checking function. As the emulation routine is only called when this condition passes, it doesn't need to check again and can unconditionally update PC. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Reject 16-bit Thumb SVC and UNDEFINED instructionsJon Medhurst2011-07-131-0/+8
| | | | | | | | SVC (SWI) instructions shouldn't occur in kernel code so we don't need to be able to probe them. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb IT instructionJon Medhurst2011-07-131-0/+33
| | | | | | | | | | The normal Thumb singlestepping routine updates the IT state after calling the instruction handler. We don't what this to happen after the IT instruction simulation sets the IT state, therefore we need to provide a custom singlestep routine. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb PUSH and POP instructionsJon Medhurst2011-07-131-0/+86
| | | | | | | | | | | | | | | | | | | These instructions are equivalent to stmdb sp!,{r0-r7,lr} ldmdb sp!,{r0-r7,pc} and we emulate them by transforming them into the 32-bit Thumb instructions stmdb r9!,{r0-r7,r8} ldmdb r9!,{r0-r7,r8} This is simpler, and almost certainly executes faster, than writing simulation functions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb CBZ and bit manipulation instructionsJon Medhurst2011-07-131-0/+29
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb PC- and SP-relative address instructionsJon Medhurst2011-07-131-0/+33
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb load and store instructionsJon Medhurst2011-07-131-0/+60
| | | | | | | | | | | Most of these instructions only operate on the low registers R0-R7 so they can make use of t16_emulate_loregs_rwflags. The instructions which use SP or PC for addressing have their own simulation functions. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb special data instructionsJon Medhurst2011-07-131-0/+49
| | | | | | | | | | | These data-processing instructions operate on the full range of CPU registers, so to simulate them we have to modify the registers used by the instruction. We can't make use of the decoding table framework to do this because the registers aren't encoded cleanly in separate nibbles, therefore we need a custom decode function. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb BX and BLX instructionsJon Medhurst2011-07-131-0/+37
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add bx_write_pc()Jon Medhurst2011-07-131-0/+14
| | | | | | | | This writes a value to PC, with interworking. I.e. switches to Thumb or ARM mode depending on the state of the least significant bit. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb data-processing instructionsJon Medhurst2011-07-131-0/+81
| | | | | | | | | | | | | | These instructions only operate on the low registers R0-R7, therefore it is possible to emulate them by executing the original instruction unaltered if we restore and save these registers. This is what t16_emulate_loregs does. Some of these instructions don't update the PSR when they execute in an IT block, so there are two flavours of emulation functions: t16_emulate_loregs_{noit}rwflags Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: ptrace: Add APSR_MASK definition to ptrace.hJon Medhurst2011-07-131-1/+2
| | | | | | | | | APSR_MASK can be used to extract the APSR bits from the CPSR. The comment for these definitions is also changed because it was inaccurate as the existing defines didn't refer to any part of the APSR. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Decode 16-bit Thumb hint instructionsJon Medhurst2011-07-133-1/+46
| | | | | | | | | | | | | | For hints which may have observable effects, like SEV (send event), we use kprobe_emulate_none which emulates the hint by executing the original instruction. For NOP we simulate the instruction using kprobe_simulate_nop, which does nothing. As probes execute with interrupts disabled this is also used for hints which may block for an indefinite time, like WFE (wait for event). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Infrastructure for table driven decoding of CPU instructionsJon Medhurst2011-07-132-1/+505
| | | | | | | | | | | | | | | | | | | | | | | The existing ARM instruction decoding functions are a mass of if/else code. Rather than follow this pattern for Thumb instruction decoding this patch implements an infrastructure for a new table driven scheme. This has several advantages: - Reduces the kernel size by approx 2kB. (The ARM instruction decoding will eventually have -3.1kB code, +1.3kB data; with similar or better estimated savings for Thumb decoding.) - Allows programmatic checking of decoding consistency and test case coverage. - Provides more uniform source code and is therefore, arguably, clearer. For a detailed explanation of how decoding tables work see the in-source documentation in kprobes.h, and also for kprobe_decode_insn(). Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Extend arch_specific_insn to add pointer to emulated instructionJon Medhurst2011-07-132-0/+7
| | | | | | | | | | | | | | When we come to emulating Thumb instructions then, to interwork correctly, the code on in the instruction slot must be invoked with a function pointer which has the least significant bit set. Rather that set this by hand in every Thumb emulation function we will add a new field for this purpose to arch_specific_insn, called insn_fn. This also enables us to seamlessly share emulation functions between ARM and Thumb code. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add hooks to override singlestep()Jon Medhurst2011-07-134-9/+31
| | | | | | | | | | | | | | | | | | When a probe fires we must single-step the instruction which was replaced by a breakpoint. As the steps to do this vary between ARM and Thumb instructions we need a way to customise single-stepping. This is done by adding a new hook called insn_singlestep to arch_specific_insn which is initialised by the instruction decoding functions. These single-step hooks must update PC and call the instruction handler. For Thumb instructions an additional step of updating ITSTATE is needed. We do this after calling the handler because some handlers will need to test if they are running in an IT block. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Use conditional breakpoints for ARM probesJon Medhurst2011-07-132-3/+9
| | | | | | | | | | | | | Now we no longer trigger probes on conditional instructions when the condition is false, we can make use of conditional instructions as breakpoints in ARM code to avoid taking unnecessary exceptions. Note, we can't rely on not getting an exception when the condition check fails, as that is Implementation Defined on newer ARM architectures. We therefore still need to perform manual condition checks as well. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Don't trigger probes on conditional instructions when ↵Jon Medhurst2011-07-131-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | condition is false This patch changes the behavior of kprobes on ARM so that: Kprobes on conditional instructions don't trigger when the condition is false. For conditional branches, this means that they don't trigger in the branch not taken case. Rationale: When probes are placed onto conditionally executed instructions in a Thumb IT block, they may not fire if the condition is not met. This is because we use invalid instructions for breakpoints and "it is IMPLEMENTATION DEFINED whether the instruction executes as a NOP or causes an Undefined Instruction exception". Therefore, for consistency, we will ignore all probes on any conditional instructions when the condition is false. Alternative solutions seem to be too complex to implement or inconsistent. This issue was discussed on linux.arm.kernel in the thread titled "[RFC] kprobes with thumb2 conditional code" See http://comments.gmane.org/gmane.linux.linaro.devel/2985 Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add it_advance()Jon Medhurst2011-07-131-0/+25
| | | | | | | | This advances the ITSTATE bits in CPSR to their values for the next instruction. Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
* ARM: kprobes: Add condition code checking to Thumb emulationJon Medhurst2011-07-131-0/+22
| | | | | Signed-off-by: Jon Medhurst <tixy@yxit.co.uk> Acked-by: Nicolas Pitre <nicolas.pitre@linaro.org>
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