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* gpu: host1x: Increase compile test coverageThierry Reding2013-12-191-1/+1
| | | | | | | | | | The ARCH_MULTIPLATFORM dependency was introduced back when Tegra didn't support multiplatform yet as a means to allow the driver to be easily compile-tested along with other DRM drivers. In the meantime, the new COMPILE_TEST Kconfig option has been introduced for exactly that purpose, so use that instead to clarify the intention. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix more sparse warningsThierry Reding2013-12-191-0/+3
| | | | | | | | Include the linux/host1x.h and dev.h headers so that function prototypes are visible to keep sparse from suggesting that their implementations be made static. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Use the correct HW headers for host1x02Thierry Reding2013-12-193-2/+150
| | | | | | | An earlier patch added a subset of the required HW specific header files but didn't actually include the right ones when compiling for host1x02. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Export public APIThierry Reding2013-12-194-0/+22
| | | | | | | Make the public API symbols visible so that depending drivers can be built as a module. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add MIPI pad calibration supportThierry Reding2013-12-195-4/+294
| | | | | | | This driver adds support to perform calibration of the MIPI pads for CSI and DSI. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add MIPI pad calibration DT bindingsThierry Reding2013-12-171-0/+41
| | | | | | | | Introduce device tree bindings for the MIPI pad calibration controller found on Tegra SoCs. The controller can be used to perform calibration of pads used for DSI and CSI peripherals. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Update host1x device tree exampleThierry Reding2013-12-171-2/+2
| | | | | | | The display controller primary clock was recently renamed to "dc", so update the example to reflect that. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Implement panel supportThierry Reding2013-12-174-4/+38
| | | | | | | | | Use the DRM panel framework to attach a panel to an output. If the panel attached to a connector supports supports the backlight brightness accessors, a property will be available to allow the brightness to be modified from userspace. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/panel: Add support for Panasonic VVX10F004B0Thierry Reding2013-12-171-7/+87
| | | | | | | The Panasonic VVX10F004B0 is a 10.1" WUXGA TFT LCD panel connected using four DSI lanes. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/panel: Add simple panel supportThierry Reding2013-12-174-0/+433
| | | | | | | | | | | | | Add a driver for simple panels. Such panels can have a regulator that provides the supply voltage and a separate GPIO to enable the panel. Optionally the panels can have a backlight associated with them so it can be enabled or disabled according to the panel's power management mode. Support is added for two panels: An AU Optronics 10.1" WSVGA and a Chunghwa Picture Tubes 10.1" WXGA panel. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm: Add panel supportThierry Reding2013-12-175-0/+190
| | | | | | | | | | | | | | | | | | | | | Add a very simple framework to register and lookup panels. Panel drivers can initialize a DRM panel and register it with the framework, allowing them to be retrieved and used by display drivers. Currently only support for DPMS and obtaining panel modes is provided. However it should be sufficient to enable a large number of panels. The framework should also be easily extensible to support more sophisticated kinds of panels such as DSI. The framework hasn't been tied into the DRM core, even though it should be easily possible to do so if that's what we want. In the current implementation, display drivers can simple make use of it to retrieve a panel, obtain its modes and control its DPMS mode. Note that this is currently only tested on systems that boot from a device tree. No glue code has been written yet for systems that use platform data, but it should be easy to add. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm: Add MIPI DSI bus supportAndrzej Hajda2013-12-174-0/+478
| | | | | | | | | | | | | | | MIPI DSI bus allows to model DSI hosts and DSI peripherals using the Linux driver model. DSI hosts are registered by the DSI host drivers. During registration DSI peripherals will be created from the children of the DSI host's device tree node. Support for registration from board-setup code will be added later when needed. DSI hosts expose operations which can be used by DSI peripheral drivers to access associated devices. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* of: Add simple panel device tree bindingThierry Reding2013-12-174-0/+42
| | | | | | | | | | | This binding specifies a set of common properties for display panels. It can be used as a basis by bindings for specific panels. Bindings for three specific panels are provided to show how the simple panel binding can be used. Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* of: Add MIPI DSI bus device tree bindingsThierry Reding2013-12-171-0/+98
| | | | | | | | Document the device tree bindings for the MIPI DSI bus. The MIPI Display Serial Interface specifies a serial bus and a protocol for communication between a host and up to four peripherals. Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'tegra-for-3.14-powergate' into drm/for-nextThierry Reding2013-12-172-3/+240
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM: tegra: powergate driver changes This branch includes all the changes to Tegra's powergate driver for 3.14. These are separate out, since the Tegra DRM changes for 3.14 rely on the new APIs introduced here. A few cleanups and fixes are included, plus additions of Tegra124 SoC support, and a new API for manipulating Tegra's IO rail deep power down states. This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order to avoid conflicts with the addition of common reset controller support to the powergate driver.
| * ARM: tegra: Add IO rail supportThierry Reding2013-12-162-0/+177
| | | | | | | | | | | | | | | | Add tegra_io_rail_power_off() and tegra_io_rail_power_on() functions to put IO rails into or out of deep powerdown mode, respectively. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Special-case the 3D clamps on Tegra124Thierry Reding2013-12-161-0/+13
| | | | | | | | | | | | | | | | | | A separate register is used to remove the clamps for the GPU on Tegra124. In order to be able to use the same API, special-case this particular partition. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Add Tegra124 powergate supportThierry Reding2013-12-162-0/+45
| | | | | | | | | | | | | | | | | | Three new gates have been added for Tegra124: SOR, VIC and IRAM. In addition, PCIe and SATA gates are again supported, like on Tegra20 and Tegra30. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Export tegra_powergate_remove_clamping()Thierry Reding2013-12-161-0/+1
| | | | | | | | | | | | | | | | | | Drivers can use the tegra_powergate_remove_clamping() API during initialization. In order to allow such drivers to be built as modules, export the symbol. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Export tegra_powergate_power_off()Thierry Reding2013-12-161-0/+1
| | | | | | | | | | | | | | | | This function can be used by drivers, which in turn may be built as modules. Export the symbol so it is available to modules. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Rename cpu0 powergate to crailThierry Reding2013-12-161-1/+1
| | | | | | | | | | | | | | This matches the name of the powergate as listed in the TRM. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ARM: tegra: Fix some whitespace odditiesThierry Reding2013-12-161-2/+2
| | | | | | | | | | | | | | | | Some of the powergate code uses unusual spacing around == and has a tab instead of a space before an opening parenthesis. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* | Merge tag 'tegra-for-3.14-dmas-resets-rework' into drm/for-nextThierry Reding2013-12-1791-3569/+6603
|\ \ | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM: tegra: implement common DMA and resets DT bindings This series converts the Tegra DTs and drivers to use the common/ standard DMA and reset bindings, rather than custom bindings. It also adds complete documentation for the Tegra clock bindings without actually changing any binding definitions. This conversion relies on a few sets of patches in branches from outside the Tegra tree: 1) A patch to add an DMA channel request API which allows deferred probe to be implemented. 2) A patch to implement a common part of the of_xlate function for DMA controllers. 3) Some ASoC patches (which in turn rely on (1) above), which support deferred probe during DMA channel allocation. 4) The Tegra clock driver changes for 3.14. Consequently, this branch is based on a merge of all of those external branches. In turn, this branch is or will be pulled into a few places that either rely on features introduced here, or would otherwise conflict with the patches: a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid conflicts. b) The DRM tree, which introduces new code that relies on the reset controller framework introduced in this branch, and to avoid conflicts.
| * spi: tegra: checking for ERR_PTR instead of NULLDan Carpenter2013-12-161-2/+2
| | | | | | | | | | | | | | | | | | | | dma_request_slave_channel() returns NULL on error and not ERR_PTRs. I've fixed this by using dma_request_slave_channel_reason() which does return ERR_PTRs. Fixes: a915d150f68d ('spi: tegra: convert to standard DMA DT bindings') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
| * ASoC: tegra: update module reset list for Tegra124Stephen Warren2013-12-122-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra124 adds a number of extra modules into the configlink bus, which must be taken out of reset before the bus is used. Update the AHUB driver to know about these extra modules (the AHUB HW module hosts the configlink bus). Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com> Based-on-work-by: Songhee Baek <sbaek@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> --- This patch depends on "ASoC: tegra: use reset framework" to compile, which is ack'd and slated to go through a (large) topic branch in the Tegra tree. So, we can either: a) Merge that Tegra topic branch into the ASoC tree, then apply this. Note that I haven't created the topic branch yet, since I'm still waiting for DMA dependencies to be applied. b) Apply this change to the Tegra tree too. This change isn't directly related to the changes in the Tegra tree; it just makes use of the new reset controller feature that's introduced there.
| * clk: tegra: remove bogus PCIE_XCLKStephen Warren2013-12-114-15/+2
| | | | | | | | | | | | | | | | | | | | | | The "pcie_xclk" clock is not actually a clock at all, but rather a reset domain. Now that the custom Tegra module reset API has been removed, we can remove the definition of any "clocks" that existed solely to support it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * clk: tegra: remove legacy reset APIsStephen Warren2013-12-114-70/+0
| | | | | | | | | | | | | | | | | | Now that no code uses the custom Tegra module reset API, we can remove its implementation. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * ARM: tegra: remove legacy DMA entries from DTStephen Warren2013-12-113-39/+0
| | | | | | | | | | | | | | | | | | Now that all Tegra drivers have been converted to use DMA APIs which retrieve DMA channel information from standard DMA DT properties, we can remove all the legacy DT DMA-related properties. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: remove legacy clock entries from DTStephen Warren2013-12-113-32/+6
| | | | | | | | | | | | | | | | | | Now that all Tegra drivers have been converted to use the common reset framework, we can remove all the legacy DT clocks/clock-names entries for "clocks" that were only used with the old custom Tegra module reset API. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * USB: EHCI: tegra: use reset frameworkStephen Warren2013-12-111-3/+11
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * Input: tegra-kbc - use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * serial: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-111-18/+6
| | | | | | | | | | | | | | | | | | | | | | By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * serial: tegra: use reset frameworkStephen Warren2013-12-111-4/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * spi: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-112-62/+34
| | | | | | | | | | | | | | | | | | | | By using dma_request_slave_channel_or_err(), the DMA slave ID can be looked up from standard DT properties, and squirrelled away during channel allocation. Hence, there's no need to use a custom DT property to store the slave ID. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * spi: tegra: use reset frameworkStephen Warren2013-12-114-15/+42
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * staging: nvec: use reset frameworkStephen Warren2013-12-112-4/+12
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Marc Dietrich <marvin24@gmx.de> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * i2c: tegra: use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ASoC: tegra: convert to standard DMA DT bindingsStephen Warren2013-12-118-60/+42
| | | | | | | | | | | | | | | | | | | | | | | | By passing no flags when calling snd_dmaengine_pcm_register() from tegra_pcm.c, we end up using dma_request_slave_channel() rather than dmaengine_pcm_compat_request_channel(), and hence rely on the standard DMA DT bindings and stashing the DMA slave ID away during channel allocation. This means there's no need to use a custom DT property to store the slave ID. So, remove all the code that parsed it. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: allocate AHUB FIFO during probe() not startup()Stephen Warren2013-12-111-44/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra30 I2S driver currently allocates DMA FIFOs from the AHUB only when an audio stream starts playback. This is theoretically nice for resource sharing, but makes no practical difference for any configuration the drivers currently support. However, this deferral prevents conversion to the standard DMA DT bindings, since conversion requires knowledge of the specific DMA channel to be allocated, which in turn depends on which specific FIFO was allocated. For this reason, move the FIFO allocation into probe() to allow later conversion to the standard DMA DT bindings. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: call pm_runtime APIs around register accessesStephen Warren2013-12-111-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Call pm_runtime_get_sync() before all register accesses; the HW requires clocks to be running when accessing registers. This hasn't been needed to date, since all register IO was performed while playback was active, and hence the ASoC core had already called pm_runtime_get(). However, an imminent future commit will allocate and set up the FIFOs and routing during probe(), when that "protection" won't be in place. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org>
| * ASoC: tegra: use reset frameworkStephen Warren2013-12-113-34/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. This change also renames "clock"/"clk" to "modules"/"mod" in symbols related to entries in configlink_clocks[], since: - We don't care about clock handles any more, but rather reset handles, so the old name isn't applicable. - It really is a list of modules on the bus, about which we currently only care about reset handles. If we start caring about any other aspect of the modules in the future, we won't have to rename all these symbols again. Note: The addition of "depends COMMON_CLOCK" is something that was missing before, not a new requirement. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Mark Brown <broonie@linaro.org> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * dma: tegra: register as an OF DMA controllerStephen Warren2013-12-111-3/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | Call of_dma_controller_register() so that DMA clients can look up the Tegra DMA controller using standard APIs. This requires the of_xlate() function to save off the DMA slave ID, and for tegra_dma_slave_config() not to over-write this information; once DMA client drivers are converted to dma_request_slave_channel() and DT-based lookups, they won't set this field of struct dma_slave_config anymore. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * dma: tegra: use reset frameworkStephen Warren2013-12-111-3/+10
| | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Dan Williams <dan.j.williams@intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com>
| * ARM: tegra: pass reset to tegra_powergate_sequence_power_up()Stephen Warren2013-12-114-8/+16
| | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * drm/tegra: use reset frameworkStephen Warren2013-12-115-6/+39
| | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
| * pci: tegra: use reset frameworkStephen Warren2013-12-111-14/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra's clock driver now provides an implementation of the common reset API (include/linux/reset.h). Use this instead of the old Tegra- specific API; that will soon be removed. The old Tegra-specific API used a struct clock to represent the module to reset. Some of the clocks retrieved during probe() were only used for reset purposes, and indeed aren't even true clocks. So, there's no need to get() them any more. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: implement a reset driverStephen Warren2013-12-116-6/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | The Tegra CAR module implements both a clock and reset controller. So far, the driver exposes the clock feature via the common clock API and the reset feature using a custom API. This patch adds an implementation of the common reset framework API (include/linux/reset*.h). The legacy reset implementation will be removed once all drivers have been converted. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
| * ARM: tegra: select the reset frameworkStephen Warren2013-12-111-0/+2
| | | | | | | | | | | | | | | | | | The Tegra clock driver is built unconditionally when Tegra support is enabled. In order to avoid having to ifdef the forthcoming reset driver implementation, have ARCH_TEGRA select RESET_CONTROLLER. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: update DT files to add DMA propertiesStephen Warren2013-12-113-0/+119
| | | | | | | | | | | | | | | | | | This patch switches the Tegra DT files to use the standard DMA DT bindings rather than custom properties. Note that the legacy properties are not yet removed; the drivers must be updated to use the new properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <treding@nvidia.com>
| * ARM: tegra: update DT files to add reset propertiesStephen Warren2013-12-114-4/+266
| | | | | | | | | | | | | | | | | | | | | | | | An earlier patch updated the Tegra DT bindings to require resets and reset-names properties to be filled in. This patch updates the DT files to include those properties. Note that any legacy clocks and clock-names entries that are replaced by reset properties are not yet removed; the drivers must be updated to use the new resets and reset-names properties first. Signed-off-by: Stephen Warren <swarren@nvidia.com>
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