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* unicore32 machine related files: add i2c bus drivers for pkunity-v3 socGuanXuetao2011-03-175-0/+323
| | | | | | | | | | | | | | change from original version -- by advice of Jean Delvare 1. remove global variable i2c_reg, replaced by local variables 2. replace ENXIO with ENODEV when no platform resources 3. add adapter->nr assignment before i2c_add_numbered_adapter() call 4. add judgement for i2c_del_adapter() return value 5. release adapter when driver removed 6. add __devexit for puv3_i2c_remove() function 7. modify several names to more appropriated ones Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 io: redefine __REG(x) and re-use readl/writel funcsGuanXuetao2011-03-1713-164/+171
| | | | | | | -- by advice of Arnd Bergmann Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 i8042 upgrade and bugfix: adjust resource request region typeGuanXuetao2011-03-171-2/+2
| | | | Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 upgrade to v2.6.38-rc5: add one more paramter for pte_alloc_map callGuanXuetao2011-03-171-1/+1
| | | | Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 i8042: adjust io funcs of i8042-unicore32io.hGuanXuetao2011-03-171-9/+12
| | | | | | | | replace inb/outb with readb/writeb in i8042-unicore32io.h and correct typecasting of register and region macros -- by advice with Arnd Bergmann Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32: rename PKUNITY_IOSPACE_BASE to PKUNITY_MMIO_BASEGuanXuetao2011-03-172-3/+3
| | | | | | | for the term IOSPACE normally refers to the PCI PIO space -- by advice with Arnd Bergmann Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32: modify function names and parameters for irq_chipsGuanXuetao2011-03-172-41/+42
| | | | | | -- by advice with Thomas Gleixner Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32: remove unused lines in arch/unicore32/include/asm/irq.hGuanXuetao2011-03-171-2/+0
| | | | Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 time.c: change calculate method for clock_event_deviceGuanXuetao2011-03-171-7/+2
| | | | | | | | apply clockevents_calc_mult_shift() to get rid of shift assignment and mult calculation for osmr0 -- by advice with Thomas Gleixner Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32: ADD MAINTAINER for unicore32 architectureGuanXuetao2011-03-171-0/+14
| | | | | | | Add MAINTAINER list for unicore32 architecture and pkunity soc drivers. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 machine related files: ps2 driverGuanXuetao2011-03-172-0/+72
| | | | | | | | | | | | This patch implements arch-specific ps2 driver. By reviewed with Dmitry Torokhov: 1. move i8042-ucio.h to drivers/input/serio/i8042-unicore32io.h 2. move puv3_ps2_init() to arch/unicore32/kernel/puv3-core.c 3. remove unused comments. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Dmitry Torokhov <dtor@mail.ru>
* unicore32 machine related files: pci bus handlingGuanXuetao2011-03-173-0/+451
| | | | | | This patch implements arch-specific pci bus driver. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 machine related files: hardware registersGuanXuetao2011-03-1720-0/+1615
| | | | | | This patch adds all hardware registers definitions. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 machine related files: core filesGuanXuetao2011-03-173-0/+440
| | | | | | | This patch adds machine related core files, also including build infrastructure. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: boot processGuanXuetao2011-03-177-0/+546
| | | | | | | This patch implements booting process, including uncompression process. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: low-level lib: miscGuanXuetao2011-03-1710-0/+662
| | | | | | | This patch implements the rest low-level libraries. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: low-level lib: uaccessGuanXuetao2011-03-178-0/+648
| | | | | | | This patch implements low-level uaccess libraries. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: low-level lib: ocd debugGuanXuetao2011-03-174-0/+269
| | | | | | | This patch implements low-level debug libraries with On-Chip-Debugger hardware support. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: ptrace handlingGuanXuetao2011-03-172-0/+282
| | | | | | | | | | | | This patch adds ptrace support. Changed from previous version: 1. disable arch_has_single_step and remove single-step instruction handler 2. add 'Ross Biro 1/23/92' contributor information 3. clean unused codes Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: float point handlingGuanXuetao2011-03-173-0/+205
| | | | | | | | This patch implements support for float point unit, which using UniCore-F64 FPU hardware in UniCore32 ISA. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 additional architecture files: pm related filesGuanXuetao2011-03-178-0/+1156
| | | | | | | This patch adds pm related files, including hibernate and sleep supports. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: signals handlingGuanXuetao2011-03-172-0/+523
| | | | | | This patch implements signals. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 core architecture: interrupts ang gpio handlingGuanXuetao2011-03-175-0/+811
| | | | | | | | This patch implements interrupts and gpio handling. UniCore32 has 9 gpio interrupt sources. And gpio device operations are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 core architecture: timer and time handlingGuanXuetao2011-03-174-0/+825
| | | | | | | This patch implements timer and time. RTC and PWM device drivers are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn>
* unicore32 core architecture: mm related: consistent device DMA handlingGuanXuetao2011-03-1710-0/+1207
| | | | | | | | This patch implements consistent device DMA handling of memory management. DMA device operations are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: mm related: fault handlingGuanXuetao2011-03-1710-0/+2247
| | | | | | | This patch implements fault handling of memory management. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: mm related: generic codesGuanXuetao2011-03-1713-0/+1390
| | | | | | | This patch includes generic codes for memory management. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: process/thread related codesGuanXuetao2011-03-176-0/+912
| | | | | | | This patch implements process/thread related codes. Backtrace and stacktrace are here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: low level entry and setup codesGuanXuetao2011-03-176-0/+1820
| | | | | | | This patch implements low level entry and setup codes. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: processor and system headersGuanXuetao2011-03-1710-0/+810
| | | | | | | | This patch includes processor and system headers. System call interface is here. We used the syscall interface the same as asm-generic version. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: generic elf and ksyms stuffGuanXuetao2011-03-178-0/+571
| | | | | | | | | | This patch includes some generic stuff including elf and ksyms. Because all one-line asm-generic headers are auto-generated by ASM_GENERIC_HEADERS in arch/unicore32/Makefile, so the rest seems very little. ELF handling functions and module handling functions are also here. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* unicore32 core architecture: build infrastructureGuanXuetao2011-03-179-0/+758
| | | | | | | This patch implements build infrastructure. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* asm-generic headers: add arch-specific __strnlen_user calling in uaccess.hGuanXuetao2011-03-171-3/+5
| | | | | | | | | | This patch changes the implementation of strnlen_user in include/asm-generic/uaccess.h. Originally, it calls strlen() function directly, which may not correctly handle the access of user space in most mmu-enabled architectures. New __strnlen_user is added for using as an architecture specific function. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
* asm-generic headers: add ftrace.hGuanXuetao2011-03-171-0/+16
| | | | | | | | This patch adds ftrace.h into asm-generic headers. The file content could be empty in most architectures. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* asm-generic headers: add sizes.hGuanXuetao2011-03-171-0/+47
| | | | | | | | This patch adds sizes.h into asm-generic headers. Only 32-bit version supported. Signed-off-by: Guan Xuetao <gxt@mprc.pku.edu.cn> Acked-by: Arnd Bergmann <arnd@arndb.de>
* asm-generic: fix inX/outX functions for architectures that have PCIGuanXuetao2011-03-171-14/+19
| | | | | | | | | | The definitions for the PC-style PIO functions in asm-generic/io.h were meant as dummies so you could compile code on architectures without ISA and PCI buses. However, unicore32 actually wants to use them with a real PCI bus, so they need to be defined to actually address the register window holding the I/O ports. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* Linux 2.6.38v2.6.38Linus Torvalds2011-03-141-1/+1
|
* Merge branch 'fixes' of ↵Linus Torvalds2011-03-143-5/+6
|\ | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300 * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-2.6-mn10300: MN10300: atomic_read() should ensure it emits a load MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not exist MN10300: Proper use of macros get_user() in the case of incremented pointers
| * MN10300: atomic_read() should ensure it emits a loadDavid Howells2011-03-141-1/+1
| | | | | | | | | | | | | | | | atomic_read() needs to ensure that it emits a load (which it can do by using ACCESS_ONCE()). Reported-by: Peter Zijlstra <peterz@infradead.org> Signed-off-by: David Howells <dhowells@redhat.com>
| * MN10300: The SMP_ICACHE_INV_FLUSH_RANGE IPI command does not existDavid Howells2011-03-141-2/+2
| | | | | | | | | | | | | | | | The invalidate-only versions of flush_icache_*range() are trying sending the SMP_ICACHE_INV_FLUSH_RANGE IPI command in SMP kernels when they should be sending SMP_ICACHE_INV_RANGE as the former does not exist. Signed-off-by: David Howells <dhowells@redhat.com>
| * MN10300: Proper use of macros get_user() in the case of incremented pointersTkhai Kirill2011-03-141-2/+3
| | | | | | | | | | | | | | | | | | | | Using __get_user_check(x, ptr++, size) leads to double increment of pointer. This macro uses the macro get_user directly, which itself is used in this way (get_user(x, ptr++)) in some functions of the kernel. The patch fixes the error. Reported-by: Tkhai Kirill <tkhai@yandex.ru> Signed-off-by: David Howells <dhowells@redhat.com>
* | Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linusLinus Torvalds2011-03-1422-305/+331
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * 'upstream' of git://git.linux-mips.org/pub/scm/upstream-linus: (26 commits) MIPS: Alchemy: Fix reset for MTX-1 and XXS1500 MIPS: MTX-1: Make au1000_eth probe all PHY addresses MIPS: Jz4740: Add HAVE_CLK MIPS: Move idle task creation to work queue MIPS, Perf-events: Use unsigned delta for right shift in event update MIPS, Perf-events: Work with the new callchain interface MIPS, Perf-events: Fix event check in validate_event() MIPS, Perf-events: Work with the new PMU interface MIPS, Perf-events: Work with irq_work MIPS: Fix always CONFIG_LOONGSON_UART_BASE=y MIPS: Loongson: Fix potentially wrong string handling MIPS: Fix GCC-4.6 'set but not used' warning in arch/mips/mm/init.c MIPS: Fix GCC-4.6 'set but not used' warning in ieee754int.h MIPS: Remove unused code from arch/mips/kernel/syscall.c MIPS: Fix GCC-4.6 'set but not used' warning in signal*.c MIPS: MSP: Fix MSP71xx bpci interrupt handler return value MIPS: Select R4K timer lib for all MSP platforms MIPS: Loongson: Remove ad-hoc cmdline default MIPS: Clear the correct flag in sysmips(MIPS_FIXADE, ...). MIPS: Add an unreachable return statement to satisfy buggy GCCs. ...
| * | MIPS: Alchemy: Fix reset for MTX-1 and XXS1500Florian Fainelli2011-03-142-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 32fd6901 (MIPS: Alchemy: get rid of common/reset.c) Alchemy-based boards use their own reset function. For MTX-1 and XXS1500, the reset function pokes at the BCSR.SYSTEM_RESET register, but this does not work. According to Bruno Randolf, this was not tested when written. Previously, the generic au1000_restart() routine called the board specific reset function, which for MTX-1 and XXS1500 did not work, but finally made a jump to the reset vector, which really triggers a system restart. Fix reboot for both targets by jumping to the reset vector. Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2093/ Acked-by: Bruno Randolf <br1@einfach.org> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: MTX-1: Make au1000_eth probe all PHY addressesFlorian Fainelli2011-03-141-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When au1000_eth probes the MII bus for PHY address, if we do not set au1000_eth platform data's phy_search_highest_address, the MII probing logic will exit early and will assume a valid PHY is found at address 0. For MTX-1, the PHY is at address 31, and without this patch, the link detection/speed/duplex would not work correctly. CC: stable@kernel.org Signed-off-by: Florian Fainelli <florian@openwrt.org> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2111/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Jz4740: Add HAVE_CLKMaurus Cuelenaere2011-03-141-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jz4740 supports the clock framework but doesn't have HAVE_CLK defined, so define it! Signed-off-by: Maurus Cuelenaere <mcuelenaere@gmail.com> To: linux-mips@linux-mips.org To: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2112/ Acked-by: Lars-Peter Clausen <lars@metafoo.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS: Move idle task creation to work queueMaksim Rayskiy2011-03-141-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To avoid forking usermode thread when creating an idle task, move fork_idle to a work queue. If kernel starts with maxcpus= option which does not bring all available cpus online at boot time, idle tasks for offline cpus are not created. If later offline cpus are hotplugged through sysfs, __cpu_up is called in the context of the user task, and fork_idle copies its non-zero mm pointer. This causes BUG() in per_cpu_trap_init. This also avoids issues with resource limits of the CPU writing to sysfs, containers, maybe others. Signed-off-by: Maksim Rayskiy <mrayskiy@broadcom.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2070/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS, Perf-events: Use unsigned delta for right shift in event updateDeng-Cheng Zhu2011-03-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Leverage the commit for ARM by Will Deacon: - 446a5a8b1eb91a6990e5c8fe29f14e7a95b69132 ARM: 6205/1: perf: ensure counter delta is treated as unsigned Hardware performance counters on ARM are 32-bits wide but atomic64_t variables are used to represent counter data in the hw_perf_event structure. The armpmu_event_update function right-shifts a signed 64-bit delta variable and adds the result to the event count. This can lead to shifting in sign-bits if the MSB of the 32-bit counter value is set. This results in perf output such as: Performance counter stats for 'sleep 20': 18446744073460670464 cycles <-- 0xFFFFFFFFF12A6000 7783773 instructions # 0.000 IPC 465 context-switches 161 page-faults 1172393 branches 20.154242147 seconds time elapsed This patch ensures that the delta value is treated as unsigned so that the right shift sets the upper bits to zero. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: fweisbec@gmail.com To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/2015/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS, Perf-events: Work with the new callchain interfaceDeng-Cheng Zhu2011-03-141-57/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the MIPS part of the following commits by Frederic Weisbecker: - f72c1a931e311bb7780fee19e41a89ac42cab50e perf: Factorize callchain context handling Store the kernel and user contexts from the generic layer instead of archs, this gathers some repetitive code. - 56962b4449af34070bb1994621ef4f0265eed4d8 perf: Generalize some arch callchain code - Most archs use one callchain buffer per cpu, except x86 that needs to deal with NMIs. Provide a default perf_callchain_buffer() implementation that x86 overrides. - Centralize all the kernel/user regs handling and invoke new arch handlers from there: perf_callchain_user() / perf_callchain_kernel() That avoid all the user_mode(), current->mm checks and so... - Invert some parameters in perf_callchain_*() helpers: entry to the left, regs to the right, following the traditional (dst, src). - 70791ce9ba68a5921c9905ef05d23f62a90bc10c perf: Generalize callchain_store() callchain_store() is the same on every archs, inline it in perf_event.h and rename it to perf_callchain_store() to avoid any collision. This removes repetitive code. - c1a65932fd7216fdc9a0db8bbffe1d47842f862c perf: Drop unappropriate tests on arch callchains Drop the TASK_RUNNING test on user tasks for callchains as this check doesn't seem to make any sense. Also remove the tests for !current that is not supposed to happen and current->pid as this should be handled at the generic level, with exclude_idle attribute. Reported-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: Frederic Weisbecker <fweisbec@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: dengcheng.zhu@gmail.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/2014/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS, Perf-events: Fix event check in validate_event()Deng-Cheng Zhu2011-03-141-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Ignore events that are in off/error state or belong to a different PMU. This patch originates from the following commit for ARM by Will Deacon: - 65b4711ff513767341aa1915c822de6ec0de65cb ARM: 6352/1: perf: fix event validation The validate_event function in the ARM perf events backend has the following problems: 1.) Events that are disabled count towards the cost. 2.) Events associated with other PMUs [for example, software events or breakpoints] do not count towards the cost, but do fail validation, causing the group to fail. This patch changes validate_event so that it ignores events in the PERF_EVENT_STATE_OFF state or that are scheduled for other PMUs. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: fweisbec@gmail.com To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: dengcheng.zhu@gmail.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Cc: ddaney@caviumnetworks.com Patchwork: http://patchwork.linux-mips.org/patch/2013/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| * | MIPS, Perf-events: Work with the new PMU interfaceDeng-Cheng Zhu2011-03-142-119/+158
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the MIPS part of the following commits by Peter Zijlstra: - a4eaf7f14675cb512d69f0c928055e73d0c6d252 perf: Rework the PMU methods Replace pmu::{enable,disable,start,stop,unthrottle} with pmu::{add,del,start,stop}, all of which take a flags argument. The new interface extends the capability to stop a counter while keeping it scheduled on the PMU. We replace the throttled state with the generic stopped state. This also allows us to efficiently stop/start counters over certain code paths (like IRQ handlers). It also allows scheduling a counter without it starting, allowing for a generic frozen state (useful for rotating stopped counters). The stopped state is implemented in two different ways, depending on how the architecture implemented the throttled state: 1) We disable the counter: a) the pmu has per-counter enable bits, we flip that b) we program a NOP event, preserving the counter state 2) We store the counter state and ignore all read/overflow events For MIPSXX, the stopped state is implemented in the way of 1.b as above. - 33696fc0d141bbbcb12f75b69608ea83282e3117 perf: Per PMU disable Changes perf_disable() into perf_pmu_disable(). - 24cd7f54a0d47e1d5b3de29e2456bfbd2d8447b7 perf: Reduce perf_disable() usage Since the current perf_disable() usage is only an optimization, remove it for now. This eases the removal of the __weak hw_perf_enable() interface. - b0a873ebbf87bf38bf70b5e39a7cadc96099fa13 perf: Register PMU implementations Simple registration interface for struct pmu, this provides the infrastructure for removing all the weak functions. - 51b0fe39549a04858001922919ab355dee9bdfcf perf: Deconstify struct pmu sed -ie 's/const struct pmu\>/struct pmu/g' `git grep -l "const struct pmu\>"` Reported-by: Wu Zhangjin <wuzhangjin@gmail.com> Acked-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@gmail.com> To: a.p.zijlstra@chello.nl To: fweisbec@gmail.com To: will.deacon@arm.com Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Cc: wuzhangjin@gmail.com Cc: paulus@samba.org Cc: mingo@elte.hu Cc: acme@redhat.com Cc: dengcheng.zhu@gmail.com Cc: matt@console-pimps.org Cc: sshtylyov@mvista.com Cc: ddaney@caviumnetworks.com Patchwork: http://patchwork.linux-mips.org/patch/2012/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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