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* clk: gate: add CLK_GATE_HIWORD_MASKHaojian Zhuang2013-06-152-6/+24
| | | | | | | | | | | | | | | In Rockchip Cortex-A9 based chips, they don't use paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b1 should be set as gate, it also needs to indicate the change by setting hiword mask (b1 << 16). The patch adds gate flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: add CLK_DIVIDER_HIWORD_MASK flagHaojian Zhuang2013-06-152-2/+18
| | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as setting divider, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds divider flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mux: add CLK_MUX_HIWORD_MASKHaojian Zhuang2013-06-152-2/+20
| | | | | | | | | | | | | | | In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the paradigm of reading-changing-writing the register contents. Instead they use a hiword mask to indicate the changed bits. When b01 should be set as switching mux, it also needs to indicate the change by setting hiword mask (b11 << 16). The patch adds mux flag for this usage. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Always notify whole subtree when reparentingSoren Brinkmann2013-06-151-2/+1
| | | | | | | | | | | | | | | | A clock's notifier count only reflects notifiers which are registered directly for that clock. A reparent operation though affects the whole subtree because of a potential rate change. When issuing the pre rate change notifications only the notifier count for the clock to be changed is considered and notifiers for subclocks may never be called. Resulting in clocks in the subtree which have registered notifiers, may receive a POST_- or ABORT_RATE_CHANGE notification, without a PRE_RATE_CHANGE_NOTIFICATION. Therefore always traverse the whole subtree when issueing pre rate change notifications during a reparent operation. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* MAINTAINERS: make drivers/clk entry match subdirsStephen Warren2013-06-111-2/+3
| | | | | | | | | | | | | Modify the drivers/clk MAINTAINERS entry so that it matches the entire drivers/clk tree, with the exception of clkdev.c which has a separate entry. Make a similar change to pick up all clk-related header files. This causes get_maintainers.pl to spit out the expected results for any patches to clock drivers that are in sub-directories of drivers/clk, e.g. drivers/clk/tegra/. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: honor CLK_GET_RATE_NOCACHE in clk_set_ratePeter De Schrijver2013-06-111-1/+1
| | | | | | | | | clk_set_rate() uses clk->rate directly. This causes problems if the clock is marked as CLK_GET_RATE_NOCACHE. Hence call clk_get_rate() to get the current rate. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: use clk_get_rate() for debugfsPeter De Schrijver2013-06-111-2/+2
| | | | | | | | | debugfs uses the rate field directly. However this ignores the CLK_GET_RATE_NOCACHE flag. Call clk_get_rate() instead. Tested-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: Use override bits when neededPeter De Schrijver2013-06-111-33/+49
| | | | | | | | | | PLLM has override bits in the PMC. Use those when PLLM_OVERRIDE_ENABLE is set. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: override bits for Tegra30 PLLMPeter De Schrijver2013-06-111-0/+18
| | | | | | | | | Define override bits for Tegra30 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: override bits for Tegra114 PLLMPeter De Schrijver2013-06-111-0/+9
| | | | | | | | | | Define override bits for Tegra114 PLLM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up trivial merge conflict]
* clk: tegra: Add fields for override bitsPeter De Schrijver2013-06-111-0/+8
| | | | | | | | | PLLM can have override bits in the PMC. Describe those in the PLL parameters. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: fix sclk_parentsPeter De Schrijver2013-06-111-1/+1
| | | | | | | | | Use the correct parents for sclk according to the TRM. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: fix pllre initilizationPeter De Schrijver2013-06-111-2/+1
| | | | | | | | | The PLLRE flags weren't set correctly. Fixed in this patch. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: PLL m,n,p init for Tegra114Peter De Schrijver2013-06-111-0/+77
| | | | | | | Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: allow PLL m,n,p init from SoC filesPeter De Schrijver2013-06-112-39/+53
| | | | | | | | | | The m,n,p fields don't have the same bit offset and width across all PLLs. This patch allows SoC specific files to indicate the offset and width. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: pllp_out2 divider is int onlyPeter De Schrijver2013-06-111-2/+2
| | | | | | | | | The pllp_out2 should be integer only, the fractional bit should always be 0. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: pllc and pllxc should use pdiv_mapPeter De Schrijver2013-06-111-80/+82
| | | | | | | | | | | The pllc and pllxc code weren't always using the correct pdiv_map to map between the post divider value and the hw p field. This could result in illegal values being programmed in the hw. Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: divider: do not propagate rate change request when unnecessaryShawn Guo2013-06-101-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the current rate of parent clock is sufficient to provide child a requested rate with a proper divider setting, the rate change request should not be propagated. Instead, changing the divider setting is good enough to get child clock run at the requested rate. On an imx6q clock configuration illustrated below, ahb --> ipg --> ipg_per 132M 66M 66M calling clk_set_rate(ipg_per, 22M) with the current clk_divider_bestdiv() implementation will result in the rate change up to ahb level like the following, because of the unnecessary/incorrect rate change propagation. ahb --> ipg --> ipg_per 66M 22M 22M Fix the problem by trying to see if the requested rate can be achieved by simply changing the divider value, and in that case return the divider immediately from function clk_divider_bestdiv() as the best one, so that all those unnecessary rate change propagation can be saved. Reported-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: ux500: Clocks definition for u8540Philippe Begnic2013-06-061-1/+559
| | | | | | | First clocks definition version of PRCMU and PRCC clocks for u8540 platform Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* mfd: db8500: Update BML clock register for db8580Philippe Begnic2013-06-063-0/+3
| | | | | | | | | BML clock register address in DB8580 has changed.Defined a new address under different name for DB8580. Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* mfd: db8500: Update register definition for u8540 clockPhilippe Begnic2013-06-062-2/+13
| | | | | | | | PRCMU and ab8500 registers updated for u8540 Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: ux500: Pass clock base adresses in initcall for u8540 and u9540Philippe Begnic2013-06-064-8/+12
| | | | | | | | | | Align on u8500 version, pass clock base address in clk_init functions for u8540 and u9540. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Philippe Begnic <philippe.begnic@st.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra114: Fix msenc clock registerMikko Perttunen2013-06-041-1/+1
| | | | | | | | The msenc clock's register was set to the usb3 clock's register. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: Use common of_clk_init functionPrashant Gaikwad2013-05-317-36/+8
| | | | | | | | | Use common of_clk_init() function for clocks initialization. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra114: correctly output clk_32kAlexandre Courbot2013-05-311-0/+3
| | | | | | | | | | | | Tegra has a blink timer register that allows to modulate the clk_32k clock before outputting it. Since clk_32k is presented to the kernel as a fixed clock, make sure this register does not tamper with the clock frequency and that clk_32k is outputted as-is, similarly to what is done on t20 and t30. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: tegra: fix clk_out parents listPrashant Gaikwad2013-05-312-4/+4
| | | | | | | | | | | Number of parents for clk_out_2 and clk_out_3 was incorrectly set to clk_out1_parents. Even though it did not break anything since the size was same better to fix. Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Add TI-Nspire clock driversDaniel Tang2013-05-313-0/+178
| | | | | | | | | | | | | This patch adds a basic clock driver for the TI-Nspire calculator series. Changes from v1: * Removed filename in header comment * Removed unnecessary #undef EXTRACT statement Signed-off-by: Daniel Tang <dt.tangr@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed $SUBJECT and changelog max width]
* clk: use platform_{get,set}_drvdata()Jingoo Han2013-05-302-3/+3
| | | | | | | | | | Use the wrapper functions for getting and setting the driver data using platform_device instead of using dev_{get,set}_drvdata() with &pdev->dev, so we can directly pass a struct platform_device. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: mpc85xx: Update the compatible stringTang Yuantian2013-05-301-1/+1
| | | | | | | | | The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: improved $SUBJECT line]
* clk: sunxi: "cpu_data" is defined in header files of some architecturesGiacomo A. Catenazzi2013-05-291-2/+2
| | | | | | | | | | | In some architectures, the #define cpu_data is not a "macro-function", so the compiler will substitute the identifier with probably something wrong. Signed-off-by: Giacomo A. Catenazzi <cate@cateee.net> Signed-off-by: Emilio López <emilio@elopez.com.ar> [emilio@elopez.com.ar: use cpu_mux_data instead of this_cpu_data] Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: exynos5250: Add sclk_mpll to the parent list of mout_cpu clockTushar Behera2013-05-291-1/+1
| | | | | | | | | | | | | | 'mout_mpll' is added the list of parent clocks for 'mout_cpu'. 'mout_mpll' is an alias to the clock 'sclk_mpll'. Hence 'sclk_mpll' should be added to the list of parent clocks. This results in an error when cpufreq driver for EXYNOS5250 tries to set 'mout_mpll' as a parent for 'mout_cpu'. clk_set_parent: clk sclk_mpll can not be parent of clk mout_cpu Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: exynos5250: Update cpufreq related clocks for EXYNOS5250Tushar Behera2013-05-291-3/+3
| | | | | | | | | | | | | | | cpufreq driver for EXYNOS5250 is not a platform driver, hence we cannot currently pass the clock names through a device tree node. Instead, we need to make them available through a global alias. cpufreq driver for EXYNOS5250 requires four clocks - 'armclk', 'mout_cpu', 'mout_mpll' and 'mout_apll'. 'armclk' has already been defined with an alias, 'mout_cpu', 'mout_mpll' and 'mout_apll' are now defined with an alias. Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Remove unnecessary divisor adjustment in vtwm_dclk_set_rate()Tony Prisk2013-05-291-4/+0
| | | | | | | | | | | | | | | | | The divisor adjustment code to ensure that a divisor is not rounded down, thereby giving a rate higher than requested, is unnecessary and in some instances results in the actual rate being much lower than requested due to rounding errors. The test is already performed in vtwm_dclk_round_rate(), which is always called when clk_set_rate is called. Due to rounding errors in the line: divisor = parent_rate / rate (clk-vt8500.c:160) we will sometimes end up adjusting the divisor twice - first in round_rate and then again in set_rate. This patch removes the test/adjustment in vtwm_dclk_set_rate. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: vt8500: Add support for clocks on the WM8850 SoCsTony Prisk2013-05-292-0/+73
| | | | | | | | The WM8850 has a different PLL clock to the previous versions. This patch adds support for the WM8850-style PLL clocks. Signed-off-by: Tony Prisk <linux@prisktech.co.nz> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Disable unused clocks after deferred probing is doneSaravana Kannan2013-05-291-1/+1
| | | | | | | | | | With deferred probing, late_initcall() is too soon to declare a clock as unused. Wait for deferred probing to finish before declaring a clock as unused. Since deferred probing is done in late_initcall(), do the unused check to late_initcall_sync. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: wm831x: Fix wm831x_clkout_get_parentAxel Lin2013-05-281-3/+3
| | | | | | | | | | | | | | | | | | | | Current code looks strange because calling wm831x_clkout_set_parent() with 0 as parent parameter, wm831x_clkout_get_parent() will return 1. According to the datasheet: R16528 (4090h) Clock Control1 BIT 0: CLKOUT output source select 0 = FLL output 1 = 32.768kHz oscillator Thus fix the entry order in wm831x_clkout_parents[] to make it has the same meaning as the datasheet and make the return value of wm831x_clkout_get_parent() consistent with the parent pass to wm831x_clkout_set_parent(). Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: wm831x: Fix update wrong register for enable/disable FLLAxel Lin2013-05-281-3/+3
| | | | | | | | | | | | | | | | | According to the datasheet, FLL Enable is controlled by R16530 (4092h) FLL Control1 BIT 0: FLL Enable 0 = Disable 1 = Enable Thus the code should update WM831X_FLL_CONTROL_1 register rather than WM831X_FLL_CONTROL_2 register. Also fixes a trivial typo in dev_crit message. Signed-off-by: Axel Lin <axel.lin@ingics.com> Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: si5351: Allow to build without CONFIG_OFSebastian Hesselbarth2013-05-281-1/+0
| | | | | | | | With of_clk_provider stubs for CONFIG_OF not set, we can now also enable clk-si5351 on those architectures. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add non CONFIG_OF routines for clk-providerSebastian Hesselbarth2013-05-281-8/+39
| | | | | | | | | | | | | | | Some drivers that are shared between architectures have HAVE_CLK selected but don't have OF. To remove compilation errors for drivers that provide clocks on DT with of_clk_add_provider we would have to enclose these calls within #ifdef CONFIG_OF, #endif. This patch adds some stubs for OF related clk-provider functions that either do nothing or return appropriate values if CONFIG_OF is not set. So, definition of these routines will always be available. Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: Fix race condition between clk_set_parent and clk_enable()Saravana Kannan2013-05-281-45/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, the following race condition is possible. * clk-A has two parents - clk-X and clk-Y. * All three are disabled and clk-X is current parent. * Thread A: clk_set_parent(clk-A, clk-Y). * Thread A: <snip execution flow> * Thread A: Grabs enable lock. * Thread A: Sees enable count of clk-A is 0, so doesn't enable clk-Y. * Thread A: Updates clk-A SW parent to clk-Y * Thread A: Releases enable lock. * Thread B: clk_enable(clk-A). * Thread B: clk_enable() enables clk-Y, then enabled clk-A and returns. clk-A is now enabled in software, but not clocking in hardware since the hardware parent is still clk-X. The only way to avoid race conditions between clk_set_parent() and clk_enable/disable() is to ensure that clk_enable/disable() calls don't require changes to hardware enable state between changes to software clock topology and hardware clock topology. The options to achieve the above are: 1. Grab the enable lock before changing software/hardware topology and release it afterwards. 2. Keep the clock enabled for the duration of software/hardware topology change so that any additional enable/disable calls don't try to change the hardware state. Once the topology change is complete, the clock can be put back in its original enable state. Option (1) is not an acceptable solution since the set_parent() ops might need to sleep. Therefore, this patch implements option (2). This patch doesn't violate any API semantics. clk_disable() doesn't guarantee that the clock is actually disabled. So, no clients of a clock can assume that a clock is disabled after their last call to clk_disable(). So, enabling the clock during a parent change is not a violation of any API semantics. This also has the nice side effect of simplifying the error handling code. Signed-off-by: Saravana Kannan <skannan@codeaurora.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org> [mturquette@linaro.org: fixed up whitespace issue]
* clk: si5351: declare all device IDs for module loadingJean-Francois Moine2013-05-281-1/+4
| | | | | | | | | | | When the si5351 driver is a kernel module, it is loaded into memory from its i2c device IDs, but not from its DT compatible properties. This patch declares the i2c device IDs of all chip variants. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: sun5i: Add compatibles for Allwinner A13Maxime Ripard2013-05-284-112/+187
| | | | | | | | | | The A13 has a lot less clocks than the one found in the Allwinner A10. Add these stripped down clocks to the clock driver and in the documentation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: ux500: abx500-clk: rename ux500 audio codec aliasesFabio Baltieri2013-05-281-4/+4
| | | | | | | | | | Change soc-audio related clk_register_clkdev() device names to reflect the ones actually used in current snd-soc-mop500 and ab8500-codec drivers. Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Fabio Baltieri <fabio.baltieri@linaro.org> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: si5351: Allow user to define disabled state for every clock outputSebastian Hesselbarth2013-05-284-3/+95
| | | | | | | | | This patch adds platform data and DT bindings to allow to overwrite the stored disabled state for each clock output. Signed-off-by: Marek Belisko <marek.belisko@streamunlimited.com> Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* clk: add PowerPC corenet clock driver supportTang Yuantian2013-05-284-0/+289
| | | | | | | | | This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
* Linux 3.10-rc3v3.10-rc3Linus Torvalds2013-05-261-1/+1
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* ipc/sem.c: Fix missing wakeups in do_smart_update_queue()Manfred Spraul2013-05-261-5/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | do_smart_update_queue() is called when an operation (semop, semctl(SETVAL), semctl(SETALL), ...) modified the array. It must check which of the sleeping tasks can proceed. do_smart_update_queue() missed a few wakeups: - if a sleeping complex op was completed, then all per-semaphore queues must be scanned - not only those that were modified by *sops - if a sleeping simple op proceeded, then the global queue must be scanned again And: - the test for "|sops == NULL) before scanning the global queue is not required: If the global queue is empty, then it doesn't need to be scanned - regardless of the reason for calling do_smart_update_queue() The patch is not optimized, i.e. even completing a wait-for-zero operation causes a rescan. This is done to keep the patch as simple as possible. Signed-off-by: Manfred Spraul <manfred@colorfullife.com> Acked-by: Davidlohr Bueso <davidlohr.bueso@hp.com> Cc: Rik van Riel <riel@redhat.com> Cc: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge tag 'nfs-for-3.10-3' of git://git.linux-nfs.org/projects/trondmy/linux-nfsLinus Torvalds2013-05-2611-41/+78
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NFS client bugfixes from Trond Myklebust: - Stable fix to prevent an rpc_task wakeup race - Fix a NFSv4.1 session drain deadlock - Fix a NFSv4/v4.1 mount regression when not running rpc.gssd - Ensure auth_gss pipe detection works in namespaces - Fix SETCLIENTID fallback if rpcsec_gss is not available * tag 'nfs-for-3.10-3' of git://git.linux-nfs.org/projects/trondmy/linux-nfs: NFS: Fix SETCLIENTID fallback if GSS is not available SUNRPC: Prevent an rpc_task wakeup race NFSv4.1 Fix a pNFS session draining deadlock SUNRPC: Convert auth_gss pipe detection to work in namespaces SUNRPC: Faster detection if gssd is actually running SUNRPC: Fix a bug in gss_create_upcall
| * NFS: Fix SETCLIENTID fallback if GSS is not availableChuck Lever2013-05-231-1/+1
| | | | | | | | | | | | | | | | | | Commit 79d852bf "NFS: Retry SETCLIENTID with AUTH_SYS instead of AUTH_NONE" did not take into account commit 23631227 "NFSv4: Fix the fallback to AUTH_NULL if krb5i is not available". Signed-off-by: Chuck Lever <chuck.lever@oracle.com> Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
| * SUNRPC: Prevent an rpc_task wakeup raceTrond Myklebust2013-05-221-1/+7
| | | | | | | | | | | | | | | | | | | | | | The lockless RPC_IS_QUEUED() test in __rpc_execute means that we need to be careful about ordering the calls to rpc_test_and_set_running(task) and rpc_clear_queued(task). If we get the order wrong, then we may end up testing the RPC_TASK_RUNNING flag after __rpc_execute() has looped and changed the state of the rpc_task. Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com> Cc: stable@vger.kernel.org
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