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* [ARM] pxa/zaurus: cleanup sharpsl_pm.cPavel Machek2009-12-012-59/+59
| | | | | | | | This fixes checkpatch/style problems in sharpsl_pm.c, allowing me to submit real fixes next. Signed-off-by: Pavel Machek <pavel@ucw.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: rename macro from pxa9xx to pxa93xHaojian Zhuang2009-12-011-3/+4
| | | | | | | | Because original macro can only judge whether current CPU is pxa93x, rename the macro to correct name. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add EXT_WAKEUP interrupts handling for pxa3xxMike Rapoport2009-12-011-0/+42
| | | | | Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: make CPU_PXA* to be selectable hidden optionsEric Miao2009-12-011-29/+36
| | | | | | | CONFIG_CPU_PXA{300,310,320,930,935,950} are really platform dependent and should be made into selectable hidden options. Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: select CPU_PXA310 for MACH_COLIBRI300Eric Miao2009-12-011-0/+1
| | | | | | | | MACH_COLIBRI300 is supposed to support both PXA300 and PXA310, select the missing CPU_PXA310. Signed-off-by: Eric Miao <eric.y.miao@gmail.com> Acked-by: Daniel Mack <daniel@caiaq.de>
* [ARM] pxa: introduce CONFIG_MACH_ZYLONITE{300,320} for CPU_PXA* removingEric Miao2009-12-012-6/+14
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: allow platforms to control which uarts are registeredRussell King2009-12-0152-14/+230
| | | | | | | | | | | | | | | | | | For some platforms, it is inappropriate to register all PXA UARTs. In some cases, the UARTs may not be used, and in others we may want to avoid registering the UARTs to allow other drivers (eg, FICP) to make use of the UART. In addition, a while back there was a request to be able to pass platform data to the UART driver. This patch enables all of this by providing functions platforms can call to register each individual UART. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Mike Rapoport <mike@compulab.co.il> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add U2D registers and bits definitionsIgor Grinberg2009-12-011-0/+199
| | | | | | | | | This should be eventually moved to somewhere closer to the U2D driver, but is kept here atm so it's easier for USB configuration code to work. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: register U2D clock for pxa3xxIgor Grinberg2009-12-011-0/+2
| | | | | | Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: use platform_device_id table for SSP driverEric Miao2009-12-011-58/+15
| | | | Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add apmu clock support in mmpHaojian Zhuang2009-12-012-0/+16
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add missing irq events for pxa168Haojian Zhuang2009-12-011-1/+3
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: re-order platforms in Kconfig and MakefileEric Miao2009-12-012-322/+329
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Due to the naming mess in Kconfig and Makefile, I'd like to get them sorted in the following order: 1. By category: Intel/Marvell Dev Platforms, followed by 3rd party platforms, followed by end-user products (this is to ensure the commonly referenced platforms will appear first) 2. By vendor name in alphabetic within each category (this is to ensure code reuse and similar platforms can be grouped as much as possible) VENDOR BOARD Intel/Marvell Lubbock Intel/Marvell Mainstone Intel/Marvell Zylonite Intel/Marvell Littleton Intel/Marvell TavorEVB Intel/Marvell SAAR Accelent IDP Arcom/Eurotech VIPER Community Balloon3 Cogent CSB726 CompuLab EM_X270 CompuLab EXEDA CompuLab ARMCORE CompuLab CM_X300 Gumstix Gumstix Intel Research MOTE2 Intel research Stargate2 Iskratel XCEP Keith and Koep Trizeps4 LogicPD LPD270 Phytec PCM027 Toradex Colibri HP HX4700 HP H5000 HTC Himalaya HTC Magician Mitac MioA701 Motorola EZX NEC MP900C Palm Palm PDA Palm Palm GSM Sharp Zaurus Toshiba E-Series Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/treo: add Palm Centro 685 supportTomáš Čech2009-12-014-1/+180
| | | | | Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/treo: generalisation of Treo680 codeTomáš Čech2009-12-015-135/+183
| | | | | | Signed-off-by: Tomáš Čech <sleep_walker@suse.cz> Acked-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: update flash structure in onenand infoHaojian Zhuang2009-12-012-2/+2
| | | | | | | | | Since flash structure is changed from flash_platform_data to onenand_platform_data in generic driver. Update the struct in saar and ttc platform driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add onenand support for SAARHaojian Zhuang2009-12-011-1/+95
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add onenand support for TTC-DKBHaojian Zhuang2009-12-011-0/+87
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add nand support in aspensite boardHaojian Zhuang2009-12-011-0/+39
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa: add nand device and clock for pxa168/pxa910Haojian Zhuang2009-12-014-0/+23
| | | | | Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: move pxa3xx_nand.h common into plat directoryHaojian Zhuang2009-12-017-8/+8
| | | | | | | | | Since the same nand controller is shared between ARCH_PXA and ARCH_MMP. Move the pxa3xx_nand.h from mach directory to plat directoy. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Cc: David Woodhouse <david.woodhouse@intel.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: update dependancy to support ARCH_MMPHaojian Zhuang2009-12-011-1/+1
| | | | | | | | MTD_NAND_PXA3xx module is shared between ARCH_PXA and ARCH_MMP. Update this configuration according to it. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: add new nand chip supportHaojian Zhuang2009-12-011-0/+48
| | | | | | | | Support samsung 2GbX8 and 32GbX8 nand flash. Support micron 4GbX8 and 4GbX16 nand flash. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: disable nand irq in initializationHaojian Zhuang2009-12-011-0/+3
| | | | | | | | | In some bootloader, IRQ is enabled. Writing nand triggers unexpected interrupts. So disable nand irq in initialization. After nand initialized and in working state, irq is controlled by nand driver. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: remove hardcode irq numberHaojian Zhuang2009-12-011-4/+7
| | | | | | | | | Nand driver uses IRQ_NAND as hardcode irq number. In ARCH_MMP, the irq number is different. So get irq resource from platform device structure and use it in initialization and deinitialization code. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: remove hardcode register addressHaojian Zhuang2009-12-011-6/+4
| | | | | | | | Although nand controller is same between PXA3xx and MMP, the register space is different. Remove the hardcode register address setting in pxa3xx_nand.h. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: adjust timing of Micron NAND flashHaojian Zhuang2009-12-011-1/+1
| | | | | | | Slow down the tRp of Micron NAND flash timing. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: reset read buffer before readingHaojian Zhuang2009-12-011-0/+1
| | | | | | | Initialize the read buffer content to 0xFF. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa3xx_nand: fix memory out of boundHaojian Zhuang2009-12-011-2/+3
| | | | | | | | When fetch nand data with non-DMA mode, we should align info->data_size to 32bit, not 8bit. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* [ARM] pxa/saar: set default WLED output currentHaojian Zhuang2009-12-011-0/+5
| | | | | | | | Set default WLED output current in saar. Otherwise, LCD backlight won't be effective. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* backlight: da903x_bl: control WLED output current in da9034Haojian Zhuang2009-12-012-0/+11
| | | | | | | Update WLED output current source before changing brightness. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* backlight: tdo24m: ensure chip select changes between transfersMike Rapoport2009-12-011-0/+1
| | | | | | | | | | Some SPI host drivers do not change chip select betwen transfers unless .cs_chnage field is explicitly set. The LCD spec requires chip select change between consecuitive transfers, so ensure it at the SPI driver level. Signed-off-by: Mike Rapoport <mike@compulab.co.il> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxamci: introduce mmc_has_26mhz() and include pxa935Haojian Zhuang2009-12-011-4/+6
| | | | | | | | Along with more processor supporting 26MHz mode (including pxa935), introduce an individual macro mmc_has_26mhz() for this. Signed-off-by: Haojian Zhuang <haojian.zhuang@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa168fb: remove useless vsync/hsync invert flagJun Nie2009-12-011-2/+0
| | | | | | | fb_var_screeninfo.var has already encoded this information. Signed-off-by: Jun Nie <njun@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxa168fb: fix offset setting at initializationJun Nie2009-12-011-0/+1
| | | | | Signed-off-by: Jun Nie <njun@marvell.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxafb: add transparency field to pxafb_mode_info structPieter Grimmerink2009-12-012-1/+3
| | | | | | | | This allows to select either RGB565 (transparency 0) or RGBT555 (transparency 1) from the mode info Signed-off-by: Pieter Grimmerink <p.grimmerink@inepro.com> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* pxafb: use passed fb_var_screeninfo struct in pxafb_pan_display()Sven Neumann2009-12-011-5/+17
| | | | | | | | | | | | | | | | | | pxafb_pan_display() used to ignore the fb_var_screeninfo parameter. Now pass it to setup_base_frame() instead of pulling default values out of fb_info. And the original patch has an issue of pxafb_pan_display() paying only attention to the 'var' parameter passed in, and Ville Syrjälä pointed out, this is potentially dangerous as user could pass in any other screeninfo parameters as well, and not only such that are relevant for display panning. This is fixed by limiting the arguments actually used to .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP. Signed-off-by: Sven Neumann <s.neumann@raumfeld.com> Cc: Ville Syrjälä <syrjala@sci.fi> Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* MAINTAINERS: Add entries for IMote 2 and Stargate 2Jonathan Cameron2009-11-301-0/+13
| | | | | Signed-off-by: Jonathan Cameron <jic23@cam.ac.uk> Signed-off-by: Eric Miao <eric.y.miao@gmail.com>
* Linux 2.6.32-rc8v2.6.32-rc8Linus Torvalds2009-11-191-1/+1
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* Merge branch 'bugfixes' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6Linus Torvalds2009-11-192-11/+9
|\ | | | | | | | | | | * 'bugfixes' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6: SUNRPC: Address buffer overrun in rpc_uaddr2sockaddr() NFSv4: Fix a cache validation bug which causes getcwd() to return ENOENT
| * SUNRPC: Address buffer overrun in rpc_uaddr2sockaddr()Chuck Lever2009-11-141-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The size of buf[] must account for the string termination needed for the first strict_strtoul() call. Introduced in commit a02d6926. Fábio Olivé Leite points out that strict_strtoul() requires _either_ '\n\0' _or_ '\0' termination, so use the simpler '\0' here instead. See http://bugzilla.kernel.org/show_bug.cgi?id=14546 . Reported-by: argp@census-labs.com Signed-off-by: Chuck Lever <chuck.lever@oracle.com> Signed-off-by: Fábio Olivé Leite <fleite@redhat.com> Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
| * NFSv4: Fix a cache validation bug which causes getcwd() to return ENOENTTrond Myklebust2009-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changeset a65318bf3afc93ce49227e849d213799b072c5fd (NFSv4: Simplify some cache consistency post-op GETATTRs) incorrectly changed the getattr bitmap for readdir(). This causes the readdir() function to fail to return a fileid/inode number, which again exposed a bug in the NFS readdir code that causes spurious ENOENT errors to appear in applications (see http://bugzilla.kernel.org/show_bug.cgi?id=14541). The immediate band aid is to revert the incorrect bitmap change, but more long term, we should change the NFS readdir code to cope with the fact that NFSv4 servers are not required to support fileids/inode numbers. Reported-by: Daniel J Blueman <daniel.blueman@gmail.com> Cc: stable@kernel.org Signed-off-by: Trond Myklebust <Trond.Myklebust@netapp.com>
* | vt: Fix use of "new" in a struct fieldAlan Cox2009-11-192-5/+5
| | | | | | | | | | | | | | | | | | | | | | As this struct is exposed to user space and the API was added for this release it's a bit of a pain for the C++ world and we still have time to fix it. Rename the fields before we end up with that pain in an actual release. Signed-off-by: Alan Cox <alan@linux.intel.com> Reported-by: Olivier Goffart Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Fix handling of the HP/Acer 'DMAR at zero' BIOS error for machines with ↵David Woodhouse2009-11-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | <4GiB RAM. Commit 86cf898e1d0fca245173980e3897580db38569a8 ("intel-iommu: Check for 'DMAR at zero' BIOS error earlier.") was supposed to work by pretending not to detect an IOMMU if it was actually being reported by the BIOS at physical address zero. However, the intel_iommu_init() function is called unconditionally, as are the corresponding functions for other IOMMU hardware. So the patch only worked if you have RAM above the 4GiB boundary. It caused swiotlb to be initialised when no IOMMU was detected during early boot, and thus the later IOMMU init would refuse to run. But if you have less RAM than that, swiotlb wouldn't get set up and the IOMMU _would_ still end up being initialised, even though we never claimed to detect it. This patch also sets the dmar_disabled flag when the error is detected during the initial detection phase -- so that the later call to intel_iommu_init() will return without doing anything, regardless of whether swiotlb is used or not. Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'fixes' of ↵Linus Torvalds2009-11-187-32/+70
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq * 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/davej/cpufreq: [CPUFREQ] Fix stale cpufreq_cpu_governor pointer [CPUFREQ] Resolve time unit thinko in ondemand/conservative govs [CPUFREQ] speedstep-ich: fix error caused by 394122ab144dae4b276d74644a2f11c44a60ac5c [CPUFREQ] Fix use after free on governor restore [CPUFREQ] acpi-cpufreq: blacklist Intel 0f68: Fix HT detection and put in notification message [CPUFREQ] powernow-k8: Fix test in get_transition_latency() [CPUFREQ] longhaul: select Longhaul version 2 for capable CPUs
| * | [CPUFREQ] Fix stale cpufreq_cpu_governor pointerPrarit Bhargava2009-11-171-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Dave, Attached is an update of my patch against the cpufreq fixes branch. Before applying the patch I compiled and booted the tree to see if the panic was still there -- to my surprise it was not. This is because of the conversion of cpufreq_cpu_governor to a char[]. While the panic is kaput, the problem of stale data continues and my patch is still valid. It is possible to end up with the wrong governor after hotplug events because CPUFREQ_DEFAULT_GOVERNOR is statically linked to a default, while the cpu siblings may have had a different governor assigned by a user. ie) the patch is still needed in order to keep the governors assigned properly when hotplugging devices Signed-off-by: Prarit Bhargava <prarit@redhat.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] Resolve time unit thinko in ondemand/conservative govsPallipadi, Venkatesh2009-11-172-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ondemand and conservative governors are messing up time units in the code path where NO_HZ is not enabled and ignore_nice is set. The walltime idletime stored is in jiffies and nice time calculation is happening in microseconds. The problem was reported and diagnosed by Alexander here. http://marc.info/?l=linux-kernel&m=125752550404513&w=2 The patch below fixes this thinko. Reported-by: Alexander Miller <Miller@fmi.uni-stuttgart.de> Tested-by: Alexander Miller <Miller@fmi.uni-stuttgart.de> Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] speedstep-ich: fix error caused by ↵Rusty Russell2009-11-171-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 394122ab144dae4b276d74644a2f11c44a60ac5c "[CPUFREQ] cpumask: avoid playing with cpus_allowed in speedstep-ich.c" changed the code to mistakenly pass the current cpu as the "processor" argument of speedstep_get_frequency(), whereas it should be the type of the processor. Addresses http://bugzilla.kernel.org/show_bug.cgi?id=14340 Based on a patch by Dave Mueller. Signed-off-by: Rusty Russell <rusty@rustcorp.com.au> Acked-by: Dominik Brodowski <linux@brodo.de> Reported-by: Dave Mueller <dave.mueller@gmx.ch> Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] Fix use after free on governor restoreDmitry Monakhov2009-11-171-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently on governer backup/restore path we storing governor's pointer. This is wrong because one may unload governor's module after cpu goes offline. As result use-after-free will take place on restored cpu. It is not easy to exploit this bug, but still we have to close this issue ASAP. Issue was introduced by following commit 084f34939424161669467c19280dbcf637730314 ##TESTCASE## #!/bin/sh -x modprobe acpi_cpufreq # Any non default governor, in may case it is "ondemand" modprobe cpufreq_ondemand echo ondemand > /sys/devices/system/cpu/cpu0/cpufreq/scaling_governor rmmod acpi_cpufreq rmmod cpufreq_ondemand modprobe acpi_cpufreq # << use-after-free here. Signed-off-by: Dmitry Monakhov <dmonakhov@openvz.org> Signed-off-by: Dave Jones <davej@redhat.com>
| * | [CPUFREQ] acpi-cpufreq: blacklist Intel 0f68: Fix HT detection and put in ↵John Villalovos2009-11-171-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | notification message Removing the SMT/HT check, since the Errata doesn't mention Hyper-Threading. Adding in a printk, so that the user knows why acpi-cpufreq refuses to load. Also, once system is blacklisted, don't repeat checks to see if blacklisted. This also causes the message to only be printed once, rather than for each CPU. Signed-off-by: John L. Villalovos <john.l.villalovos@intel.com> Signed-off-by: Dave Jones <davej@redhat.com>
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