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* Merge tag 'samsung-dt-devfreq-4.7' of ↵Arnd Bergmann2016-05-1012-155/+1295
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late Merge "ARM: dts: exynos: Devfreq for v4.7: from Krzysztof Kozłowski: Topic branch for Device Tree changes adding new generic devfreq driver, for v4.7: 1. Add bus nodes for Exynos3250, Exynos4x12, Exynos4210 and Exynos542x. 2. Split out common PPMU (Performance Monitoring Unit) nodes into separate DTSI. The PPMU provides performance data for devfreq. 3. Add NoCP (Network on Chip Probe) node for Exynos542x. On this SoC, like PPMU on older designs, provides performance data for devfreq. 4. Enable DFVS (Dynamic Voltage and Frequency Scaling) on boards: - Exynos3250 Rinato, - Exynos4412 Odroid-X/X2/U3 and Trats2, - Exynos5422 Odroid XU3/XU3-Lite/XU4. * tag 'samsung-dt-devfreq-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: ARM: dts: exynos: Add support of Bus frequency using VDD_INT for exynos5422-odroidxu3 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoC ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoC ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3 ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for exynos4412-odroidu3 ARM: dts: exynos: Add support of bus frequency using VDD_INT for exynos3250-rinato ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodes ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12 ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250 ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monk ARM: dts: exynos: Add DMC bus node for Exynos3250 clk: samsung: exynos542x: Add the clock id for ACLK dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoC
| * ARM: dts: exynos: Add support of Bus frequency using VDD_INT for ↵Chanwoo Choi2016-05-031-0/+99
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos5422-odroidxu3 This patch adds the bus device tree nodes for INT (Internal) block to enable the AMBA bus frequency scaling and add the NoC (Network on Chip) Probe Device Tree node to measure the bandwidth for AMBA AXI bus. The WCORE bus bus is parent device in INT block using VDD_INT. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos542x SoCChanwoo Choi2016-05-031-0/+371
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the AMBA bus nodes using VDD_INT for Exynos542x SoC. Exynos542x has the following AMBA buses to translate data between DRAM and sub-blocks. Following list specifies the detailed correlation between sub-block and clock: - CLK_DOUT_ACLK400_WCORE clock for WCORE's AXI - CLK_DOUT_ACLK100_NOC for NoC (Network on Chip)'s AXI - CLK_DOUT_PCLK200_FSYS for FSYS's APB - CLK_DOUT_ACLK200_FSYS for FSYS's AXI - CLK_DOUT_ACLK200_FSYS2 for FSYS2's AXI - CLK_DOUT_ACLK333 for MFC's AXI - CLK_DOUT_ACLK266 for GEN's AXI - CLK_DOUT_ACLK66 for PERIC/PERIR's AXI - CLK_DOUT_ACLK333_G2D for G2D's AXI - CLK_DOUT_ACLK266_G2D for ACP's AXI - CLK_DOUT_ACLK300_JPEG for JPEG's AXI - CLK_DOUT_ACLK166 for JPEG's APB - CLK_DOUT_ACLK300_DISP1 for FIMD's AXI - CLK_DOUT_ACLK400_DISP1 for DISP1's AXI - CLK_DOUT_ACLK300_GSCL for GSCL Scaler's AXI - CLK_DOUT_ACLK400_MSCL for MSCL's AXI Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add NoC Probe dt node for Exynos542x SoCChanwoo Choi2016-05-031-0/+36
| | | | | | | | | | | | | | | | | | | | | | This patch adds the NoCP (Network on Chip Probe) Device Tree node to measure the bandwidth of memory and g3d in Exynos542x SoC. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add support of bus frequency for exynos4412-trats/odroidu3Chanwoo Choi2016-05-032-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bus device tree nodes for both MIF (Memory) and INT (Internal) block to enable the bus frequency. The DMC bus is parent device in MIF block using VDD_MIF and the LEFTBUS bus is parent device in INT block using VDD_INT. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Expand the voltage range of buck1/3 regulator for ↵Chanwoo Choi2016-05-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos4412-odroidu3 This patch expands the voltage range of buck1/3 regulator due to as following: - MIF (Memory Interface) bus frequency needs the range of '900 - 1100 mV'. - INT (Internal) bus frequency needs the range of '900 - 1050 mV'. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add support of bus frequency using VDD_INT for ↵Chanwoo Choi2016-05-031-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exynos3250-rinato This patch adds the bus device-tree nodes of INT (internal) block to enable the bus frequency scaling. The following sub-blocks share the VDD_INT power source: - LEFTBUS (parent device) - RIGHTBUS - PERIL - LCD0 - FSYS - MCUISP / ISP - MFC The LEFTBUS is parent device with devfreq ondemand governor and the rest of devices depend on the LEFTBUS device. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add exynos4412-ppmu-common dtsi to delete duplicate PPMU nodesChanwoo Choi2016-05-035-120/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the exynos4412-ppmu-common.dtsi to remove duplicate PPMU nodes because exynos3250-rinato/monk, exynos4412-trats2/odroidu3 has the same PPMU device tree node. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4210Chanwoo Choi2016-05-031-0/+159
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bus nodes for Exynos4210 SoC. Exynos4210 SoC has one power line for all buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - DMC/ACP clock for DMC (Dynamic Memory Controller) - ACLK200 clock for LCD0 - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD0/LCD1 - ACLK133 clock for FSYS/GPS - GDL/GDR clock for LEFTBUS/RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos4x12Chanwoo Choi2016-05-031-0/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bus nodes using VDD_INT for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK100 clock for PERIL/PERIR/MFC(PCLK) - ACLK160 clock for CAM/TV/LCD : The minimum clock of ACLK160 should be over 160MHz. When drop the clock under 160MHz, show the broken image. - ACLK133 clock for FSYS - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add bus nodes using VDD_MIF for Exynos4x12Chanwoo Choi2016-05-031-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bus nodes using VDD_MIF for Exynos4x12 SoC. Exynos4x12 has the following AXI buses to translate data between DRAM and DMC/ACP/C2C. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> [m.reichl and linux.amoon: Tested it on exynos4412-odroidu3 board] Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add bus nodes using VDD_INT for Exynos3250Chanwoo Choi2016-05-031-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the bus nodes using VDD_INT for Exynos3250 SoC. Exynos3250 has following AXI buses to translate data between DRAM and sub-blocks. Following list specifies the detailed relation between DRAM and sub-blocks: - ACLK400 clock for MCUISP - ACLK266 clock for ISP - ACLK200 clock for FSYS - ACLK160 clock for LCD0 - ACLK100 clock for PERIL - GDL clock for LEFTBUS - GDR clock for RIGHTBUS - SCLK_MFC clock for MFC Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add DMC bus frequency for exynos3250-rinato/monkChanwoo Choi2016-05-032-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the DMC (Dynamic Memory Controller) bus frequency node which includes the devfreq-events and regulator properties. The bus frequency support the DVFS (Dynamic Voltage Frequency Scaling) feature with ondemand governor. The devfreq-events (ppmu_dmc0*) can monitor the utilization of DMC bus on runtime and the buck1_reg (VDD_MIF power line) supplies the power to the DMC block. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * ARM: dts: exynos: Add DMC bus node for Exynos3250Chanwoo Choi2016-05-031-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the DMC (Dynamic Memory Controller) bus node for Exynos3250 SoC. The DMC is an AMBA AXI-compliant slave to interface external JEDEC standard SDRAM devices. The bus includes the OPP tables and the source clock for DMC block. Following list specifies the detailed relation between the clock and DMC block: - The source clock of DMC block : div_dmc Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
| * Merge tag 'clk-v4.7-exynos542x' of git://linuxtv.org/snawrocki/samsung into ↵Krzysztof Kozlowski2016-05-032-31/+70
| |\ | | | | | | | | | | | | | | | | | | | | | for-v4.7-late/dts-exynos-devfreq Addition of IDs for Exynos542x SoC AMBA AXI bus clocks. These IDs are needed before we start using them in DTS.
| | * clk: samsung: exynos542x: Add the clock id for ACLKChanwoo Choi2016-04-151-30/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the clock id for ACLK clock which is source clock of AMBA AXI bus. This clock should be handled in the bus frequency scaling driver. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * dt-bindings: clock: Add the clock id for ACLK clock of Exynos542x SoCChanwoo Choi2016-04-151-1/+23
| |/ | | | | | | | | | | | | | | | | | | | | | | This patch adds the clock id for ACLK clock of Exynos542x SoC. ACLK clock means the source clock of AMBA AXI bus. This clock id should be used for Bus frequency scaling. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Tested-by: Markus Reichl <m.reichl@fivetechno.de> Tested-by: Anand Moon <linux.amoon@gmail.com> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | Merge tag 'imx-dt-clkdep-4.7' of ↵Arnd Bergmann2016-05-1013-15/+934
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/late Merge "The i.MX device tree updates with new clocks for 4.7" from Shawn Guo: - Add LCDIF and FlexCAN device support for i.MX7D - New support i.MX7D based Nitrogen7 board from Boundary Devices - Add display support for vf610-colibri board * tag 'imx-dt-clkdep-4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: dts: vf610-colibri: enable display controller ARM: dts: vf610: add display nodes ARM: dts: imx: add Boundary Devices Nitrogen7 board ARM: dts: imx7d: add flexcan support ARM: dts: imx7d: add lcdif support clk: imx: vf610: fix whitespace in vf610-clock.h clk: imx: vf610: add TCON ipg clock clk: imx: vf610: fix DCU clock tree clk: imx: add ckil clock for i.MX7 clk: imx: vf610: add suspend/resume support clk: imx: vf610: add WKPU unit clk: imx: vf610: leave DDR clock on clk: imx: clk-gate2: allow custom gate configuration clk: imx6sx: Register SAI clocks as shared clocks
| * | ARM: dts: vf610-colibri: enable display controllerStefan Agner2016-04-132-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable dcu node which is used by the DCU DRM driver. Assign the 5.7" EDT panel with VGA resolution which Toradex sells often with the evaluation board. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | ARM: dts: vf610: add display nodesStefan Agner2016-04-131-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add the dcu and tcon nodes to enable the Display Controller Unit and Timing Controller in Vybrid's SoC level device-tree file. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | ARM: dts: imx: add Boundary Devices Nitrogen7 boardGary Bisson2016-04-132-0/+746
| | | | | | | | | | | | | | | | | | | | | | | | | | | Based on i.MX7 Dual with 1GB of RAM. https://boundarydevices.com/product/nitrogen7/ Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | ARM: dts: imx7d: add flexcan supportGary Bisson2016-04-131-0/+20
| | | | | | | | | | | | | | | | | | | | | Add the device nodes for the i.MX7 FlexCAN buses. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | ARM: dts: imx7d: add lcdif supportGary Bisson2016-04-131-0/+11
| | | | | | | | | | | | | | | | | | | | | Add the device node for the i.MX7 eLCDIF interface. Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| * | Merge tag 'imx-clk-4.7' into imx/dt-clkdepShawn Guo2016-04-137-15/+89
| |\ \ | | |/ | |/| | | | | | | | | | | | | | | | | | | | | | The i.MX clock update for 4.7: - Register SAI clk as shared clocks to support SAI audio on i.MX6SX - Add the missing ckil clock for i.MX7 - Update clk-gate2 and vf610 clock driver to prepare for suspend support on VF610 - Fix DCU clock configurations and add TCON ipg clock to support DRM display on VF610
| | * clk: imx: vf610: fix whitespace in vf610-clock.hShawn Guo2016-04-121-1/+1
| | | | | | | | | | | | | | | | | | There is whitespace in VF610_CLK_OCOTP line. Fix it. Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: vf610: add TCON ipg clockStefan Agner2016-04-122-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the ipg (bus) clock for the TCON modules (Timing Controller). This module is required by the new DCU DRM driver, since the display signals pass through TCON. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: vf610: fix DCU clock treeStefan Agner2016-04-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to an earlier fix for the SAI clocks, the DCU clock hierarchy mixes the bus clock with the display controllers pixel clock. Tests have shown that the gates in CCM_CCGR3/9 registers do not control the DCU pixel clock, but only the register access clock (bus clock). Fix this by defining the parent clock of VF610_CLK_DCUx to be the bus clock (ipg_bus). Since the clock has not been used far, there are no further changes needed. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: add ckil clock for i.MX7Gary Bisson2016-04-062-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the necessary clock to use the ckil on i.MX7. Inspired from the following patch: https://github.com/boundarydevices/linux-imx6/commit/b80e8271 Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com> Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: vf610: add suspend/resume supportStefan Agner2016-03-311-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The clock register are lost when enterying LPSTOPx, hence provide suspend/resume functions restoring them. The clock gates get restored by the individual driver, hence we do not need to restore them here. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: vf610: add WKPU unitStefan Agner2016-03-312-1/+4
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: vf610: leave DDR clock onStefan Agner2016-03-312-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To use STOP mode without putting DDR3 into self-refresh mode, we need to keep the DDR clock enabled. Use the new gate configuration with a value of 2 to make sure that the clock is enabled in RUN, WAIT and STOP mode. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx: clk-gate2: allow custom gate configurationStefan Agner2016-03-312-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 2-bit gates found i.MX and Vybrid SoC support different clock configuration: 0b00: clk disabled 0b01: clk enabled in RUN mode but disabled in WAIT and STOP mode 0b10: clk enabled in RUN, WAIT and STOP mode (only Vybrid) 0b11: clk enabled in RUN and WAIT mode For some clocks, we might want to configure different behaviour, e.g. a memory clock should be on even in STOP mode. Add a new function imx_clk_gate2_cgr which allow to configure specific gate values through the cgr_val parameter. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
| | * clk: imx6sx: Register SAI clocks as shared clocksFabio Estevam2016-03-311-4/+6
| |/ | | | | | | | | | | | | | | SAIx and SAIx_IPG share the same bit fields in the CCM registers, so we should better register them via imx_clk_gate2_shared(). Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
* | Merge tag 'tegra-for-4.7-xusb-no-defconfig' of ↵Arnd Bergmann2016-05-094-50/+456
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/late Merge "ARM: tegra: Enable the XUSB controller" from Thierry Reding: These changes add support for the XUSB controller on Tegra124. It is an XHCI compatible controller that replaces the existing EHCI controllers. Support is enabled on Venice2, Jetson TK1 and Nyan-based Chromebooks. * tag 'tegra-for-4.7-xusb-no-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: ARM: tegra: Enable XUSB on Nyan ARM: tegra: Enable XUSB on Jetson TK1 ARM: tegra: Enable XUSB on Venice2 ARM: tegra: Add Tegra124 XUSB controller ARM: tegra: Move Tegra124 to the new XUSB pad controller binding
| * | ARM: tegra: Enable XUSB on NyanThierry Reding2016-04-291-28/+94
| | | | | | | | | | | | | | | | | | | | | Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Nyan boards. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: Enable XUSB on Jetson TK1Thierry Reding2016-04-291-14/+102
| | | | | | | | | | | | | | | | | | | | | Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Jetson TK1 board. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: Enable XUSB on Venice2Thierry Reding2016-04-291-1/+100
| | | | | | | | | | | | | | | | | | | | | Add XUSB pad controller and XUSB controller device tree nodes and enable them with a configuration for the Venice2 board. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: Add Tegra124 XUSB controllerThierry Reding2016-04-291-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | Add a device tree node for the Tegra XUSB controller. It contains a phandle to the XUSB pad controller for control of the PHYs assigned to the USB ports. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | ARM: tegra: Move Tegra124 to the new XUSB pad controller bindingThierry Reding2016-04-291-7/+125
| | | | | | | | | | | | | | | | | | Use the new XUSB pad controller binding on Tegra124. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | Merge branch 'for-4.7/xhci' into for-4.7/xusbThierry Reding2016-04-294-0/+1461
| |\ \
| * \ \ Merge branch 'for-4.7/pci' into for-4.7/xusbThierry Reding2016-04-292-22/+446
| |\ \ \
| * \ \ \ Merge branch 'for-4.7/phy' into for-4.7/xusbThierry Reding2016-04-2918-34/+6173
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*-. \ \ \ \ Merge branches 'tegra/pci' and 'tegra/usb' into next/lateArnd Bergmann2016-05-0924-56/+8080
|\ \ \ \ \ \ | | |_|_|/ / | |/| | | / | | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a prerequisite for enabling the Tegra XUSB, all the branches should be merged already at the time we get here. * tegra/pci: PCI: tegra: Support per-lane PHYs dt-bindings: pci: tegra: Update for per-lane PHYs phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs * tegra/usb: usb: xhci: tegra: Add Tegra210 support usb: xhci: Add NVIDIA Tegra XUSB controller driver dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller support dt-bindings: usb: Add NVIDIA Tegra XUSB controller binding phy: tegra: Add Tegra210 support phy: Add Tegra XUSB pad controller support dt-bindings: phy: tegra-xusb-padctl: Add Tegra210 support dt-bindings: phy: Add NVIDIA Tegra XUSB pad controller binding phy: core: Allow children node to be overridden clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs
| | * | | usb: xhci: tegra: Add Tegra210 supportThierry Reding2016-04-291-8/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Parameterize more parts of the driver and add support for Tegra210. Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | usb: xhci: Add NVIDIA Tegra XUSB controller driverThierry Reding2016-04-293-0/+1298
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the on-chip XUSB controller present on Tegra SoCs. This controller, when loaded with external firmware, exposes an interface compliant with xHCI. This driver loads the firmware, starts the controller, and is able to service host-specific messages sent by the controller's firmware. The controller also supports USB device mode as well as powergating of the SuperSpeed and host-controller logic when not in use, but support for these is not yet implemented. Based on work by: Ajay Gupta <ajayg@nvidia.com> Bharath Yadav <byadav@nvidia.com> Andrew Bresticker <abrestic@chromium.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | dt-bindings: usb: xhci-tegra: Add Tegra210 XUSB controller supportThierry Reding2016-04-291-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extend the Tegra XUSB controller device tree binding with Tegra210 support. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | dt-bindings: usb: Add NVIDIA Tegra XUSB controller bindingThierry Reding2016-04-291-0/+108
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add device-tree binding documentation for the XUSB controller present on Tegra124 and later SoCs. This controller supports USB 3.0 via an xHCI compliant interface. Based on work by Andrew Bresticker <abrestic@chromium.org>. Cc: Rob Herring <robh+dt@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Cc: Mathias Nyman <mathias.nyman@intel.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * | | Merge branch 'for-4.7/phy' into for-4.7/xhciThierry Reding2016-04-2918-34/+6173
| | |\ \ \ | | | |/ / | | |/| / | | | |/
| * | | PCI: tegra: Support per-lane PHYsThierry Reding2016-04-291-17/+227
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current XUSB pad controller bindings are insufficient to describe PHY devices attached to USB controllers. New bindings have been created to overcome these restrictions. As a side-effect each root port now is assigned a set of PHY devices, one for each lane associated with the root port. This has the benefit of allowing fine-grained control of the power management for each lane. Acked-by: Stephen Warren <swarren@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | | dt-bindings: pci: tegra: Update for per-lane PHYsThierry Reding2016-04-291-5/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The XUSB pad controller allows PCIe lanes to be controlled individually, providing fine-grained control over their power state. Previous attempts at describing the XUSB pad controller in DT had erroneously assumed that all PCIe lanes were driven by the same PHY, and hence the PCI host controller would reference only a single PHY. Moving to a representation of per-lane PHYs requires that the operating system driver for the PCI host controller have access to the set of PHY devices that make up the connection of each root port in order to power up and down all of the lanes as necessary. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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