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* ARM: EXYNOS: Migrate Exynos specific macros from plat to machSachin Kamat2014-05-262-60/+72
| | | | | | | | | Move Exynos specific macros to mach-exynos from plat-samsung to avoid unnecessary dependency on plat based header files. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: EXYNOS: Remove exynos_subsys registrationSachin Kamat2014-05-262-12/+0
| | | | | | | | 'exynos_subsys' has no users. Remove this code. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: EXYNOS: Remove duplicate lines in MakefileSachin Kamat2014-05-261-6/+1
| | | | | | | | Group all files compiled under common config option together. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* ARM: EXYNOS: use v7_exit_coherency_flush macro for cache disablingLeela Krishna Amudala2014-05-261-62/+1
| | | | | | | | | | | | | | | | | | A common macro v7_exit_coherency_flush available which does the below tasks in the seqeunce. -clearing C bit -clearing L1 cache -exit SMP -instruction and data synchronization So removing the local functions which does the same thing and use the macro instead. Signed-off-by: Leela Krishna Amudala <leela.krishna@linaro.org> Acked-by: Nicolas Pitre <nico@linaro.org> [cw00.choi@samsung.com: tested on exynos3250 based board] Tested-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Merge branch 'v3.16-next/clk-s3c24xx-3' into v3.16-next/cleanup-samsungKukjin Kim2014-05-2661-3223/+2655
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| * ARM: S3C24XX: fix merge conflictKukjin Kim2014-05-151-2/+0
| | | | | | | | | | | | | | Missed some changes during re-sorting this branch. So fixed it. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: remove SAMSUNG_CLOCK remnants after ccf conversionHeiko Stuebner2014-05-139-160/+0
| | | | | | | | | | | | | | | | This finally removes all remaining SAMSUNG_CLOCK conditional code from s3c24xx architectures. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: remove legacy clock codeHeiko Stuebner2014-05-1313-1122/+0
| | | | | | | | | | | | | | | | | | | | | | With the move to the common clock framework completed for s3c2410, s3c2440 and s3c2442, the legacy clock code for these machines can go away too. This also includes the legacy dclk code, as all legacy users are converted. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: convert s3c2410 to common clock frameworkHeiko Stuebner2014-05-1312-34/+67
| | | | | | | | | | | | | | | | | | | | | | | | Convert the machines using the s3c2410 to use the new driver based on the common clock framework instead of the legacy Samsung clock driver. As with the s3c244x, machines using the clkout output will need a fixup from someone with the hardware. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: convert s3c2440 and s3c2442 to common clock frameworkHeiko Stuebner2014-05-1312-36/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Some of the more esotheric machines will probably need a fixup, as they do strange things to the clkout outputs, that I did not really understand nor have the hardware to check. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: add platform code for conversion to the common clock frameworkHeiko Stuebner2014-05-136-1/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds the necessary init functions to init the clocks from the common clock framework and necessary CONFIG_SAMSUNG_CLOCK ifdefs around the legacy clock code. This also includes empty stubs for the *_setup_clocks functions that are called from the cpufreq driver on resume. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock controller driver for s3c2410, s3c2440 and s3c2442Heiko Stuebner2014-05-133-0/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver can handle the clock controllers of the socs mentioned above, as they share a common clock tree with only small differences. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As pll-rate-tables only the 12mhz variants are currently included. The original code was wrongly checking for 169mhz xti values [a 0 to much at the end], so the original 16mhz pll table would have never been included and its values are so obscure that I have no possibility to at least check their sane-ness. When using the formula from the manual the resulting frequency is near the table value but still slightly off. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * dt-bindings: add documentation for s3c2410 clock controllerHeiko Stuebner2014-05-131-0/+50
| | | | | | | | | | | | | | | | Describe the clock controller of s3c2410, s3c2440 and s3c2442. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: enable usage of common dclk if common clock framework is enabledHeiko Stuebner2014-05-139-5/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add platform device and select the correct implementation automatically depending on wether the old samsung_clock or the common clock framework is enabled. This is only done for machines already using the old dclk implementation, as everybody else should move to use dt anyway. The machine-specific settings for the external clocks will have to be set by somebody with knowledge about the specific hardware. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> [pebolle@tiscali.nl: pointed out typo and fixed] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock driver for external clock outputsHeiko Stuebner2014-05-092-0/+441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for controlling the external clock outputs of s3c24xx architectures including the dclk muxes and dividers. The driver at the moment only supports the legacy non-dt boards using these clock outputs. The clock-output control itself is part of the system-controller mainly controlled by the pinctrl drivers. So it should most likely be integrated there for dt platforms. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: cpufreq-utils: don't write raw values to MPLLCON when using ccfHeiko Stuebner2014-05-093-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The s3c24xx cpufreq driver needs to change the mpll speed and was doing this by writing raw values from a translation table into the MPLLCON register. Change this to use a regular clk_set_rate call when using the common clock framework and only write the raw value in the samsung_clock case. The s3c cpufreq driver does already aquire the mpll, so simply add a reference to struct s3c_cpufreq_config to let set_fvco access it. While struct clk is opaque the differenciation between samsung clock and common clock is kept, as the samsung-clock mpll clk does not implement a real set_rate. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: convert s3c2412 to common clock frameworkHeiko Stuebner2014-04-159-813/+40
| | | | | | | | | | | | | | | | | | Convert all machines using these cpus to use the ccf clock driver instead of the legacy Samsung clock implementation. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock controller driver for s3c2412Heiko Stuebner2014-04-153-0/+343
| | | | | | | | | | | | | | | | | | | | | | | | | | This driver can handle the clock controller in the s3c2412 soc. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * dt-bindings: add documentation for s3c2412 clock controllerHeiko Stuebner2014-04-151-0/+50
| | | | | | | | | | | | | | Describe the clock controller of the s3c2412. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add plls used by the early s3c24xx cpusHeiko Stuebner2014-04-152-0/+185
| | | | | | | | | | | | | | | | | | | | | | | | | | The manuals do not give them explicit names like in later socs, so more generic names with a s3c2410-prefix were used for them. As it was common to do so in the previous implementation, functionality to change the pll rate is already included. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Mike Turquette <mturquette@linaro.org> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: only store clock registers when old clock code is activeHeiko Stuebner2014-04-151-3/+10
| | | | | | | | | | | | | | | | | | | | The Samsung ccf driver already handles the save and restore of the clock registers on suspend and resume. The architecture code should not duplicate this when the ccf is active. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: Convert s3c2416 and s3c2443 to common clock frameworkHeiko Stuebner2014-04-1510-1114/+41
| | | | | | | | | | | | | | | | | | | | | | This converts the mentioned platforms to use the newly introduced driver for the common clock framework for them. With this the whole legacy clock structure can go away too. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: dts: add clock data for s3c2416Heiko Stuebner2014-04-152-0/+55
| | | | | | | | | | | | | | | | | | This adds the clock controller itself, the xti clock on the smdk2416 as well as the clock references in the individual device nodes. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * ARM: S3C24XX: prevent conflicts between ccf and non-ccf s3c24xx-socsHeiko Stuebner2014-04-152-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the conversion to the common-clock-framework is done in multiple steps, it is necessary to prevent conflicts between the different struct clk implementations. For this include the s3c24xx_setup_clocks function only when SAMSUNG_CLOCK is selected and make the socs we don't convert this time explicitly depend on SAMSUNG_CLOCK, which gets only selected automatically if COMMON_CLK is not enabled. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add clock-driver for s3c2416, s3c2443 and s3c2450Heiko Stuebner2014-04-154-0/+561
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The three SoCs share a common clock tree which only differs in the existence of some special clocks. As with all parts common to these three SoCs the driver is named after the s3c2443, as it was the first SoC introducing this structure and there exists no other label to describe this s3c24xx epoch. The clock structure is built according to the manuals of the included SoCs and might include changes in comparison to the previous clock structure. As an example the sclk_uart gate was never handled previously and the div_uart was made to be the clock used by the serial driver. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * dt-bindings: add binding for clock-controller of s3c2443 and followingHeiko Stuebner2014-04-151-0/+56
| | | | | | | | | | | | | | | | | | | | Starting with the s3c2443 the s3c24xx series got a new clock tree compared to the previous s3c24xx socs. This binding describes the clock controller found in the s3c2443, s3c2416 and s3c2450 socs. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add plls used by the s3c2443Heiko Stuebner2014-04-152-0/+74
| | | | | | | | | | | | | | | | | | | | The s3c2443 uses different plls that are not present yet. Therefore add the two needed types. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| * clk: samsung: add pll_6552 variant for s3c2416Heiko Stuebner2014-04-152-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the manual s3c2416 and s3c2450 use a pll 6552 and 6553 and while the pll_6553 matches exactly the one already implemented the pll_6552 differs to the one from the s3c64xx series. The change is solely in the bit locations of the mdiv and pdiv values. All calculations are the same for both implementatons and even the proposed divider-values for specific frequencies in the manuals are the same. Therefore implement a variant that simply uses the changed bit locations if necessary. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Tomasz Figa <t.figa@samsung.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: dts: Remove g2d_pd node for exynos5420Arun Kumar K2014-05-151-6/+0
| | | | | | | | | | | | | | | | | | | | G2D power domain also controls the CMU block of G2D. Since clock registers can be accessed anytime for viewing clk_summary, it can cause a system crash if g2d power domain is disabled. Signed-off-by: Arun Kumar K <arun.kk@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: dts: Remove mau_pd node for exynos5420Tushar Behera2014-05-151-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MAU powerdomain provides clocks for Audio sub-system block. This block comprises of the I2S audio controller, audio DMA blocks and Audio sub-system clock registers. Right now, there is no way to hook up power-domains with clock providers. During late boot when this power-domain gets disabled, we get following external abort. Unhandled fault: imprecise external abort (0x1406) at 0x00000000 Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000007 Signed-off-by: Tushar Behera <tushar.behera@linaro.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: exynos_defconfig: enable HS-I2C to fix for mmc partition mountSachin Kamat2014-05-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | High speed I2C is used on Exynos5 based SoCs. Enable it. The MMC partition for Root filesystem cannot be mounted without this enabling HS-I2C and regulators on many boards are connected HS-I2C bus so the regulators don't come by default without this. Actually, we are not able to get arndale-octa board to boot and mount an MMC partition without this change. Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org> Tested-by: Javi Merino <javi.merino@arm.com> [kgene.kim@samsung.com: modified description] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: dts: disable MDMA1 node for exynos5420Seungwon Jeon2014-05-152-12/+7
| | | | | | | | | | | | | | | | | | | | | | | | This change places MDMA1 in disabled node for Exynos5420. If MDMA1 region is configured with secure mode, it makes the boot failure with the following on smdk5420 board. ("Unhandled fault: imprecise external abort (0x1406) at 0x00000000") Thus, arndale-octa board don't need to do the same thing anymore. Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com> Tested-by: Javi Merino <javi.merino@arm.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | ARM: EXYNOS: fix the secondary CPU boot of exynos4212Kyungmin Park2014-05-151-1/+14
| | | | | | | | | | | | | | | | | | | | | | This patch fixes the offset of CPU boot address and changes the parameter of smc call for SMC_CMD_CPU1BOOT command on exynos4212. Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* | Linux 3.15-rc4v3.15-rc4Linus Torvalds2014-05-041-1/+1
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* | Merge tag 'locks-v3.15-3' of git://git.samba.org/jlayton/linuxLinus Torvalds2014-05-041-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | Pull file locking change from Jeff Layton: "Only an email address change to the MAINTAINERS file" * tag 'locks-v3.15-3' of git://git.samba.org/jlayton/linux: MAINTAINERS: email address change for Jeff Layton
| * | MAINTAINERS: email address change for Jeff LaytonJeff Layton2014-04-301-1/+1
| | | | | | | | | | | | | | | | | | jlayton@redhat.com -> jlayton@poochiereds.net Signed-off-by: Jeff Layton <jlayton@poochiereds.net>
* | | Merge tag 'arm64-fixes' of ↵Linus Torvalds2014-05-048-7/+50
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 fixes from Catalin Marinas: "These are mostly arm64 fixes with an additional arm(64) platform fix for the initialisation of vexpress clocks (the latter only affecting arm64; the arch/arm64 code is SoC agnostic and does not rely on early SoC-specific calls) - vexpress platform clocks initialisation moved earlier following the arm64 move of of_clk_init() call in a previous commit - Default DMA ops changed to non-coherent to preserve compatibility with 32-bit ARM DT files. The "dma-coherent" property can be used to explicitly mark a device coherent. The Applied Micro DT file has been updated to avoid DMA cache maintenance for the X-Gene SATA controller (the only arm64 related driver with such assumption in -rc mainline) - Fixmap correction for earlyprintk - kern_addr_valid() fix for huge pages" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: vexpress: Initialise the sysregs before setting up the clocks arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherent arm64: Use bus notifiers to set per-device coherent DMA ops arm64: Make default dma_ops to be noncoherent arm64: fixmap: fix missing sub-page offset for earlyprintk arm64: Fix for the arm64 kern_addr_valid() function
| * | | vexpress: Initialise the sysregs before setting up the clocksCatalin Marinas2014-05-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Following arm64 commit bc3ee18a7a57 (arm64: init: Move of_clk_init to time_init()), vexpress_osc_of_setup() is called via of_clk_init() long before initcalls are issued. Initialising the vexpress oscillators requires the vespress sysregs to be already initialised, so this patch adds an explicit call to vexpress_sysreg_of_early_init() in vexpress oscillator setup function. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Tested-by: Will Deacon <will.deacon@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Tested-by: Pawel Moll <pawel.moll@arm.com> Acked-by: Pawel Moll <pawel.moll@arm.com> Cc: Mike Turquette <mturquette@linaro.org>
| * | | arm64: Mark the Applied Micro X-Gene SATA controller as DMA coherentCatalin Marinas2014-05-032-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the default DMA ops for arm64 are non-coherent, mark the X-Gene controller explicitly as dma-coherent to avoid additional cache maintenance. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com> Cc: Loc Ho <lho@apm.com>
| * | | arm64: Use bus notifiers to set per-device coherent DMA opsCatalin Marinas2014-05-032-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recently, the default DMA ops have been changed to non-coherent for alignment with 32-bit ARM platforms (and DT files). This patch adds bus notifiers to be able to set the coherent DMA ops (with no cache maintenance) for devices explicitly marked as coherent via the "dma-coherent" DT property. Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | arm64: Make default dma_ops to be noncoherentRitesh Harjani2014-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently arm64 dma_ops is by default made coherent which makes it opposite in default policy from arm. Make default dma_ops to be noncoherent (same as arm), as currently there aren't any dma-capable drivers which assumes coherent ops Signed-off-by: Ritesh Harjani <ritesh.harjani@gmail.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | arm64: fixmap: fix missing sub-page offset for earlyprintkMarc Zyngier2014-05-032-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit d57c33c5daa4 (add generic fixmap.h) added (among other similar things) set_fixmap_io to deal with early ioremap of devices. More recently, commit bf4b558eba92 (arm64: add early_ioremap support) converted the arm64 earlyprintk to use set_fixmap_io. A side effect of this conversion is that my virtual machines have stopped booting when I pass "earlyprintk=uart8250-8bit,0x3f8" to the guest kernel. Turns out that the new earlyprintk code doesn't care at all about sub-page offsets, and just assumes that the earlyprintk device will be page-aligned. Obviously, that doesn't play well with the above example. Further investigation shows that set_fixmap_io uses __set_fixmap instead of __set_fixmap_offset. A fix is to introduce a set_fixmap_offset_io that uses the latter, and to remove the superflous call to fix_to_virt (which only returns the value that set_fixmap_io has already given us). With this applied, my VMs are back in business. Tested on a Cortex-A57 platform with kvmtool as platform emulation. Cc: Will Deacon <will.deacon@arm.com> Acked-by: Mark Salter <msalter@redhat.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| * | | arm64: Fix for the arm64 kern_addr_valid() functionDave Anderson2014-05-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix for the arm64 kern_addr_valid() function to recognize virtual addresses in the kernel logical memory map. The function fails as written because it does not check whether the addresses in that region are mapped at the pmd level to 2MB or 512MB pages, continues the page table walk to the pte level, and issues a garbage value to pfn_valid(). Tested on 4K-page and 64K-page kernels. Signed-off-by: Dave Anderson <anderson@redhat.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
* | | | Merge tag 'scsi-fixes' of ↵Linus Torvalds2014-05-042-2/+5
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi Pull SCSI fixes from James Bottomley: "This is two patches both fixing bugs in drivers (virtio-scsi and mpt2sas) causing an oops in certain circumstances" * tag 'scsi-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: [SCSI] virtio-scsi: Skip setting affinity on uninitialized vq [SCSI] mpt2sas: Don't disable device twice at suspend.
| * | | | [SCSI] virtio-scsi: Skip setting affinity on uninitialized vqFam Zheng2014-04-281-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | virtscsi_init calls virtscsi_remove_vqs on err, even before initializing the vqs. The latter calls virtscsi_set_affinity, so let's check the pointer there before setting affinity on it. This fixes a panic when setting device's num_queues=2 on RHEL 6.5: qemu-system-x86_64 ... \ -device virtio-scsi-pci,id=scsi0,addr=0x13,...,num_queues=2 \ -drive file=/stor/vm/dummy.raw,id=drive-scsi-disk,... \ -device scsi-hd,drive=drive-scsi-disk,... [ 0.354734] scsi0 : Virtio SCSI HBA [ 0.379504] BUG: unable to handle kernel NULL pointer dereference at 0000000000000020 [ 0.380141] IP: [<ffffffff814741ef>] __virtscsi_set_affinity+0x4f/0x120 [ 0.380141] PGD 0 [ 0.380141] Oops: 0000 [#1] SMP [ 0.380141] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 3.14.0+ #5 [ 0.380141] Hardware name: Red Hat KVM, BIOS 0.5.1 01/01/2007 [ 0.380141] task: ffff88003c9f0000 ti: ffff88003c9f8000 task.ti: ffff88003c9f8000 [ 0.380141] RIP: 0010:[<ffffffff814741ef>] [<ffffffff814741ef>] __virtscsi_set_affinity+0x4f/0x120 [ 0.380141] RSP: 0000:ffff88003c9f9c08 EFLAGS: 00010256 [ 0.380141] RAX: 0000000000000000 RBX: ffff88003c3a9d40 RCX: 0000000000001070 [ 0.380141] RDX: 0000000000000002 RSI: 0000000000000000 RDI: 0000000000000000 [ 0.380141] RBP: ffff88003c9f9c28 R08: 00000000000136c0 R09: ffff88003c801c00 [ 0.380141] R10: ffffffff81475229 R11: 0000000000000008 R12: 0000000000000000 [ 0.380141] R13: ffffffff81cc7ca8 R14: ffff88003cac3d40 R15: ffff88003cac37a0 [ 0.380141] FS: 0000000000000000(0000) GS:ffff88003e400000(0000) knlGS:0000000000000000 [ 0.380141] CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b [ 0.380141] CR2: 0000000000000020 CR3: 0000000001c0e000 CR4: 00000000000006f0 [ 0.380141] Stack: [ 0.380141] ffff88003c3a9d40 0000000000000000 ffff88003cac3d80 ffff88003cac3d40 [ 0.380141] ffff88003c9f9c48 ffffffff814742e8 ffff88003c26d000 ffff88003c26d000 [ 0.380141] ffff88003c9f9c68 ffffffff81474321 ffff88003c26d000 ffff88003c3a9d40 [ 0.380141] Call Trace: [ 0.380141] [<ffffffff814742e8>] virtscsi_set_affinity+0x28/0x40 [ 0.380141] [<ffffffff81474321>] virtscsi_remove_vqs+0x21/0x50 [ 0.380141] [<ffffffff81475231>] virtscsi_init+0x91/0x240 [ 0.380141] [<ffffffff81365290>] ? vp_get+0x50/0x70 [ 0.380141] [<ffffffff81475544>] virtscsi_probe+0xf4/0x280 [ 0.380141] [<ffffffff81363ea5>] virtio_dev_probe+0xe5/0x140 [ 0.380141] [<ffffffff8144c669>] driver_probe_device+0x89/0x230 [ 0.380141] [<ffffffff8144c8ab>] __driver_attach+0x9b/0xa0 [ 0.380141] [<ffffffff8144c810>] ? driver_probe_device+0x230/0x230 [ 0.380141] [<ffffffff8144c810>] ? driver_probe_device+0x230/0x230 [ 0.380141] [<ffffffff8144ac1c>] bus_for_each_dev+0x8c/0xb0 [ 0.380141] [<ffffffff8144c499>] driver_attach+0x19/0x20 [ 0.380141] [<ffffffff8144bf28>] bus_add_driver+0x198/0x220 [ 0.380141] [<ffffffff8144ce9f>] driver_register+0x5f/0xf0 [ 0.380141] [<ffffffff81d27c91>] ? spi_transport_init+0x79/0x79 [ 0.380141] [<ffffffff8136403b>] register_virtio_driver+0x1b/0x30 [ 0.380141] [<ffffffff81d27d19>] init+0x88/0xd6 [ 0.380141] [<ffffffff81d27c18>] ? scsi_init_procfs+0x5b/0x5b [ 0.380141] [<ffffffff81ce88a7>] do_one_initcall+0x7f/0x10a [ 0.380141] [<ffffffff81ce8aa7>] kernel_init_freeable+0x14a/0x1de [ 0.380141] [<ffffffff81ce8b3b>] ? kernel_init_freeable+0x1de/0x1de [ 0.380141] [<ffffffff817dec20>] ? rest_init+0x80/0x80 [ 0.380141] [<ffffffff817dec29>] kernel_init+0x9/0xf0 [ 0.380141] [<ffffffff817e68fc>] ret_from_fork+0x7c/0xb0 [ 0.380141] [<ffffffff817dec20>] ? rest_init+0x80/0x80 [ 0.380141] RIP [<ffffffff814741ef>] __virtscsi_set_affinity+0x4f/0x120 [ 0.380141] RSP <ffff88003c9f9c08> [ 0.380141] CR2: 0000000000000020 [ 0.380141] ---[ end trace 8074b70c3d5e1d73 ]--- [ 0.475018] Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 [ 0.475018] [ 0.475068] Kernel Offset: 0x0 from 0xffffffff81000000 (relocation range: 0xffffffff80000000-0xffffffff9fffffff) [ 0.475068] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x00000009 [jejb: checkpatch fixes] Signed-off-by: Fam Zheng <famz@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Cc: stable@vger.kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
| * | | | [SCSI] mpt2sas: Don't disable device twice at suspend.Tyler Stachecki2014-04-281-1/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On suspend, _scsih_suspend calls mpt2sas_base_free_resources, which in turn calls pci_disable_device if the device is enabled prior to suspending. However, _scsih_suspend also calls pci_disable_device itself. Thus, in the event that the device is enabled prior to suspending, pci_disable_device will be called twice. This patch removes the duplicate call to pci_disable_device in _scsi_suspend as it is both unnecessary and results in a kernel oops. Signed-off-by: Tyler Stachecki <tstache1@binghamton.edu> Cc: stable@vger.kernel.org Signed-off-by: James Bottomley <JBottomley@Parallels.com>
* | | | Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2014-05-037-37/+42
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq fixes from Thomas Gleixner: "This udpate delivers: - A fix for dynamic interrupt allocation on x86 which is required to exclude the GSI interrupts from the dynamic allocatable range. This was detected with the newfangled tablet SoCs which have GPIOs and therefor allocate a range of interrupts. The MSI allocations already excluded the GSI range, so we never noticed before. - The last missing set_irq_affinity() repair, which was delayed due to testing issues - A few bug fixes for the armada SoC interrupt controller - A memory allocation fix for the TI crossbar interrupt controller - A trivial kernel-doc warning fix" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: irq-crossbar: Not allocating enough memory irqchip: armanda: Sanitize set_irq_affinity() genirq: x86: Ensure that dynamic irq allocation does not conflict linux/interrupt.h: fix new kernel-doc warnings irqchip: armada-370-xp: Fix releasing of MSIs irqchip: armada-370-xp: implement the ->check_device() msi_chip operation irqchip: armada-370-xp: fix invalid cast of signed value into unsigned variable
| * \ \ \ Merge tag 'mvebu-irqchip-fixes-3.15' of git://git.infradead.org/linux-mvebu ↵Thomas Gleixner2014-04-291-3/+14
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into irq/urgent Bugfixes for armada-370-xp SoC from Jason Cooper: * Fix invalid cast (signed to unsigned) * Add missing ->check_device() msi_chip op * Fix releasing of MSIs
| | * | | | irqchip: armada-370-xp: Fix releasing of MSIsNeil Greatorex2014-04-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Store the value of d->hwirq in a local variable as the real value is wiped out by calling irq_dispose_mapping. Without this patch, the armada_370_xp_free_msi function would always free MSI#0, no matter what was passed to it. Fixes: 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 ('irqchip: armada-370-xp: implement MSI support') Cc: <stable@vger.kernel.org> # v3.13+ Signed-off-by: Neil Greatorex <neil@fatboyfat.co.uk> Link: https://lkml.kernel.org/r/1397823593-1932-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-4-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| | * | | | irqchip: armada-370-xp: implement the ->check_device() msi_chip operationThomas Petazzoni2014-04-201-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, we were leaving the ->check_device() msi_chip operation empty, which leads the PCI core to believe that we support both MSI and MSI-X. In fact, we do not support MSI-X, so we have to tell this to the PCI core by providing an implementation of this operation. Fixes: 31f614edb726fcc4d5aa0f2895fbdec9b04a3ca4 ('irqchip: armada-370-xp: implement MSI support') Cc: <stable@vger.kernel.org> # v3.13+ Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397823593-1932-3-git-send-email-thomas.petazzoni@free-electrons.com Tested-by: Neil Greatorex <neil@fatboyfat.co.uk> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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