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| | * drm/i915: cache the last object lookup during pin_and_relocate()Chris Wilson2010-10-201-171/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The most frequent relocation within a batchbuffer is a contiguous sequence of vertex buffer relocations, for which we can virtually eliminate the drm_gem_object_lookup() overhead by caching the last handle to object translation. In doing so we refactor the pin and relocate retry loop out of do_execbuffer into its own helper function and so improve the error paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Do interrupible mutex lock first to avoid locking for unreferenceChris Wilson2010-10-191-113/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the primarily consumers of the i915 driver is X, a large signal driven application. Frequently when writing into the buffers, there is a pending signal which causes us not to take the interruptible lock but then we need to take that same lock around the object unreference. By rearranging the code to do the interruptible lock as the first check, we can avoid the frequent additional locking around the unreference. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drivers: gpu: drm: i915: Fix a typo.Andrea Gelmini2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | "userpace" -> "userspace" Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * agp/intel: Also add B43.1 to list of supported devicesChris Wilson2010-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This was a missing piece from 41a5142 that dropped recognition of the AGP module for the second B43 variant. Reported-by: Stefan Bader <stefan.bader@canonical.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| | * drm/i915: rearrange mutex acquisition for preadChris Wilson2010-10-191-56/+43
| | | | | | | | | | | | | | | | | | ... to avoid the double acquisition along fast[er] paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Rearrange acquisition of mutex during pwriteChris Wilson2010-10-191-105/+65
| | | | | | | | | | | | | | | | | | | | | | | | ... to avoid reacquiring it to drop the object reference count on exit. Note we have to make sure we now drop (and reacquire) the lock around acquiring the mm semaphore on the slow paths. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Attempt to prefault user pages for pread/pwriteChris Wilson2010-10-191-14/+19
| | | | | | | | | | | | | | | | | | ... in the hope that it makes the atomic fast paths more likely. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Avoid taking the mutex for dropping the refcnt upon creationChris Wilson2010-10-191-4/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | After allocation a handle for the fresh object, we know that we can safely drop the refcnt without triggering a free so we do not need the mutex. Strangely, this mutex acquisition is the one that appears on driver profiles. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Perform relocations in CPU domain [if in CPU domain]Chris Wilson2010-10-191-26/+29
| | | | | | | | | | | | | | | | | | | | | Avoid an early eviction of the batch buffer into the uncached GTT domain, and so do the relocation fixup in cacheable memory. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Avoid vmallocing a buffer for the relocationsChris Wilson2010-10-191-149/+75
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ... perform an access validation check up front instead and copy them in on-demand, during i915_gem_object_pin_and_relocate(). As around 20% of the CPU overhead may be spent inside vmalloc for the relocation entries when submitting an execbuffer [for x11perf -aa10text], the savings are considerable and result in around a 10% throughput increase [for glyphs]. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/hdmi: Add 'force_audio' propertyChris Wilson2010-10-191-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the user to override the detection of the sink's audio capabilities from EDID. Not all sinks support the required EDID level to specify whether they handle audio over the display connection, so allow the user to enable it manually. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/sdvo: Add 'force_audio' propertyChris Wilson2010-10-191-2/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the user to override the detection of the sink's audio capabilities from EDID. Not all sinks support the required EDID level to specify whether they handle audio over the display connection, so allow the user to enable it manually. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/dp: Add 'force_audio' propertyChris Wilson2010-10-191-5/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | | Allow the user to override the detection of the sink's audio capabilities from EDID. Not all sinks support the required EDID level to specify whether they handle audio over the display connection, so allow the user to enable it manually. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Enable HDMI audio for monitor with audio supportZhenyu Wang2010-10-191-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | Rely on monitor's audio capability to turn on audio output for HDMI. Tested-by: Wu Fengguang <fengguang.wu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Enable DisplayPort audioZhenyu Wang2010-10-191-21/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | This will turn on DP audio output by checking monitor's audio capability. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> [ickle: rebase onto recent changes and rearranged for clarity] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/edid: add helper function to detect monitor audio capabilityZhenyu Wang2010-10-192-14/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To help to determine if digital display port needs to enable audio output or not. This one adds a helper to get monitor's audio capability via EDID CEA extension block. Tested-by: Wu Fengguang <fengguang.wu@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Adam Jackson <ajax@redhat.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Initialize panel timing registers if VBIOS did notBryan Freed2010-10-193-4/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The time between start of the pixel clock and backlight enable is a basic panel timing constraint. If the Panel Power On/Off registers are found to be 0, assume we are booting without VBIOS initialization and set these registers to something reasonable. Change-Id: Ibed6cc10d46bf52fd92e0beb25ae3525b5eef99d Signed-off-by: Bryan Freed <bfreed@chromium.org> [ickle: rearranged into a separate function to distinguish its role from simply parsing the VBIOS tables.] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Sleep whilst waiting for the ringChris Wilson2010-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If userspace is submitting so many long running batches that the ring becomes full, throttle by sleeping for a 1ms before checking for free space. Simply yielding was causing excessive scheduler overhead whilst making no progress. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Fix GPIO pin to register mappingZhenyu Wang2010-10-191-0/+1
| | | | | | | | | | | | | | | | | | | | | In i2c GPIO fallback, index 6 is reserved for nothing. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: restore fixed FDI link rate on SandybridgeChris Wilson2010-10-191-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | FDI_PLL_BIOS_0 register is for Ironlake only, don't apply to Sandybridge. Original-patch-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915/dp: down the DP link even if the reg indicates it's already downJesse Barnes2010-10-191-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the PLL may still be on, and the training pattern may not be correct. Fixes suspend/resume on my PCH eDP test system. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: minor merge conflict and silence the compiler] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Fix oops on HWS unloadDaniel Vetter2010-10-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freeing the Hardware Status Page was writing to the HWS register in order to disable the GPU writing to the HWS page. Unfortunately, we were writing to the mmio register after unmapping the register space, hence the oops. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * drm/i915: Remove duplicate set of ADPA definitionsChris Wilson2010-10-191-7/+1
| | | | | | | | | | | | Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * Revert "drm/i915: Prevent module unload to avoid random memory corruption"Chris Wilson2010-10-191-3/+0
| | | | | | | | | | | | | | | | | | | | | This reverts commit 6939a5aca7cfada279a24c307e772f33104fca20. Daniel Vetter supplied a set of fixes for all the module unload bugs he could trigger on his machines, so let the fun recommence!
| | * Merge remote branch 'airlied/drm-core-next' into tmpChris Wilson2010-10-19435-1797/+3335
| | |\
| | * | drm/i915: Update hotplug interrupts register definitions for SandybridgeYuanhan Liu2010-10-082-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Sandybridge, the bit definition for hotplug on SDE has changed, so update the code to new definition. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30378 Cc: stable@kernel.org Signed-off-by: Yuanhan Liu <yuanhan.liu@intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/crt: Make sure the hotplug interrupt is enabledYuanhan Liu2010-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After disabling the hotplug interrupts for VGA detection on Ironlake, be sure to re-enable them again afterwards. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30378 Signed-off-by: Yuanhan Liu <yuanhan.liu@intel.com> Cc: stable@kernel.org Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: diasable clock gating for the panel power sequencerJesse Barnes2010-10-082-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Needed on Ibex Peak and Cougar Point or the panel won't always come on. Cc: stable@kernel.org Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: make eDP PLL functions work as advertisedJesse Barnes2010-10-081-2/+4
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: don't bother with DP PLL for PCH attached eDPJesse Barnes2010-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We don't use the CPU DP PLL with PCH attached eDP panels, so don't bother to enable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: use VBT provided eDP params if availableJesse Barnes2010-10-081-57/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We can skip most of the link training step if we use the VBT provided values. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: cache eDP DPCD dataJesse Barnes2010-10-082-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cache the first 4 bytes of DPCD data in the eDP case. It's unlikely to change and can save us some trouble at link training time. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: don't program FDI RX/TX in mode_setJesse Barnes2010-10-081-21/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do this later (and more properly) when we enable FDI, so we don't need to do it here. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: fix ironlake CRTC enable/disableJesse Barnes2010-10-081-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Wait for vblank after enabling a pipe, make the error messages more informative, and wait for the pipe to turn off when we disable it. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: use DPLL_DVO_HIGH_SPEED for PCH eDPJesse Barnes2010-10-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As with other PCH DP connections. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: use 120MHz refclk in PCH eDP case tooJesse Barnes2010-10-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPU eDP needs a different reference clock than PCH eDP, which uses the standard PCH refclk of 120MHz. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: fix PCH eDP SSC supportJesse Barnes2010-10-081-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SSC on PCH eDP if possible. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: added a posting read of PCH_DREF_CONTROL before the udelay] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: add Ironlake clock gating workaround for FDI link trainingJesse Barnes2010-10-082-0/+9
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: fetch eDP configuration data from the VBTJesse Barnes2010-10-083-20/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We need to use some of these values in eDP configurations, so be sure to fetch them and store them in the i915 private structure. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: add _DSM supportJesse Barnes2010-10-085-0/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The _DSM method on the integrated graphics device can tell us which connectors are muxable, so add support for making the call and parsing out the connector info. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> [ickle: fix compiler warnings for using uninitialized 'result' and downgrade error message for non-switchable devices] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: eDP power sequencing fixesJesse Barnes2010-10-082-45/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the panel before adjusting eDP link params, make sure the panel is idle after powering it on before proceeding with other activity, delay backlight enable to avoid visible flicker. Also avoid using VDD per hw team recommendation; it can conflict with the builtin panel power sequencing logic and lead to panel power sequencing failures. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: fix CPU vs PCH eDP confusionJesse Barnes2010-10-081-35/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | FDI training needs to done and idle for PCH eDP and before we turn the pipes on, and various eDP checks need to account for PCH attached eDP. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: remove broken intel_pch_has_edp functionJesse Barnes2010-10-083-23/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we set the output type of PCH attached eDP panels to INTEL_OUTPUT_eDP this function would never return true when it should. It's been replaced by working functions. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: add eDP checking functions for the display codeJesse Barnes2010-10-082-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The display code needs to distinguish between CPU and PCH attached eDP panels, so add some helpers to handle that. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: correct eDP lane count and bppJesse Barnes2010-10-081-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the old check we'd never set lane_count or bpp to different values on PCH attached eDP panels. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: remove redundant is_pch_edp checksJesse Barnes2010-10-081-20/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If is_edp is true, is_pch_edp will always be true. So limit the calls to the latter function to places where the distinction actually matters. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915/dp: convert eDP checks to functions and documentJesse Barnes2010-10-081-35/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most of the PCH eDP checks are redundant, so document the functions in preparation for removing most of the calls. Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Wait for pending flips on the GPUChris Wilson2010-10-072-48/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, if a batch buffer refers to an object with a pending flip, then we sleep until that pending flip is completed (unpinned and signalled). This is so that a flip can be queued and the user can continue rendering to the backbuffer oblivious to whether the buffer is still pinned as the scan out. (The kernel arbitrating at the last moment to stall the batch and wait until the buffer is unpinned and replaced as the front buffer.) As we only have a queue depth of 1, we can simply wait for the current pending flip to complete and continue rendering. We can achieve this with a single WAIT_FOR_EVENT command inserted into the ring buffer prior to executing the batch, *without* stalling the client. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
| | * | drm/i915: Free hardware status page on unload when physically mappedKeith Packard2010-10-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A physically mapped hardware status page is allocated at driver load time but was never freed. Call the existing code to free this page at driver unload time on hardware which uses this kind. Signed-off-by: Keith Packard <keithp@keithp.com> [ickle: call before tearing down registers on KMS-only path, as pointed out by Dave Airlie] Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
| * | | drm/ttm: Optimize delayed buffer destructionThomas Hellstrom2010-10-211-64/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit replaces the ttm_bo_cleanup_ref function with two new functions. One for the case where the bo is not yet on the delayed destroy list, and one for the case where the bo was on the delayed destroy list, at least at the time of call. This makes it possible to optimize the two cases somewhat. It also enables the possibility to directly destroy buffers on the delayed delete list when they are about to be evicted or swapped out. Currently they were only evicted / swapped and destruction was left for the delayed buffer destruction thread. Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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