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* ARM: mvebu: Relocate PCIe node in Armada 370 RD boardEzequiel Garcia2013-08-091-16/+16
| | | | | | | | The pcie-controller node needs to be relocated according the MBus DT binding, since it's now a child of the mbus-compatible node. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Fix AXP-WiFi-AP DT for MBUS DT bindingEzequiel Garcia2013-08-071-25/+25
| | | | | | | | | The ranges property needs to be changed to use the new MBus DT binding. Also, the pcie-controller node needs to be relocated as according the MBus DT binding, it's now a child of the mbus-compatible node. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: add support for the AXP WiFi AP boardThomas Petazzoni2013-08-072-0/+165
| | | | | | | | | | | | | | | | | The AXP WiFi AP board is a Marvell platform based on the Armada XP MV78230 SoC. It has two mini-PCIe connectors, one USB 3.0 port powered by a USB 3.0 controller on PCIe, two Ethernet ports, 1 GB of RAM, 1 GB of NAND, 16 MB of SPI flash, one SATA port and one button, two UARTs Successfully tested: USB 3.0 port, the mini-PCIe connectors, SPI flash, Ethernet ports, SATA port, button, UART. Untested: NAND flash, due to lack of mainline support for the Armada 370/XP NAND controller for now. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Seif Mazareeb <seif@marvell.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: use dts pre-processor for mv78230Jason Cooper2013-08-071-1/+1
| | | | Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: Adapt to the new device tree layoutThomas Petazzoni2013-08-061-36/+109
| | | | | | | | | | | | | | | The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Cc: devicetree@vger.kernel.org Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Add devicetree bindingEzequiel Garcia2013-08-061-0/+276
| | | | | | | | | | | | | | | | | | | | Introduce the devicetree binding for the mvebu MBus driver avaiable in the mvebu SoCs (Armada 370/XP, Kirkwood, Dove, ...). This binding provides an accurate model of the SoC address space, and allows to declare the address and size of the decoding windows the MBus needs to access the peripherals, together with the target ID and attribute for those windows. The binding is composed of two required nodes: one for the MBus bus and one for the MBus controller. Cc: devicetree@vger.kernel.org Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Rob Herring <rob.herring@calxeda.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Relocate PCIe device tree nodesEzequiel Garcia2013-08-0612-136/+163
| | | | | | | | | | | | | | | | | | | | | Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of the ocp node, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. In addition, we encode the PCIe memory and I/O apertures in the MBus node, according to the MBus DT binding specification. The choice made is 0xe0000000-0xf0000000 for memory space, and 0xf200000-0xf2100000 for I/O space. These apertures can be changed in each per-board DT file. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Introduce MBUS_IDEzequiel Garcia2013-08-061-0/+2
| | | | | | | | | | This macro is used to define window's target ID and attribute cells for the MBus ranges entries. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Introduce MBus DT nodeEzequiel Garcia2013-08-061-0/+10
| | | | | | | | | | Add a minimal MBus node, just to allow the MBus driver to probe. Follow-up patches will migrate the rest of the nodes appropriately. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Use the preprocessor on device tree filesEzequiel Garcia2013-08-0634-58/+58
| | | | | | | Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Split DT and legacy MBus initializationEzequiel Garcia2013-08-062-4/+5
| | | | | | | | | | | This commit replaces the legacy MBus initialization with the new DT-based in Kirkwood. For boards that are not yet converted to DT, we keep the legacy initialization. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Relocate Armada 370/XP PCIe device tree nodesEzequiel Garcia2013-08-069-542/+612
| | | | | | | | | | | | | | | | | | Now that mbus has been added to the device tree, it's possible to move the PCIe nodes out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Moving the PCIe nodes, we now need to introduce an extra cell to encode the window target ID and attribute. Since this depends on the PCIe port, we split the ranges translation entries, to correspond to each MBus window. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Relocate Armada 370/XP DeviceBus device tree nodesEzequiel Garcia2013-08-064-138/+140
| | | | | | | | | | | Now that mbus has been added to the device tree, it's possible to move the DeviceBus out of internal registers, placing it directly below the mbus. This is a more accurate representation of the hardware. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add BootROM to Armada 370/XP device treeEzequiel Garcia2013-08-068-6/+22
| | | | | | | | | | | In order to access the SoC BootROM, we need to declare a mapping (through a ranges property). The mbus driver will use this property to allocate a suitable address decoding window. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Add MBus to Armada 370/XP device treeEzequiel Garcia2013-08-069-16/+23
| | | | | | | | | | | | | | | | | | | | The Armada 370/XP SoC family has a completely configurable address space handled by the MBus controller. This patch introduces the device tree layout of MBus, making the 'soc' node as mbus-compatible. Since every peripheral/controller is a child of this 'soc' node, this makes all of them sit behind the mbus, thus describing the hardware accurately. A translation entry has been added for the internal-regs mapping. This can't be done in the common armada-370-xp.dtsi because A370 and AXP have different addressing width. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Use the preprocessor on Armada 370/XP device tree filesEzequiel Garcia2013-08-0610-10/+10
| | | | | | | Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Initialize MBus using the DT bindingEzequiel Garcia2013-08-061-33/+1
| | | | | | | | | | | | | | Now that the mbus device tree binding has been introduced, we can switch over to it. Also, and since the initialization of the mbus driver is quite fundamental for the system to work properly, this patch adds a BUG() in case mbus fails to initialize. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mvebu: Remove the harcoded BootROM window allocationEzequiel Garcia2013-08-061-1/+24
| | | | | | | | | | The address decoding window to access the BootROM should not be allocated programatically, but instead declared in the device tree. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Factorize Armada 370/XP data structuresThomas Petazzoni2013-08-061-11/+3
| | | | | | | | | | | These structures were only different in the mapping tables. Now that those tables have been removed, it doesn't make any sense to keep different structures. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Update main descriptionThomas Petazzoni2013-08-061-7/+3
| | | | | | | | | | | After replacing the MBus name-based by the new ID-based API let's fix the general description of the driver at the beginning of the file. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Remove name -> target, attribute mapping tablesThomas Petazzoni2013-08-061-143/+7
| | | | | | | | | | | This tables were used together with the name-based MBus window creation API. Since that's has been removed, we can also remove the tables. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Remove the no longer used name-based APIThomas Petazzoni2013-08-062-43/+0
| | | | | | | | | | Now that every user of the deprecated name-based API has been converted to using the ID-based API, let's remove the former one. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: Check valid base address before port setupEzequiel Garcia2013-08-061-0/+2
| | | | | | | | | | | | This driver does not fail to probe when it cannot obtain a port base address. Therefore, add a check for NULL base address before setting up the port, which prevents a kernel panic in such cases. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI: mvebu: Adapt to the new device tree layoutThomas Petazzoni2013-08-061-29/+84
| | | | | | | | | | | | | | The new device tree layout encodes the window's target ID and attribute in the PCIe controller node's ranges property. This allows to parse such entries to obtain such information and use the recently introduced MBus API to create the windows, instead of using the current name based scheme. Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Add new API for the PCIe memory and IO apertureEzequiel Garcia2013-08-062-0/+53
| | | | | | | | | | | | | | | We add two optional properties to the MBus DT binding, to encode the PCIe memory and IO aperture. This allows such information to be retrieved by -for instance- the pci driver to allocate the MBus decoding windows. Correspondingly, and in order to retrieve this information, we add two new APIs. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Add static window allocation to the DT bindingEzequiel Garcia2013-08-061-1/+126
| | | | | | | | | | | | This patch adds static window allocation to the device tree binding. Each first-child of the mbus-compatible node, with a suitable 'ranges' property, declaring an address translation, will trigger an address decoding window allocation. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Introduce device tree bindingEzequiel Garcia2013-08-062-0/+50
| | | | | | | | | | | | | This patch adds the most fundamental device-tree initialization. We only introduce what's required to be able to probe the mvebu-mbus driver from the DT. Follow-up patches will extend the device tree binding, allowing to describe static address decoding windows. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Factor out initialization detailsEzequiel Garcia2013-08-061-17/+30
| | | | | | | | | | | | | We introduce a common initialization function mvebu_mbus_common_init() that will be used by both legacy and device-tree initialization code. This patch is an intermediate step, which will allow to introduce the DT binding for this driver in a less intrusive way. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: dove: Move to ID based window creationThomas Petazzoni2013-08-061-23/+45
| | | | | | | | | | | | | With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: orion5x: Move to ID based window creationThomas Petazzoni2013-08-0622-70/+137
| | | | | | | | | | | | | With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: mv78xx0: Move to ID based window creationThomas Petazzoni2013-08-061-12/+11
| | | | | | | | | | | | | With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* ARM: kirkwood: Move to ID based MBus window creationThomas Petazzoni2013-08-062-20/+38
| | | | | | | | | | | | | With the introduction of the ID based MBus API, it's better to switch to use it instead of the current name based scheme. This will allow to deprecate the name based API, once every user is removed. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* bus: mvebu-mbus: Add new API for window creationThomas Petazzoni2013-08-062-8/+31
| | | | | | | | | | | We add an API to create MBus address decoding windows from the target ID and attribute. This function will be used later and deprecate the current name based scheme. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: Remove address decoding window workaroundEzequiel Garcia2013-08-061-62/+2
| | | | | | | | | | | | | Now that mbus device tree binding has been introduced, remove the address decoding window management from this driver. A suitable 'ranges' entry should be added to the devbus-compatible node in the device tree, as described by the mbus binding documentation. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* Linux 3.11-rc1v3.11-rc1Linus Torvalds2013-07-142-1604/+883
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* Merge branch 'slab/for-linus' of ↵Linus Torvalds2013-07-148-69/+121
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/penberg/linux Pull slab update from Pekka Enberg: "Highlights: - Fix for boot-time problems on some architectures due to init_lock_keys() not respecting kmalloc_caches boundaries (Christoph Lameter) - CONFIG_SLUB_CPU_PARTIAL requested by RT folks (Joonsoo Kim) - Fix for excessive slab freelist draining (Wanpeng Li) - SLUB and SLOB cleanups and fixes (various people)" I ended up editing the branch, and this avoids two commits at the end that were immediately reverted, and I instead just applied the oneliner fix in between myself. * 'slab/for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/penberg/linux slub: Check for page NULL before doing the node_match check mm/slab: Give s_next and s_stop slab-specific names slob: Check for NULL pointer before calling ctor() slub: Make cpu partial slab support configurable slab: add kmalloc() to kernel API documentation slab: fix init_lock_keys slob: use DIV_ROUND_UP where possible slub: do not put a slab to cpu partial list when cpu_partial is 0 mm/slub: Use node_nr_slabs and node_nr_objs in get_slabinfo mm/slub: Drop unnecessary nr_partials mm/slab: Fix /proc/slabinfo unwriteable for slab mm/slab: Sharing s_next and s_stop between slab and slub mm/slab: Fix drain freelist excessively slob: Rework #ifdeffery in slab.h mm, slab: moved kmem_cache_alloc_node comment to correct place
| * slub: Check for page NULL before doing the node_match checkSteven Rostedt2013-07-141-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the -rt kernel (mrg), we hit the following dump: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180 PGD a2d39067 PUD b1641067 PMD 0 Oops: 0000 [#1] PREEMPT SMP Modules linked in: sunrpc cpufreq_ondemand ipv6 tg3 joydev sg serio_raw pcspkr k8temp amd64_edac_mod edac_core i2c_piix4 e100 mii shpchp ext4 mbcache jbd2 sd_mod crc_t10dif sr_mod cdrom sata_svw ata_generic pata_acpi pata_serverworks radeon ttm drm_kms_helper drm hwmon i2c_algo_bit i2c_core dm_mirror dm_region_hash dm_log dm_mod CPU 3 Pid: 20878, comm: hackbench Not tainted 3.6.11-rt25.14.el6rt.x86_64 #1 empty empty/Tyan Transport GT24-B3992 RIP: 0010:[<ffffffff811573f1>] [<ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180 RSP: 0018:ffff8800a9b17d70 EFLAGS: 00010213 RAX: 0000000000000000 RBX: 0000000001200011 RCX: ffff8800a06d8000 RDX: 0000000004d92a03 RSI: 00000000000000d0 RDI: ffff88013b805500 RBP: ffff8800a9b17dc0 R08: ffff88023fd14d10 R09: ffffffff81041cbd R10: 00007f4e3f06e9d0 R11: 0000000000000246 R12: ffff88013b805500 R13: ffff8801ff46af40 R14: 0000000000000001 R15: 0000000000000000 FS: 00007f4e3f06e700(0000) GS:ffff88023fd00000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 000000008005003b CR2: 0000000000000000 CR3: 00000000a2d3a000 CR4: 00000000000007e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process hackbench (pid: 20878, threadinfo ffff8800a9b16000, task ffff8800a06d8000) Stack: ffff8800a9b17da0 ffffffff81202e08 ffff8800a9b17de0 000000d001200011 0000000001200011 0000000001200011 0000000000000000 0000000000000000 00007f4e3f06e9d0 0000000000000000 ffff8800a9b17e60 ffffffff81041cbd Call Trace: [<ffffffff81202e08>] ? current_has_perm+0x68/0x80 [<ffffffff81041cbd>] copy_process+0xdd/0x15b0 [<ffffffff810a2125>] ? rt_up_read+0x25/0x30 [<ffffffff8104369a>] do_fork+0x5a/0x360 [<ffffffff8107c66b>] ? migrate_enable+0xeb/0x220 [<ffffffff8100b068>] sys_clone+0x28/0x30 [<ffffffff81527423>] stub_clone+0x13/0x20 [<ffffffff81527152>] ? system_call_fastpath+0x16/0x1b Code: 89 fc 89 75 cc 41 89 d6 4d 8b 04 24 65 4c 03 04 25 48 ae 00 00 49 8b 50 08 4d 8b 28 49 8b 40 10 4d 85 ed 74 12 41 83 fe ff 74 27 <48> 8b 00 48 c1 e8 3a 41 39 c6 74 1b 8b 75 cc 4c 89 c9 44 89 f2 RIP [<ffffffff811573f1>] kmem_cache_alloc_node+0x51/0x180 RSP <ffff8800a9b17d70> CR2: 0000000000000000 ---[ end trace 0000000000000002 ]--- Now, this uses SLUB pretty much unmodified, but as it is the -rt kernel with CONFIG_PREEMPT_RT set, spinlocks are mutexes, although they do disable migration. But the SLUB code is relatively lockless, and the spin_locks there are raw_spin_locks (not converted to mutexes), thus I believe this bug can happen in mainline without -rt features. The -rt patch is just good at triggering mainline bugs ;-) Anyway, looking at where this crashed, it seems that the page variable can be NULL when passed to the node_match() function (which does not check if it is NULL). When this happens we get the above panic. As page is only used in slab_alloc() to check if the node matches, if it's NULL I'm assuming that we can say it doesn't and call the __slab_alloc() code. Is this a correct assumption? Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Pekka Enberg <penberg@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
| * mm/slab: Give s_next and s_stop slab-specific namesWanpeng Li2013-07-083-8/+8
| | | | | | | | | | | | | | | | Give s_next and s_stop slab-specific names instead of exporting "s_next" and "s_stop". Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slob: Check for NULL pointer before calling ctor()Steven Rostedt2013-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While doing some code inspection, I noticed that the slob constructor method can be called with a NULL pointer. If memory is tight and slob fails to allocate with slob_alloc() or slob_new_pages() it still calls the ctor() method with a NULL pointer. Looking at the first ctor() method I found, I noticed that it can not handle a NULL pointer (I'm sure others probably can't either): static void sighand_ctor(void *data) { struct sighand_struct *sighand = data; spin_lock_init(&sighand->siglock); init_waitqueue_head(&sighand->signalfd_wqh); } The solution is to only call the ctor() method if allocation succeeded. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Steven Rostedt <rostedt@goodmis.org> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slub: Make cpu partial slab support configurableJoonsoo Kim2013-07-072-6/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | CPU partial support can introduce level of indeterminism that is not wanted in certain context (like a realtime kernel). Make it configurable. This patch is based on Christoph Lameter's "slub: Make cpu partial slab support configurable V2". Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slab: add kmalloc() to kernel API documentationMichael Opdenacker2013-07-072-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment, kmalloc() isn't even listed in the kernel API documentation (DocBook/kernel-api.html after running "make htmldocs"). Another issue is that the documentation for kmalloc_node() refers to kcalloc()'s documentation to describe its 'flags' parameter, while kcalloc() refered to kmalloc()'s documentation, which doesn't exist! This patch is a proposed fix for this. It also removes the documentation for kmalloc() in include/linux/slob_def.h which isn't included to generate the documentation anyway. This way, kmalloc() is described in only one place. Acked-by: Christoph Lameter <cl@linux.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Michael Opdenacker <michael.opdenacker@free-electrons.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slab: fix init_lock_keysChristoph Lameter2013-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some architectures (e.g. powerpc built with CONFIG_PPC_256K_PAGES=y CONFIG_FORCE_MAX_ZONEORDER=11) get PAGE_SHIFT + MAX_ORDER > 26. In 3.10 kernels, CONFIG_LOCKDEP=y with PAGE_SHIFT + MAX_ORDER > 26 makes init_lock_keys() dereference beyond kmalloc_caches[26]. This leads to an unbootable system (kernel panic at initializing SLAB) if one of kmalloc_caches[26...PAGE_SHIFT+MAX_ORDER-1] is not NULL. Fix this by making sure that init_lock_keys() does not dereference beyond kmalloc_caches[26] arrays. Signed-off-by: Christoph Lameter <cl@linux.com> Reported-by: Tetsuo Handa <penguin-kernel@I-Love.SAKURA.ne.jp> Cc: Pekka Enberg <penberg@kernel.org> Cc: <stable@vger.kernel.org> [3.10.x] Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slob: use DIV_ROUND_UP where possibleSasha Levin2013-07-071-1/+1
| | | | | | | | | | | | Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Sasha Levin <sasha.levin@oracle.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slub: do not put a slab to cpu partial list when cpu_partial is 0Joonsoo Kim2013-07-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | In free path, we don't check number of cpu_partial, so one slab can be linked in cpu partial list even if cpu_partial is 0. To prevent this, we should check number of cpu_partial in put_cpu_partial(). Acked-by: Christoph Lameeter <cl@linux.com> Reviewed-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Joonsoo Kim <iamjoonsoo.kim@lge.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * mm/slub: Use node_nr_slabs and node_nr_objs in get_slabinfoWanpeng Li2013-07-071-2/+2
| | | | | | | | | | | | | | | | | | Use existing interface node_nr_slabs and node_nr_objs to get nr_slabs and nr_objs. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * mm/slub: Drop unnecessary nr_partialsWanpeng Li2013-07-071-2/+0
| | | | | | | | | | | | | | | | This patch remove unused nr_partials variable. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * mm/slab: Fix /proc/slabinfo unwriteable for slabWanpeng Li2013-07-071-1/+9
| | | | | | | | | | | | | | | | | | | | | | Slab have some tunables like limit, batchcount, and sharedfactor can be tuned through function slabinfo_write. Commit (b7454ad3: mm/sl[au]b: Move slabinfo processing to slab_common.c) uncorrectly change /proc/slabinfo unwriteable for slab, this patch fix it by revert to original mode. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * mm/slab: Sharing s_next and s_stop between slab and slubWanpeng Li2013-07-073-12/+5
| | | | | | | | | | | | | | | | This patch shares s_next and s_stop between slab and slub. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * mm/slab: Fix drain freelist excessivelyWanpeng Li2013-07-071-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The drain_freelist is called to drain slabs_free lists for cache reap, cache shrink, memory hotplug callback etc. The tofree parameter should be the number of slab to free instead of the number of slab objects to free. This patch fix the callers that pass # of objects. Make sure they pass # of slabs. Acked-by: Christoph Lameter <cl@linux.com> Signed-off-by: Wanpeng Li <liwanp@linux.vnet.ibm.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
| * slob: Rework #ifdeffery in slab.hChristoph Lameter2013-06-181-11/+28
| | | | | | | | | | | | | | | | | | Make the SLOB specific stuff harmonize more with the way the other allocators do it. Create the typical kmalloc constants for that purpose. SLOB does not support it but the constants help us avoid #ifdefs. Signed-off-by: Christoph Lameter <cl@linux.com> Signed-off-by: Pekka Enberg <penberg@kernel.org>
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