diff options
Diffstat (limited to 'include')
48 files changed, 2642 insertions, 76 deletions
diff --git a/include/asm-arm/arch-ixp23xx/platform.h b/include/asm-arm/arch-ixp23xx/platform.h index 56e16d6..db8aa30 100644 --- a/include/asm-arm/arch-ixp23xx/platform.h +++ b/include/asm-arm/arch-ixp23xx/platform.h @@ -14,17 +14,17 @@ #ifndef __ASSEMBLY__ -extern inline unsigned long ixp2000_reg_read(volatile void *reg) +static inline unsigned long ixp2000_reg_read(volatile void *reg) { return *((volatile unsigned long *)reg); } -extern inline void ixp2000_reg_write(volatile void *reg, unsigned long val) +static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) { *((volatile unsigned long *)reg) = val; } -extern inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) +static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) { *((volatile unsigned long *)reg) = val; } diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h index bf30cbd..b943d3a 100644 --- a/include/asm-arm/arch-ns9xxx/clock.h +++ b/include/asm-arm/arch-ns9xxx/clock.h @@ -19,7 +19,7 @@ static inline u32 ns9xxx_systemclock(void) __attribute__((const)); static inline u32 ns9xxx_systemclock(void) { - u32 pll = SYS_PLL; + u32 pll = __raw_readl(SYS_PLL); /* * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in @@ -46,8 +46,8 @@ static inline u32 ns9xxx_systemclock(void) * * Fine. */ - return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1) - >> REGGET(pll, SYS_PLL, FS); + return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1) + >> REGGETIM(pll, SYS_PLL, FS); } static inline u32 ns9xxx_cpuclock(void) __attribute__((const)); diff --git a/include/asm-arm/arch-ns9xxx/gpio.h b/include/asm-arm/arch-ns9xxx/gpio.h new file mode 100644 index 0000000..adbca08 --- /dev/null +++ b/include/asm-arm/arch-ns9xxx/gpio.h @@ -0,0 +1,47 @@ +/* + * include/asm-arm/arch-ns9xxx/gpio.h + * + * Copyright (C) 2007 by Digi International Inc. + * All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. +*/ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#include <asm/errno.h> + +int gpio_request(unsigned gpio, const char *label); + +void gpio_free(unsigned gpio); + +int ns9xxx_gpio_configure(unsigned gpio, int inv, int func); + +int gpio_direction_input(unsigned gpio); + +int gpio_direction_output(unsigned gpio, int value); + +int gpio_get_value(unsigned gpio); + +void gpio_set_value(unsigned gpio, int value); + +/* + * ns9xxx can use gpio pins to trigger an irq, but it's not generic + * enough to be supported by the gpio_to_irq/irq_to_gpio interface + */ +static inline int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +/* get the cansleep() stubs */ +#include <asm-generic/gpio.h> + +#endif /* ifndef __ASM_ARCH_GPIO_H */ diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h index 2560055..0b7b346 100644 --- a/include/asm-arm/arch-ns9xxx/hardware.h +++ b/include/asm-arm/arch-ns9xxx/hardware.h @@ -27,42 +27,53 @@ #define io_v2p(x) ((((x) & 0x0f000000) << 4) \ + ((x) & 0x00ffffff)) +#define __REGSHIFT(mask) ((mask) & (-(mask))) + #define __REGBIT(bit) ((u32)1 << (bit)) #define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit)) -#define __REGVAL(mask, value) (((value) * ((mask) & (-(mask))) & (mask))) +#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask)) #ifndef __ASSEMBLY__ -# define __REG(x) (*((volatile u32 *)io_p2v((x)))) -# define __REG2(x, y) (*((volatile u32 *)io_p2v((x)) + (y))) +# define __REG(x) ((void __iomem __force *)io_p2v((x))) +# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y))) -# define __REGB(x) (*((volatile u8 *)io_p2v((x)))) -# define __REGB2(x) (*((volatile u8 *)io_p2v((x)) + (y))) +# define __REGSET(var, field, value) \ + ((var) = (((var) & ~((field) & ~(value))) | (value))) # define REGSET(var, reg, field, value) \ - ((var) = (((var) \ - & ~(reg ## _ ## field & \ - ~ reg ## _ ## field ## _ ## value)) \ - | (reg ## _ ## field ## _ ## value))) + __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value) + +# define REGSET_IDX(var, reg, field, idx, value) \ + __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx))) # define REGSETIM(var, reg, field, value) \ - ((var) = (((var) \ - & ~(reg ## _ ## field & \ - ~(__REGVAL(reg ## _ ## field, value)))) \ - | (__REGVAL(reg ## _ ## field, value)))) + __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value))) + +# define REGSETIM_IDX(var, reg, field, idx, value) \ + __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value))) + +# define __REGGET(var, field) \ + (((var) & (field))) # define REGGET(var, reg, field) \ - ((var & (reg ## _ ## field)) / \ - ((reg ## _ ## field) & (-(reg ## _ ## field)))) + __REGGET(var, reg ## _ ## field) + +# define REGGET_IDX(var, reg, field, idx) \ + __REGGET(var, reg ## _ ## field((idx))) + +# define REGGETIM(var, reg, field) \ + __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field) + +# define REGGETIM_IDX(var, reg, field, idx) \ + __REGGET(var, reg ## _ ## field((idx))) / \ + __REGSHIFT(reg ## _ ## field((idx))) #else # define __REG(x) io_p2v(x) # define __REG2(x, y) io_p2v((x) + (y)) -# define __REGB(x) __REG((x)) -# define __REGB2(x, y) __REG2((x), (y)) - #endif #endif /* ifndef __ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h index c3dc532..afa3a9d 100644 --- a/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h +++ b/include/asm-arm/arch-ns9xxx/regs-board-a9m9750dev.h @@ -18,7 +18,7 @@ #define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10) #define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18) -#define FPGA_IER __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x50) -#define FPGA_ISR __REGB(NS9XXX_CSxSTAT_PHYS(0) + 0x60) +#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50) +#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60) #endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */ diff --git a/include/asm-arm/arch-ns9xxx/system.h b/include/asm-arm/arch-ns9xxx/system.h index e3cd4d3..c1082bd 100644 --- a/include/asm-arm/arch-ns9xxx/system.h +++ b/include/asm-arm/arch-ns9xxx/system.h @@ -24,9 +24,9 @@ static inline void arch_reset(char mode) { u32 reg; - reg = SYS_PLL >> 16; + reg = __raw_readl(SYS_PLL) >> 16; REGSET(reg, SYS_PLL, SWC, YES); - SYS_PLL = reg; + __raw_writel(reg, SYS_PLL); BUG(); } diff --git a/include/asm-arm/arch-omap/blizzard.h b/include/asm-arm/arch-omap/blizzard.h new file mode 100644 index 0000000..8d160f1 --- /dev/null +++ b/include/asm-arm/arch-omap/blizzard.h @@ -0,0 +1,12 @@ +#ifndef _BLIZZARD_H +#define _BLIZZARD_H + +struct blizzard_platform_data { + void (*power_up)(struct device *dev); + void (*power_down)(struct device *dev); + unsigned long (*get_clock_rate)(struct device *dev); + + unsigned te_connected : 1; +}; + +#endif diff --git a/include/asm-arm/arch-omap/board-2430sdp.h b/include/asm-arm/arch-omap/board-2430sdp.h new file mode 100644 index 0000000..e9c65ce --- /dev/null +++ b/include/asm-arm/arch-omap/board-2430sdp.h @@ -0,0 +1,44 @@ +/* + * linux/include/asm-arm/arch-omap/board-2430sdp.h + * + * Hardware definitions for TI OMAP2430 SDP board. + * + * Based on board-h4.h by Dirk Behme <dirk.behme@de.bosch.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __ASM_ARCH_OMAP_2430SDP_H +#define __ASM_ARCH_OMAP_2430SDP_H + +/* Placeholder for 2430SDP specific defines */ +#define OMAP24XX_ETHR_START 0x08000300 +#define OMAP24XX_ETHR_GPIO_IRQ 149 +#define SDP2430_CS0_BASE 0x04000000 + +#define TWL4030_IRQNUM INT_24XX_SYS_NIRQ + +/* TWL4030 Primary Interrupt Handler (PIH) interrupts */ +#define IH_TWL4030_BASE IH_BOARD_BASE +#define IH_TWL4030_END (IH_TWL4030_BASE+8) +#define NR_IRQS (IH_TWL4030_END) + +#endif /* __ASM_ARCH_OMAP_2430SDP_H */ diff --git a/include/asm-arm/arch-omap/board-palmte.h b/include/asm-arm/arch-omap/board-palmte.h new file mode 100644 index 0000000..cd22035 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmte.h @@ -0,0 +1,34 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmte.h + * + * Hardware definitions for the Palm Tungsten E device. + * + * Maintainters : http://palmtelinux.sf.net + * palmtelinux-developpers@lists.sf.net + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMTE_H +#define __OMAP_BOARD_PALMTE_H + +#include <asm/arch/gpio.h> + +#define PALMTE_USBDETECT_GPIO 0 +#define PALMTE_USB_OR_DC_GPIO 1 +#define PALMTE_TSC_GPIO 4 +#define PALMTE_PINTDAV_GPIO 6 +#define PALMTE_MMC_WP_GPIO 8 +#define PALMTE_MMC_POWER_GPIO 9 +#define PALMTE_HDQ_GPIO 11 +#define PALMTE_HEADPHONES_GPIO 14 +#define PALMTE_SPEAKER_GPIO 15 +#define PALMTE_DC_GPIO OMAP_MPUIO(2) +#define PALMTE_MMC_SWITCH_GPIO OMAP_MPUIO(4) +#define PALMTE_MMC1_GPIO OMAP_MPUIO(6) +#define PALMTE_MMC2_GPIO OMAP_MPUIO(7) +#define PALMTE_MMC3_GPIO OMAP_MPUIO(11) + +#endif /* __OMAP_BOARD_PALMTE_H */ diff --git a/include/asm-arm/arch-omap/board-palmtt.h b/include/asm-arm/arch-omap/board-palmtt.h new file mode 100644 index 0000000..d9590b0 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmtt.h @@ -0,0 +1,23 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmte.h + * + * Hardware definitions for the Palm Tungsten|T device. + * + * Maintainters : Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMTT_H +#define __OMAP_BOARD_PALMTT_H + +#define PALMTT_USBDETECT_GPIO 0 +#define PALMTT_CABLE_GPIO 1 +#define PALMTT_LED_GPIO 3 +#define PALMTT_PENIRQ_GPIO 6 +#define PALMTT_MMC_WP_GPIO 8 +#define PALMTT_HDQ_GPIO 11 + +#endif /* __OMAP_BOARD_PALMTT_H */ diff --git a/include/asm-arm/arch-omap/board-palmz71.h b/include/asm-arm/arch-omap/board-palmz71.h new file mode 100644 index 0000000..1252a85 --- /dev/null +++ b/include/asm-arm/arch-omap/board-palmz71.h @@ -0,0 +1,26 @@ +/* + * linux/include/asm-arm/arch-omap/board-palmz71.h + * + * Hardware definitions for the Palm Zire71 device. + * + * Maintainters : Marek Vasut <marek.vasut@gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP_BOARD_PALMZ71_H +#define __OMAP_BOARD_PALMZ71_H + +#define PALMZ71_USBDETECT_GPIO 0 +#define PALMZ71_PENIRQ_GPIO 6 +#define PALMZ71_MMC_WP_GPIO 8 +#define PALMZ71_HDQ_GPIO 11 + +#define PALMZ71_HOTSYNC_GPIO OMAP_MPUIO(1) +#define PALMZ71_CABLE_GPIO OMAP_MPUIO(2) +#define PALMZ71_SLIDER_GPIO OMAP_MPUIO(3) +#define PALMZ71_MMC_IN_GPIO OMAP_MPUIO(4) + +#endif /* __OMAP_BOARD_PALMZ71_H */ diff --git a/include/asm-arm/arch-omap/board-sx1.h b/include/asm-arm/arch-omap/board-sx1.h new file mode 100644 index 0000000..2bb8dd6 --- /dev/null +++ b/include/asm-arm/arch-omap/board-sx1.h @@ -0,0 +1,46 @@ +/* + * Siemens SX1 board definitions + * + * Copyright: Vovan888 at gmail com + * + * This package is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED + * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. + */ + +#ifndef __ASM_ARCH_SX1_I2C_CHIPS_H +#define __ASM_ARCH_SX1_I2C_CHIPS_H + +#define SOFIA_MAX_LIGHT_VAL 0x2B + +#define SOFIA_I2C_ADDR 0x32 +/* Sofia reg 3 bits masks */ +#define SOFIA_POWER1_REG 0x03 + +#define SOFIA_USB_POWER 0x01 +#define SOFIA_MMC_POWER 0x04 +#define SOFIA_BLUETOOTH_POWER 0x08 +#define SOFIA_MMILIGHT_POWER 0x20 + +#define SOFIA_POWER2_REG 0x04 +#define SOFIA_BACKLIGHT_REG 0x06 +#define SOFIA_KEYLIGHT_REG 0x07 +#define SOFIA_DIMMING_REG 0x09 + + +/* Function Prototypes for SX1 devices control on I2C bus */ + +int sx1_setbacklight(u8 backlight); +int sx1_getbacklight(u8 *backlight); +int sx1_setkeylight(u8 keylight); +int sx1_getkeylight(u8 *keylight); + +int sx1_setmmipower(u8 onoff); +int sx1_setusbpower(u8 onoff); +int sx1_setmmcpower(u8 onoff); + +#endif /* __ASM_ARCH_SX1_I2C_CHIPS_H */ diff --git a/include/asm-arm/arch-omap/board.h b/include/asm-arm/arch-omap/board.h index 031672c..db44c5d1 100644 --- a/include/asm-arm/arch-omap/board.h +++ b/include/asm-arm/arch-omap/board.h @@ -179,4 +179,8 @@ extern const void *omap_get_var_config(u16 tag, size_t *len); extern struct omap_board_config_kernel *omap_board_config; extern int omap_board_config_size; + +/* for TI reference platforms sharing the same debug card */ +extern int debug_card_init(u32 addr, unsigned gpio); + #endif diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index f777419..f33b467 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h @@ -417,7 +417,6 @@ extern void omap_free_lcd_dma(void); extern void omap_setup_lcd_dma(void); extern void omap_enable_lcd_dma(void); extern void omap_stop_lcd_dma(void); -extern int omap_lcd_dma_ext_running(void); extern void omap_set_lcd_dma_ext_controller(int external); extern void omap_set_lcd_dma_single_transfer(int single); extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres, diff --git a/include/asm-arm/arch-omap/eac.h b/include/asm-arm/arch-omap/eac.h new file mode 100644 index 0000000..6662cb0 --- /dev/null +++ b/include/asm-arm/arch-omap/eac.h @@ -0,0 +1,101 @@ +/* + * linux/include/asm-arm/arch-omap2/eac.h + * + * Defines for Enhanced Audio Controller + * + * Contact: Jarkko Nikula <jarkko.nikula@nokia.com> + * + * Copyright (C) 2006 Nokia Corporation + * Copyright (C) 2004 Texas Instruments, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA + * 02110-1301 USA + * + */ + +#ifndef __ASM_ARM_ARCH_OMAP2_EAC_H +#define __ASM_ARM_ARCH_OMAP2_EAC_H + +#include <asm/arch/io.h> +#include <asm/arch/hardware.h> +#include <asm/irq.h> + +#include <sound/driver.h> +#include <sound/core.h> + +/* master codec clock source */ +#define EAC_MCLK_EXT_MASK 0x100 +enum eac_mclk_src { + EAC_MCLK_INT_11290000, /* internal 96 MHz / 8.5 = 11.29 Mhz */ + EAC_MCLK_EXT_11289600 = EAC_MCLK_EXT_MASK, + EAC_MCLK_EXT_12288000, + EAC_MCLK_EXT_2x11289600, + EAC_MCLK_EXT_2x12288000, +}; + +/* codec port interface mode */ +enum eac_codec_mode { + EAC_CODEC_PCM, + EAC_CODEC_AC97, + EAC_CODEC_I2S_MASTER, /* codec port, I.e. EAC is the master */ + EAC_CODEC_I2S_SLAVE, +}; + +/* configuration structure for I2S mode */ +struct eac_i2s_conf { + /* if enabled, then first data slot (left channel) is signaled as + * positive level of frame sync EAC.AC_FS */ + unsigned polarity_changed_mode:1; + /* if enabled, then serial data starts one clock cycle after the + * of EAC.AC_FS for first audio slot */ + unsigned sync_delay_enable:1; +}; + +/* configuration structure for EAC codec port */ +struct eac_codec { + enum eac_mclk_src mclk_src; + + enum eac_codec_mode codec_mode; + union { + struct eac_i2s_conf i2s; + } codec_conf; + + int default_rate; /* audio sampling rate */ + + int (* set_power)(void *private_data, int dac, int adc); + int (* register_controls)(void *private_data, + struct snd_card *card); + const char *short_name; + + void *private_data; +}; + +/* structure for passing platform dependent data to the EAC driver */ +struct eac_platform_data { + int (* init)(struct device *eac_dev); + void (* cleanup)(struct device *eac_dev); + /* these callbacks are used to configure & control external MCLK + * source. NULL if not used */ + int (* enable_ext_clocks)(struct device *eac_dev); + void (* disable_ext_clocks)(struct device *eac_dev); +}; + +extern void omap_init_eac(struct eac_platform_data *pdata); + +extern int eac_register_codec(struct device *eac_dev, struct eac_codec *codec); +extern void eac_unregister_codec(struct device *eac_dev); + +extern int eac_set_mode(struct device *eac_dev, int play, int rec); + +#endif /* __ASM_ARM_ARCH_OMAP2_EAC_H */ diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h index 995cc83..6a8e07f 100644 --- a/include/asm-arm/arch-omap/gpmc.h +++ b/include/asm-arm/arch-omap/gpmc.h @@ -23,9 +23,10 @@ #define GPMC_CS_NAND_DATA 0x24 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) -#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 20) +#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) +#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) @@ -80,6 +81,8 @@ struct gpmc_timings { }; extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); +extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); +extern unsigned long gpmc_get_fclk_period(void); extern void gpmc_cs_write_reg(int cs, int idx, u32 val); extern u32 gpmc_cs_read_reg(int cs, int idx); diff --git a/include/asm-arm/arch-omap/hardware.h b/include/asm-arm/arch-omap/hardware.h index e225f4f..da57209 100644 --- a/include/asm-arm/arch-omap/hardware.h +++ b/include/asm-arm/arch-omap/hardware.h @@ -318,6 +318,10 @@ #include "board-h4.h" #endif +#ifdef CONFIG_MACH_OMAP_2430SDP +#include "board-2430sdp.h" +#endif + #ifdef CONFIG_MACH_OMAP_APOLLON #include "board-apollon.h" #endif @@ -330,6 +334,22 @@ #include "board-voiceblue.h" #endif +#ifdef CONFIG_MACH_OMAP_PALMTE +#include "board-palmte.h" +#endif + +#ifdef CONFIG_MACH_OMAP_PALMZ71 +#include "board-palmz71.h" +#endif + +#ifdef CONFIG_MACH_OMAP_PALMTT +#include "board-palmtt.h" +#endif + +#ifdef CONFIG_MACH_SX1 +#include "board-sx1.h" +#endif + #endif /* !__ASSEMBLER__ */ #endif /* __ASM_ARCH_OMAP_HARDWARE_H */ diff --git a/include/asm-arm/arch-omap/io.h b/include/asm-arm/arch-omap/io.h index 4aca7e3..289082d 100644 --- a/include/asm-arm/arch-omap/io.h +++ b/include/asm-arm/arch-omap/io.h @@ -72,6 +72,16 @@ #define L4_24XX_PHYS L4_24XX_BASE /* 0x48000000 */ #define L4_24XX_VIRT 0xd8000000 #define L4_24XX_SIZE SZ_1M /* 1MB of 128MB used, want 1MB sect */ + +#ifdef CONFIG_ARCH_OMAP2430 +#define L4_WK_243X_PHYS L4_WK_243X_BASE /* 0x49000000 */ +#define L4_WK_243X_VIRT 0xd9000000 +#define L4_WK_243X_SIZE SZ_1M +#define OMAP243X_GPMC_PHYS OMAP243X_GPMC_BASE /* 0x49000000 */ +#define OMAP243X_GPMC_VIRT 0xFE000000 +#define OMAP243X_GPMC_SIZE SZ_1M +#endif + #define IO_OFFSET 0x90000000 #define IO_ADDRESS(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ #define io_p2v(pa) ((pa) + IO_OFFSET) /* Works for L3 and L4 */ diff --git a/include/asm-arm/arch-omap/menelaus.h b/include/asm-arm/arch-omap/menelaus.h index 82d276a..69ed7ee 100644 --- a/include/asm-arm/arch-omap/menelaus.h +++ b/include/asm-arm/arch-omap/menelaus.h @@ -7,6 +7,12 @@ #ifndef __ASM_ARCH_MENELAUS_H #define __ASM_ARCH_MENELAUS_H +struct device; + +struct menelaus_platform_data { + int (* late_init)(struct device *dev); +}; + extern int menelaus_register_mmc_callback(void (*callback)(void *data, u8 card_mask), void *data); extern void menelaus_unregister_mmc_callback(void); @@ -20,6 +26,19 @@ extern int menelaus_set_vaux(unsigned int mV); extern int menelaus_set_vdcdc(int dcdc, unsigned int mV); extern int menelaus_set_slot_sel(int enable); extern int menelaus_get_slot_pin_states(void); +extern int menelaus_set_vcore_sw(unsigned int mV); +extern int menelaus_set_vcore_hw(unsigned int roof_mV, unsigned int floor_mV); + +#define EN_VPLL_SLEEP (1 << 7) +#define EN_VMMC_SLEEP (1 << 6) +#define EN_VAUX_SLEEP (1 << 5) +#define EN_VIO_SLEEP (1 << 4) +#define EN_VMEM_SLEEP (1 << 3) +#define EN_DC3_SLEEP (1 << 2) +#define EN_DC2_SLEEP (1 << 1) +#define EN_VC_SLEEP (1 << 0) + +extern int menelaus_set_regulator_sleep(int enable, u32 val); #if defined(CONFIG_ARCH_OMAP24XX) && defined(CONFIG_MENELAUS) #define omap_has_menelaus() 1 @@ -28,4 +47,3 @@ extern int menelaus_get_slot_pin_states(void); #endif #endif - diff --git a/include/asm-arm/arch-omap/mmc.h b/include/asm-arm/arch-omap/mmc.h new file mode 100644 index 0000000..b70e37b --- /dev/null +++ b/include/asm-arm/arch-omap/mmc.h @@ -0,0 +1,66 @@ +/* + * MMC definitions for OMAP2 + * + * Copyright (C) 2006 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __OMAP2_MMC_H +#define __OMAP2_MMC_H + +#include <linux/types.h> +#include <linux/device.h> +#include <linux/mmc/host.h> + +#define OMAP_MMC_MAX_SLOTS 2 + +struct omap_mmc_platform_data { + unsigned enabled:1; + /* number of slots on board */ + unsigned nr_slots:2; + /* nomux means "standard" muxing is wrong on this board, and that + * board-specific code handled it before common init logic. + */ + unsigned nomux:1; + /* 4 wire signaling is optional, and is only used for SD/SDIO and + * MMCv4 */ + unsigned wire4:1; + /* set if your board has components or wiring that limits the + * maximum frequency on the MMC bus */ + unsigned int max_freq; + + /* switch the bus to a new slot */ + int (* switch_slot)(struct device *dev, int slot); + /* initialize board-specific MMC functionality, can be NULL if + * not supported */ + int (* init)(struct device *dev); + void (* cleanup)(struct device *dev); + + struct omap_mmc_slot_data { + int (* set_bus_mode)(struct device *dev, int slot, int bus_mode); + int (* set_power)(struct device *dev, int slot, int power_on, int vdd); + int (* get_ro)(struct device *dev, int slot); + + /* return MMC cover switch state, can be NULL if not supported. + * + * possible return values: + * 0 - open + * 1 - closed + */ + int (* get_cover_state)(struct device *dev, int slot); + + const char *name; + u32 ocr_mask; + } slots[OMAP_MMC_MAX_SLOTS]; +}; + +extern void omap_set_mmc_info(int host, const struct omap_mmc_platform_data *info); + +/* called from board-specific card detection service routine */ +extern void omap_mmc_notify_card_detect(struct device *dev, int slot, int detected); +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, int is_closed); + +#endif diff --git a/include/asm-arm/arch-omap/mux.h b/include/asm-arm/arch-omap/mux.h index f1ec2ed..b8fff50 100644 --- a/include/asm-arm/arch-omap/mux.h +++ b/include/asm-arm/arch-omap/mux.h @@ -406,6 +406,29 @@ enum omap1xxx_index { V10_1610_CF_IREQ, W10_1610_CF_RESET, W11_1610_CF_CD1, + + /* parallel camera */ + J15_1610_CAM_LCLK, + J18_1610_CAM_D7, + J19_1610_CAM_D6, + J14_1610_CAM_D5, + K18_1610_CAM_D4, + K19_1610_CAM_D3, + K15_1610_CAM_D2, + K14_1610_CAM_D1, + L19_1610_CAM_D0, + L18_1610_CAM_VS, + L15_1610_CAM_HS, + M19_1610_CAM_RSTZ, + Y15_1610_CAM_OUTCLK, + + /* serial camera */ + H19_1610_CAM_EXCLK, + Y12_1610_CCP_CLKP, + W13_1610_CCP_CLKM, + W14_1610_CCP_DATAP, + Y14_1610_CCP_DATAM, + }; enum omap24xx_index { diff --git a/include/asm-arm/arch-omap/omap24xx.h b/include/asm-arm/arch-omap/omap24xx.h index 708b2fa..14c0f94 100644 --- a/include/asm-arm/arch-omap/omap24xx.h +++ b/include/asm-arm/arch-omap/omap24xx.h @@ -8,6 +8,7 @@ */ #define L4_24XX_BASE 0x48000000 +#define L4_WK_243X_BASE 0x49000000 #define L3_24XX_BASE 0x68000000 /* interrupt controller */ @@ -16,9 +17,20 @@ #define OMAP24XX_IVA_INTC_BASE 0x40000000 #define IRQ_SIR_IRQ 0x0040 +#ifdef CONFIG_ARCH_OMAP2420 #define OMAP24XX_32KSYNCT_BASE (L4_24XX_BASE + 0x4000) #define OMAP24XX_PRCM_BASE (L4_24XX_BASE + 0x8000) #define OMAP24XX_SDRC_BASE (L3_24XX_BASE + 0x9000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#endif + +#ifdef CONFIG_ARCH_OMAP2430 +#define OMAP24XX_32KSYNCT_BASE (L4_WK_243X_BASE + 0x20000) +#define OMAP24XX_PRCM_BASE (L4_WK_243X_BASE + 0x6000) +#define OMAP24XX_SDRC_BASE (0x6D000000) +#define OMAP242X_CONTROL_STATUS (L4_24XX_BASE + 0x2f8) +#define OMAP243X_GPMC_BASE 0x6E000000 +#endif /* DSP SS */ #define OMAP24XX_DSP_BASE 0x58000000 diff --git a/include/asm-arm/arch-omap/onenand.h b/include/asm-arm/arch-omap/onenand.h new file mode 100644 index 0000000..6c959d0ce --- /dev/null +++ b/include/asm-arm/arch-omap/onenand.h @@ -0,0 +1,21 @@ +/* + * include/asm-arm/arch-omap/onenand.h + * + * Copyright (C) 2006 Nokia Corporation + * Author: Juha Yrjola + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <linux/mtd/partitions.h> + +struct omap_onenand_platform_data { + int cs; + int gpio_irq; + struct mtd_partition *parts; + int nr_parts; + int (*onenand_setup)(void __iomem *); + int dma_channel; +}; diff --git a/include/asm-arm/arch-pxa/cm-x270.h b/include/asm-arm/arch-pxa/cm-x270.h new file mode 100644 index 0000000..f8fac9e --- /dev/null +++ b/include/asm-arm/arch-pxa/cm-x270.h @@ -0,0 +1,50 @@ +/* + * linux/include/asm/arch-pxa/cm-x270.h + * + * Copyright Compulab Ltd., 2003, 2007 + * Mike Rapoport <mike@compulab.co.il> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + + +/* CM-x270 device physical addresses */ +#define CMX270_CS1_PHYS (PXA_CS1_PHYS) +#define MARATHON_PHYS (PXA_CS2_PHYS) +#define CMX270_IDE104_PHYS (PXA_CS3_PHYS) +#define CMX270_IT8152_PHYS (PXA_CS4_PHYS) + +/* Statically mapped regions */ +#define CMX270_VIRT_BASE (0xe8000000) +#define CMX270_IT8152_VIRT (CMX270_VIRT_BASE) +#define CMX270_IDE104_VIRT (CMX270_IT8152_VIRT + SZ_64M) + +/* GPIO related definitions */ +#define GPIO_IT8152_IRQ (22) + +#define IRQ_GPIO_IT8152_IRQ IRQ_GPIO(GPIO_IT8152_IRQ) +#define PME_IRQ IRQ_GPIO(0) +#define CMX270_IDE_IRQ IRQ_GPIO(100) +#define CMX270_GPIRQ1 IRQ_GPIO(101) +#define CMX270_TOUCHIRQ IRQ_GPIO(96) +#define CMX270_ETHIRQ IRQ_GPIO(10) +#define CMX270_GFXIRQ IRQ_GPIO(95) +#define CMX270_NANDIRQ IRQ_GPIO(89) +#define CMX270_MMC_IRQ IRQ_GPIO(83) + +/* PCMCIA related definitions */ +#define PCC_DETECT(x) (GPLR(84 - (x)) & GPIO_bit(84 - (x))) +#define PCC_READY(x) (GPLR(82 - (x)) & GPIO_bit(82 - (x))) + +#define PCMCIA_S0_CD_VALID IRQ_GPIO(84) +#define PCMCIA_S0_CD_VALID_EDGE GPIO_BOTH_EDGES + +#define PCMCIA_S1_CD_VALID IRQ_GPIO(83) +#define PCMCIA_S1_CD_VALID_EDGE GPIO_BOTH_EDGES + +#define PCMCIA_S0_RDYINT IRQ_GPIO(82) +#define PCMCIA_S1_RDYINT IRQ_GPIO(81) + +#define PCMCIA_RESET_GPIO 53 diff --git a/include/asm-arm/arch-pxa/dma.h b/include/asm-arm/arch-pxa/dma.h index 3280ee2..dbe110e 100644 --- a/include/asm-arm/arch-pxa/dma.h +++ b/include/asm-arm/arch-pxa/dma.h @@ -30,6 +30,10 @@ typedef enum { DMA_PRIO_LOW = 2 } pxa_dma_prio; +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define HAVE_ARCH_PCI_SET_DMA_MASK 1 +#endif + /* * DMA registration */ diff --git a/include/asm-arm/arch-pxa/gpio.h b/include/asm-arm/arch-pxa/gpio.h index 9e99241..9dbc2dc 100644 --- a/include/asm-arm/arch-pxa/gpio.h +++ b/include/asm-arm/arch-pxa/gpio.h @@ -38,16 +38,8 @@ static inline void gpio_free(unsigned gpio) return; } -static inline int gpio_direction_input(unsigned gpio) -{ - return pxa_gpio_mode(gpio | GPIO_IN); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return pxa_gpio_mode(gpio | GPIO_OUT | - (value ? GPIO_DFLT_HIGH : GPIO_DFLT_LOW)); -} +extern int gpio_direction_input(unsigned gpio); +extern int gpio_direction_output(unsigned gpio, int value); static inline int __gpio_get_value(unsigned gpio) { diff --git a/include/asm-arm/arch-pxa/hardware.h b/include/asm-arm/arch-pxa/hardware.h index 3861217..ab2d963 100644 --- a/include/asm-arm/arch-pxa/hardware.h +++ b/include/asm-arm/arch-pxa/hardware.h @@ -62,6 +62,7 @@ #ifndef __ASSEMBLY__ +#ifdef CONFIG_PXA25x #define __cpu_is_pxa21x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xf3f; \ @@ -73,12 +74,50 @@ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x2d0 || _id == 0x290; \ }) +#else +#define __cpu_is_pxa21x(id) (0) +#define __cpu_is_pxa25x(id) (0) +#endif +#ifdef CONFIG_PXA27x #define __cpu_is_pxa27x(id) \ ({ \ unsigned int _id = (id) >> 4 & 0xfff; \ _id == 0x411; \ }) +#else +#define __cpu_is_pxa27x(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA300 +#define __cpu_is_pxa300(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x688; \ + }) +#else +#define __cpu_is_pxa300(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA310 +#define __cpu_is_pxa310(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x689; \ + }) +#else +#define __cpu_is_pxa310(id) (0) +#endif + +#ifdef CONFIG_CPU_PXA320 +#define __cpu_is_pxa320(id) \ + ({ \ + unsigned int _id = (id) >> 4 & 0xfff; \ + _id == 0x603 || _id == 0x682; \ + }) +#else +#define __cpu_is_pxa320(id) (0) +#endif #define cpu_is_pxa21x() \ ({ \ @@ -98,6 +137,53 @@ __cpu_is_pxa27x(id); \ }) +#define cpu_is_pxa300() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa300(id); \ + }) + +#define cpu_is_pxa310() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa310(id); \ + }) + +#define cpu_is_pxa320() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa320(id); \ + }) + +/* + * CPUID Core Generation Bit + * <= 0x2 for pxa21x/pxa25x/pxa26x/pxa27x + * == 0x3 for pxa300/pxa310/pxa320 + */ +#define __cpu_is_pxa2xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id <= 0x2; \ + }) + +#define __cpu_is_pxa3xx(id) \ + ({ \ + unsigned int _id = (id) >> 13 & 0x7; \ + _id == 0x3; \ + }) + +#define cpu_is_pxa2xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa2xx(id); \ + }) + +#define cpu_is_pxa3xx() \ + ({ \ + unsigned int id = read_cpuid(CPUID_ID); \ + __cpu_is_pxa3xx(id); \ + }) + /* * Handy routine to set GPIO alternate functions */ @@ -116,14 +202,23 @@ extern void pxa_gpio_set_value(unsigned gpio, int value); /* * Routine to enable or disable CKEN */ -extern void pxa_set_cken(int clock, int enable); +static inline void __deprecated pxa_set_cken(int clock, int enable) +{ + extern void __pxa_set_cken(int clock, int enable); + __pxa_set_cken(clock, enable); +} /* * return current memory and LCD clock frequency in units of 10kHz */ extern unsigned int get_memclk_frequency_10khz(void); -extern unsigned int get_lcdclk_frequency_10khz(void); #endif +#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +#define PCIBIOS_MIN_IO 0 +#define PCIBIOS_MIN_MEM 0 +#define pcibios_assign_all_busses() 1 +#endif + #endif /* _ASM_ARCH_HARDWARE_H */ diff --git a/include/asm-arm/arch-pxa/irqs.h b/include/asm-arm/arch-pxa/irqs.h index a07fe0f..6238dbf 100644 --- a/include/asm-arm/arch-pxa/irqs.h +++ b/include/asm-arm/arch-pxa/irqs.h @@ -66,12 +66,6 @@ #define IRQ_TO_GPIO_2_x(i) ((i) - PXA_GPIO_IRQ_BASE) #define IRQ_TO_GPIO(i) (((i) < IRQ_GPIO(2)) ? ((i) - IRQ_GPIO0) : IRQ_TO_GPIO_2_x(i)) -#if defined(CONFIG_PXA25x) -#define PXA_LAST_GPIO 84 -#elif defined(CONFIG_PXA27x) -#define PXA_LAST_GPIO 127 -#endif - /* * The next 16 interrupts are for board specific purposes. Since * the kernel can only run on one machine at a time, we can re-use @@ -216,3 +210,24 @@ #define IRQ_LOCOMO_GPIO_BASE (IRQ_BOARD_START + 1) #define IRQ_LOCOMO_LT_BASE (IRQ_BOARD_START + 2) #define IRQ_LOCOMO_SPI_BASE (IRQ_BOARD_START + 3) + +/* ITE8152 irqs */ +/* add IT8152 IRQs beyond BOARD_END */ +#ifdef CONFIG_PCI_HOST_ITE8152 +#define IT8152_IRQ(x) (IRQ_GPIO(IRQ_BOARD_END) + 1 + (x)) + +/* IRQ-sources in 3 groups - local devices, LPC (serial), and external PCI */ +#define IT8152_LD_IRQ_COUNT 9 +#define IT8152_LP_IRQ_COUNT 16 +#define IT8152_PD_IRQ_COUNT 15 + +/* Priorities: */ +#define IT8152_PD_IRQ(i) IT8152_IRQ(i) +#define IT8152_LP_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT) +#define IT8152_LD_IRQ(i) (IT8152_IRQ(i) + IT8152_PD_IRQ_COUNT + IT8152_LP_IRQ_COUNT) + +#define IT8152_LAST_IRQ IT8152_LD_IRQ(IT8152_LD_IRQ_COUNT - 1) + +#undef NR_IRQS +#define NR_IRQS (IT8152_LAST_IRQ+1) +#endif diff --git a/include/asm-arm/arch-pxa/memory.h b/include/asm-arm/arch-pxa/memory.h index e17f988..bee81d6 100644 --- a/include/asm-arm/arch-pxa/memory.h +++ b/include/asm-arm/arch-pxa/memory.h @@ -39,4 +39,14 @@ */ #define NODE_MEM_SIZE_BITS 26 +#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI) +void cmx270_pci_adjust_zones(int node, unsigned long *size, + unsigned long *holes); + +#define arch_adjust_zones(node, size, holes) \ + cmx270_pci_adjust_zones(node, size, holes) + +#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1) +#endif + #endif diff --git a/include/asm-arm/arch-pxa/mfp-pxa300.h b/include/asm-arm/arch-pxa/mfp-pxa300.h new file mode 100644 index 0000000..7513c7a --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa300.h @@ -0,0 +1,574 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa300.h + * + * PXA300/PXA310 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA300_H +#define __ASM_ARCH_MFP_PXA300_H + +#include <asm/arch/mfp.h> + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO46, AF1) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF3) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF2) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF3) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF3) +#define GPIO56_GPIO MFP_CFG(GPIO56, AF0) +#define GPIO58_GPIO MFP_CFG(GPIO58, AF0) +#define GPIO59_GPIO MFP_CFG(GPIO59, AF0) +#define GPIO60_GPIO MFP_CFG(GPIO60, AF0) +#define GPIO61_GPIO MFP_CFG(GPIO61, AF0) +#define GPIO62_GPIO MFP_CFG(GPIO62, AF0) + +#ifdef CONFIG_CPU_PXA310 +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#endif + +/* Chip Select */ +#define GPIO2_nCS3 MFP_CFG(GPIO2, AF1) + +/* AC97 */ +#define GPIO23_AC97_nACRESET MFP_CFG(GPIO23, AF1) +#define GPIO24_AC97_SYSCLK MFP_CFG(GPIO24, AF1) +#define GPIO29_AC97_BITCLK MFP_CFG(GPIO29, AF1) +#define GPIO25_AC97_SDATA_IN_0 MFP_CFG(GPIO25, AF1) +#define GPIO26_AC97_SDATA_IN_1 MFP_CFG(GPIO26, AF1) +#define GPIO17_AC97_SDATA_IN_2 MFP_CFG(GPIO17, AF3) +#define GPIO21_AC97_SDATA_IN_2 MFP_CFG(GPIO21, AF2) +#define GPIO18_AC97_SDATA_IN_3 MFP_CFG(GPIO18, AF3) +#define GPIO22_AC97_SDATA_IN_3 MFP_CFG(GPIO22, AF2) +#define GPIO27_AC97_SDATA_OUT MFP_CFG(GPIO27, AF1) +#define GPIO28_AC97_SYNC MFP_CFG(GPIO28, AF1) + +/* I2C */ +#define GPIO21_I2C_SCL MFP_CFG_LPM(GPIO21, AF1, PULL_HIGH) +#define GPIO22_I2C_SDA MFP_CFG_LPM(GPIO22, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO39_CI_DD_0 MFP_CFG_DRV(GPIO39, AF1, DS04X) +#define GPIO40_CI_DD_1 MFP_CFG_DRV(GPIO40, AF1, DS04X) +#define GPIO41_CI_DD_2 MFP_CFG_DRV(GPIO41, AF1, DS04X) +#define GPIO42_CI_DD_3 MFP_CFG_DRV(GPIO42, AF1, DS04X) +#define GPIO43_CI_DD_4 MFP_CFG_DRV(GPIO43, AF1, DS04X) +#define GPIO44_CI_DD_5 MFP_CFG_DRV(GPIO44, AF1, DS04X) +#define GPIO45_CI_DD_6 MFP_CFG_DRV(GPIO45, AF1, DS04X) +#define GPIO46_CI_DD_7 MFP_CFG_DRV(GPIO46, AF0, DS04X) +#define GPIO47_CI_DD_8 MFP_CFG_DRV(GPIO47, AF1, DS04X) +#define GPIO48_CI_DD_9 MFP_CFG_DRV(GPIO48, AF1, DS04X) +#define GPIO52_CI_HSYNC MFP_CFG_DRV(GPIO52, AF0, DS04X) +#define GPIO51_CI_VSYNC MFP_CFG_DRV(GPIO51, AF0, DS04X) +#define GPIO49_CI_MCLK MFP_CFG_DRV(GPIO49, AF0, DS04X) +#define GPIO50_CI_PCLK MFP_CFG_DRV(GPIO50, AF0, DS04X) + +/* KEYPAD */ +#define GPIO3_KP_DKIN_6 MFP_CFG_LPM(GPIO3, AF2, FLOAT) +#define GPIO4_KP_DKIN_7 MFP_CFG_LPM(GPIO4, AF2, FLOAT) +#define GPIO16_KP_DKIN_6 MFP_CFG_LPM(GPIO16, AF6, FLOAT) +#define GPIO83_KP_DKIN_2 MFP_CFG_LPM(GPIO83, AF5, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF5, FLOAT) +#define GPIO85_KP_DKIN_0 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_1 MFP_CFG_LPM(GPIO86, AF3, FLOAT) +#define GPIO87_KP_DKIN_2 MFP_CFG_LPM(GPIO87, AF3, FLOAT) +#define GPIO88_KP_DKIN_3 MFP_CFG_LPM(GPIO88, AF3, FLOAT) +#define GPIO89_KP_DKIN_3 MFP_CFG_LPM(GPIO89, AF3, FLOAT) +#define GPIO107_KP_DKIN_0 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_1 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_2 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_3 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_4 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_5 MFP_CFG_LPM(GPIO112, AF2, FLOAT) +#define GPIO113_KP_DKIN_6 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_7 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_0 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_1 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_2 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_3 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_4 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_5 MFP_CFG_LPM(GPIO120, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF5, FLOAT) +#define GPIO0_2_KP_DKIN_0 MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) +#define GPIO1_2_KP_DKIN_1 MFP_CFG_LPM(GPIO1_2, AF2, FLOAT) +#define GPIO2_2_KP_DKIN_6 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_7 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_1 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) +#define GPIO5_2_KP_DKIN_0 MFP_CFG_LPM(GPIO5_2, AF2, FLOAT) + +#define GPIO5_KP_MKIN_0 MFP_CFG_LPM(GPIO5, AF2, FLOAT) +#define GPIO6_KP_MKIN_1 MFP_CFG_LPM(GPIO6, AF2, FLOAT) +#define GPIO9_KP_MKIN_6 MFP_CFG_LPM(GPIO9, AF3, FLOAT) +#define GPIO10_KP_MKIN_7 MFP_CFG_LPM(GPIO10, AF3, FLOAT) +#define GPIO70_KP_MKIN_6 MFP_CFG_LPM(GPIO70, AF3, FLOAT) +#define GPIO71_KP_MKIN_7 MFP_CFG_LPM(GPIO71, AF3, FLOAT) +#define GPIO100_KP_MKIN_6 MFP_CFG_LPM(GPIO100, AF7, FLOAT) +#define GPIO101_KP_MKIN_7 MFP_CFG_LPM(GPIO101, AF7, FLOAT) +#define GPIO112_KP_MKIN_6 MFP_CFG_LPM(GPIO112, AF4, FLOAT) +#define GPIO113_KP_MKIN_7 MFP_CFG_LPM(GPIO113, AF4, FLOAT) +#define GPIO115_KP_MKIN_0 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_1 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_2 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_3 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_4 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_5 MFP_CFG_LPM(GPIO120, AF1, FLOAT) +#define GPIO125_KP_MKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO2_2_KP_MKIN_6 MFP_CFG_LPM(GPIO2_2, AF1, FLOAT) +#define GPIO3_2_KP_MKIN_7 MFP_CFG_LPM(GPIO3_2, AF1, FLOAT) + +#define GPIO7_KP_MKOUT_5 MFP_CFG_LPM(GPIO7, AF1, DRIVE_HIGH) +#define GPIO11_KP_MKOUT_5 MFP_CFG_LPM(GPIO11, AF3, DRIVE_HIGH) +#define GPIO12_KP_MKOUT_6 MFP_CFG_LPM(GPIO12, AF3, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_7 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO19_KP_MKOUT_4 MFP_CFG_LPM(GPIO19, AF3, DRIVE_HIGH) +#define GPIO20_KP_MKOUT_5 MFP_CFG_LPM(GPIO20, AF3, DRIVE_HIGH) +#define GPIO38_KP_MKOUT_5 MFP_CFG_LPM(GPIO38, AF5, DRIVE_HIGH) +#define GPIO53_KP_MKOUT_6 MFP_CFG_LPM(GPIO53, AF5, DRIVE_HIGH) +#define GPIO78_KP_MKOUT_7 MFP_CFG_LPM(GPIO78, AF5, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_0 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_1 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO87_KP_MKOUT_2 MFP_CFG_LPM(GPIO87, AF2, DRIVE_HIGH) +#define GPIO88_KP_MKOUT_3 MFP_CFG_LPM(GPIO88, AF2, DRIVE_HIGH) +#define GPIO104_KP_MKOUT_6 MFP_CFG_LPM(GPIO104, AF5, DRIVE_HIGH) +#define GPIO105_KP_MKOUT_7 MFP_CFG_LPM(GPIO105, AF5, DRIVE_HIGH) +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_7 MFP_CFG_LPM(GPIO126, AF4, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_6 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) +#define GPIO4_2_KP_MKOUT_5 MFP_CFG_LPM(GPIO4_2, AF1, DRIVE_HIGH) +#define GPIO6_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO6_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO54_LCD_LDD_0 MFP_CFG_DRV(GPIO54, AF1, DS01X) +#define GPIO55_LCD_LDD_1 MFP_CFG_DRV(GPIO55, AF1, DS01X) +#define GPIO56_LCD_LDD_2 MFP_CFG_DRV(GPIO56, AF1, DS01X) +#define GPIO57_LCD_LDD_3 MFP_CFG_DRV(GPIO57, AF1, DS01X) +#define GPIO58_LCD_LDD_4 MFP_CFG_DRV(GPIO58, AF1, DS01X) +#define GPIO59_LCD_LDD_5 MFP_CFG_DRV(GPIO59, AF1, DS01X) +#define GPIO60_LCD_LDD_6 MFP_CFG_DRV(GPIO60, AF1, DS01X) +#define GPIO61_LCD_LDD_7 MFP_CFG_DRV(GPIO61, AF1, DS01X) +#define GPIO62_LCD_LDD_8 MFP_CFG_DRV(GPIO62, AF1, DS01X) +#define GPIO63_LCD_LDD_9 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_10 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_11 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_12 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_13 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_14 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_15 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_16 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_17 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO62_LCD_CS_N MFP_CFG_DRV(GPIO62, AF2, DS01X) +#define GPIO72_LCD_FCLK MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_LCLK MFP_CFG_DRV(GPIO73, AF1, DS01X) +#define GPIO74_LCD_PCLK MFP_CFG_DRV(GPIO74, AF1, DS01X) +#define GPIO75_LCD_BIAS MFP_CFG_DRV(GPIO75, AF1, DS01X) +#define GPIO76_LCD_VSYNC MFP_CFG_DRV(GPIO76, AF2, DS01X) + +#define GPIO15_LCD_CS_N MFP_CFG_DRV(GPIO15, AF2, DS01X) +#define GPIO127_LCD_CS_N MFP_CFG_DRV(GPIO127, AF1, DS01X) +#define GPIO63_LCD_VSYNC MFP_CFG_DRV(GPIO63, AF2, DS01X) + +/* Mini-LCD */ +#define GPIO72_MLCD_FCLK MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_LCLK MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO54_MLCD_LDD_0 MFP_CFG_DRV(GPIO54, AF7, DS08X) +#define GPIO55_MLCD_LDD_1 MFP_CFG_DRV(GPIO55, AF7, DS08X) +#define GPIO56_MLCD_LDD_2 MFP_CFG_DRV(GPIO56, AF7, DS08X) +#define GPIO57_MLCD_LDD_3 MFP_CFG_DRV(GPIO57, AF7, DS08X) +#define GPIO58_MLCD_LDD_4 MFP_CFG_DRV(GPIO58, AF7, DS08X) +#define GPIO59_MLCD_LDD_5 MFP_CFG_DRV(GPIO59, AF7, DS08X) +#define GPIO60_MLCD_LDD_6 MFP_CFG_DRV(GPIO60, AF7, DS08X) +#define GPIO61_MLCD_LDD_7 MFP_CFG_DRV(GPIO61, AF7, DS08X) +#define GPIO62_MLCD_LDD_8 MFP_CFG_DRV(GPIO62, AF7, DS08X) +#define GPIO63_MLCD_LDD_9 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_LDD_10 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_LDD_11 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_LDD_12 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_LDD_13 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_LDD_14 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_LDD_15 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO74_MLCD_PCLK MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO75_MLCD_BIAS MFP_CFG_DRV(GPIO75, AF2, DS08X) + +/* MMC1 */ +#define GPIO7_MMC1_CLK MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_CMD MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO14_MMC1_CMD MFP_CFG_LPM(GPIO14, AF5, DRIVE_HIGH) +#define GPIO15_MMC1_CMD MFP_CFG_LPM(GPIO15, AF5, DRIVE_HIGH) +#define GPIO3_MMC1_DAT0 MFP_CFG_LPM(GPIO3, AF4, DRIVE_HIGH) +#define GPIO4_MMC1_DAT1 MFP_CFG_LPM(GPIO4, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT2 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT3 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) + +/* MMC2 */ +#define GPIO9_MMC2_DAT0 MFP_CFG_LPM(GPIO9, AF4, PULL_HIGH) +#define GPIO10_MMC2_DAT1 MFP_CFG_LPM(GPIO10, AF4, PULL_HIGH) +#define GPIO11_MMC2_DAT2 MFP_CFG_LPM(GPIO11, AF4, PULL_HIGH) +#define GPIO12_MMC2_DAT3 MFP_CFG_LPM(GPIO12, AF4, PULL_HIGH) +#define GPIO13_MMC2_CLK MFP_CFG_LPM(GPIO13, AF4, PULL_HIGH) +#define GPIO14_MMC2_CMD MFP_CFG_LPM(GPIO14, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT0 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT1 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) +#define GPIO79_MMC2_DAT2 MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_DAT3 MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) +#define GPIO81_MMC2_CLK MFP_CFG_LPM(GPIO81, AF4, PULL_HIGH) +#define GPIO82_MMC2_CMD MFP_CFG_LPM(GPIO82, AF4, PULL_HIGH) + +/* SSP1 */ +#define GPIO89_SSP1_EXTCLK MFP_CFG(GPIO89, AF1) +#define GPIO90_SSP1_SYSCLK MFP_CFG(GPIO90, AF1) +#define GPIO15_SSP1_SCLK MFP_CFG(GPIO15, AF6) +#define GPIO16_SSP1_FRM MFP_CFG(GPIO16, AF2) +#define GPIO33_SSP1_SCLK MFP_CFG(GPIO33, AF5) +#define GPIO34_SSP1_FRM MFP_CFG(GPIO34, AF5) +#define GPIO85_SSP1_SCLK MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_FRM MFP_CFG(GPIO86, AF1) +#define GPIO18_SSP1_TXD MFP_CFG(GPIO18, AF7) +#define GPIO18_SSP1_RXD MFP_CFG(GPIO18, AF2) +#define GPIO20_SSP1_TXD MFP_CFG(GPIO20, AF2) +#define GPIO20_SSP1_RXD MFP_CFG(GPIO20, AF7) +#define GPIO35_SSP1_TXD MFP_CFG(GPIO35, AF5) +#define GPIO35_SSP1_RXD MFP_CFG(GPIO35, AF4) +#define GPIO36_SSP1_TXD MFP_CFG(GPIO36, AF5) +#define GPIO36_SSP1_RXD MFP_CFG(GPIO36, AF6) +#define GPIO87_SSP1_TXD MFP_CFG(GPIO87, AF1) +#define GPIO87_SSP1_RXD MFP_CFG(GPIO87, AF6) +#define GPIO88_SSP1_TXD MFP_CFG(GPIO88, AF6) +#define GPIO88_SSP1_RXD MFP_CFG(GPIO88, AF1) + +/* SSP2 */ +#define GPIO29_SSP2_EXTCLK MFP_CFG(GPIO29, AF2) +#define GPIO23_SSP2_SCLK MFP_CFG(GPIO23, AF2) +#define GPIO17_SSP2_FRM MFP_CFG(GPIO17, AF2) +#define GPIO25_SSP2_SCLK MFP_CFG(GPIO25, AF2) +#define GPIO26_SSP2_FRM MFP_CFG(GPIO26, AF2) +#define GPIO33_SSP2_SCLK MFP_CFG(GPIO33, AF6) +#define GPIO34_SSP2_FRM MFP_CFG(GPIO34, AF6) +#define GPIO64_SSP2_SCLK MFP_CFG(GPIO64, AF2) +#define GPIO65_SSP2_FRM MFP_CFG(GPIO65, AF2) +#define GPIO19_SSP2_TXD MFP_CFG(GPIO19, AF2) +#define GPIO19_SSP2_RXD MFP_CFG(GPIO19, AF7) +#define GPIO24_SSP2_TXD MFP_CFG(GPIO24, AF5) +#define GPIO24_SSP2_RXD MFP_CFG(GPIO24, AF4) +#define GPIO27_SSP2_TXD MFP_CFG(GPIO27, AF2) +#define GPIO27_SSP2_RXD MFP_CFG(GPIO27, AF5) +#define GPIO28_SSP2_TXD MFP_CFG(GPIO28, AF5) +#define GPIO28_SSP2_RXD MFP_CFG(GPIO28, AF2) +#define GPIO35_SSP2_TXD MFP_CFG(GPIO35, AF7) +#define GPIO35_SSP2_RXD MFP_CFG(GPIO35, AF6) +#define GPIO66_SSP2_TXD MFP_CFG(GPIO66, AF4) +#define GPIO66_SSP2_RXD MFP_CFG(GPIO66, AF2) +#define GPIO67_SSP2_TXD MFP_CFG(GPIO67, AF2) +#define GPIO67_SSP2_RXD MFP_CFG(GPIO67, AF4) +#define GPIO36_SSP2_TXD MFP_CFG(GPIO36, AF7) + +/* SSP3 */ +#define GPIO69_SSP3_FRM MFP_CFG_X(GPIO69, AF2, DS08X, DRIVE_LOW) +#define GPIO68_SSP3_SCLK MFP_CFG_X(GPIO68, AF2, DS08X, FLOAT) +#define GPIO92_SSP3_FRM MFP_CFG_X(GPIO92, AF1, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_SCLK MFP_CFG_X(GPIO91, AF1, DS08X, FLOAT) +#define GPIO70_SSP3_TXD MFP_CFG_X(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO70_SSP3_RXD MFP_CFG_X(GPIO70, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF5, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF2, DS08X, FLOAT) +#define GPIO93_SSP3_TXD MFP_CFG_X(GPIO93, AF1, DS08X, DRIVE_LOW) +#define GPIO93_SSP3_RXD MFP_CFG_X(GPIO93, AF5, DS08X, FLOAT) +#define GPIO94_SSP3_TXD MFP_CFG_X(GPIO94, AF5, DS08X, DRIVE_LOW) +#define GPIO94_SSP3_RXD MFP_CFG_X(GPIO94, AF1, DS08X, FLOAT) + +/* SSP4 */ +#define GPIO95_SSP4_SCLK MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_FRM MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO97_SSP4_TXD MFP_CFG_LPM(GPIO97, AF1, PULL_HIGH) +#define GPIO97_SSP4_RXD MFP_CFG_LPM(GPIO97, AF5, PULL_HIGH) +#define GPIO98_SSP4_TXD MFP_CFG_LPM(GPIO98, AF5, PULL_HIGH) +#define GPIO98_SSP4_RXD MFP_CFG_LPM(GPIO98, AF1, PULL_HIGH) + +/* UART1 */ +#define GPIO32_UART1_CTS MFP_CFG_LPM(GPIO32, AF2, FLOAT) +#define GPIO37_UART1_CTS MFP_CFG_LPM(GPIO37, AF4, FLOAT) +#define GPIO79_UART1_CTS MFP_CFG_LPM(GPIO79, AF1, FLOAT) +#define GPIO84_UART1_CTS MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO101_UART1_CTS MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO106_UART1_CTS MFP_CFG_LPM(GPIO106, AF6, FLOAT) + +#define GPIO32_UART1_RTS MFP_CFG_LPM(GPIO32, AF4, FLOAT) +#define GPIO37_UART1_RTS MFP_CFG_LPM(GPIO37, AF2, FLOAT) +#define GPIO79_UART1_RTS MFP_CFG_LPM(GPIO79, AF3, FLOAT) +#define GPIO84_UART1_RTS MFP_CFG_LPM(GPIO84, AF1, FLOAT) +#define GPIO101_UART1_RTS MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO106_UART1_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) + +#define GPIO34_UART1_DSR MFP_CFG_LPM(GPIO34, AF2, FLOAT) +#define GPIO36_UART1_DSR MFP_CFG_LPM(GPIO36, AF4, FLOAT) +#define GPIO81_UART1_DSR MFP_CFG_LPM(GPIO81, AF1, FLOAT) +#define GPIO83_UART1_DSR MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO105_UART1_DSR MFP_CFG_LPM(GPIO105, AF6, FLOAT) + +#define GPIO34_UART1_DTR MFP_CFG_LPM(GPIO34, AF4, FLOAT) +#define GPIO36_UART1_DTR MFP_CFG_LPM(GPIO36, AF2, FLOAT) +#define GPIO81_UART1_DTR MFP_CFG_LPM(GPIO81, AF3, FLOAT) +#define GPIO83_UART1_DTR MFP_CFG_LPM(GPIO83, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO105_UART1_DTR MFP_CFG_LPM(GPIO105, AF1, FLOAT) + +#define GPIO35_UART1_RI MFP_CFG_LPM(GPIO35, AF2, FLOAT) +#define GPIO82_UART1_RI MFP_CFG_LPM(GPIO82, AF1, FLOAT) +#define GPIO104_UART1_RI MFP_CFG_LPM(GPIO104, AF1, FLOAT) + +#define GPIO33_UART1_DCD MFP_CFG_LPM(GPIO33, AF2, FLOAT) +#define GPIO80_UART1_DCD MFP_CFG_LPM(GPIO80, AF1, FLOAT) +#define GPIO102_UART1_DCD MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +#define GPIO30_UART1_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO31_UART1_RXD MFP_CFG_LPM(GPIO31, AF4, FLOAT) +#define GPIO77_UART1_RXD MFP_CFG_LPM(GPIO77, AF1, FLOAT) +#define GPIO78_UART1_RXD MFP_CFG_LPM(GPIO78, AF3, FLOAT) +#define GPIO99_UART1_RXD MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO100_UART1_RXD MFP_CFG_LPM(GPIO100, AF6, FLOAT) +#define GPIO102_UART1_RXD MFP_CFG_LPM(GPIO102, AF6, FLOAT) +#define GPIO104_UART1_RXD MFP_CFG_LPM(GPIO104, AF4, FLOAT) + +#define GPIO30_UART1_TXD MFP_CFG_LPM(GPIO30, AF4, FLOAT) +#define GPIO31_UART1_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO77_UART1_TXD MFP_CFG_LPM(GPIO77, AF3, FLOAT) +#define GPIO78_UART1_TXD MFP_CFG_LPM(GPIO78, AF1, FLOAT) +#define GPIO99_UART1_TXD MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO100_UART1_TXD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO102_UART1_TXD MFP_CFG_LPM(GPIO102, AF4, FLOAT) + +/* UART2 */ +#define GPIO15_UART2_CTS MFP_CFG_LPM(GPIO15, AF3, FLOAT) +#define GPIO16_UART2_CTS MFP_CFG_LPM(GPIO16, AF5, FLOAT) +#define GPIO111_UART2_CTS MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO114_UART2_CTS MFP_CFG_LPM(GPIO114, AF1, FLOAT) + +#define GPIO15_UART2_RTS MFP_CFG_LPM(GPIO15, AF4, FLOAT) +#define GPIO16_UART2_RTS MFP_CFG_LPM(GPIO16, AF4, FLOAT) +#define GPIO114_UART2_RTS MFP_CFG_LPM(GPIO114, AF3, FLOAT) +#define GPIO111_UART2_RTS MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +#define GPIO18_UART2_RXD MFP_CFG_LPM(GPIO18, AF5, FLOAT) +#define GPIO19_UART2_RXD MFP_CFG_LPM(GPIO19, AF4, FLOAT) +#define GPIO112_UART2_RXD MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO113_UART2_RXD MFP_CFG_LPM(GPIO113, AF3, FLOAT) + +#define GPIO18_UART2_TXD MFP_CFG_LPM(GPIO18, AF4, FLOAT) +#define GPIO19_UART2_TXD MFP_CFG_LPM(GPIO19, AF5, FLOAT) +#define GPIO112_UART2_TXD MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO113_UART2_TXD MFP_CFG_LPM(GPIO113, AF1, FLOAT) + +/* UART3 */ +#define GPIO91_UART3_CTS MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_CTS MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_CTS MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_CTS MFP_CFG_LPM(GPIO108, AF3, FLOAT) + +#define GPIO91_UART3_RTS MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO92_UART3_RTS MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO107_UART3_RTS MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO108_UART3_RTS MFP_CFG_LPM(GPIO108, AF1, FLOAT) + +#define GPIO7_UART3_RXD MFP_CFG_LPM(GPIO7, AF2, FLOAT) +#define GPIO8_UART3_RXD MFP_CFG_LPM(GPIO8, AF6, FLOAT) +#define GPIO93_UART3_RXD MFP_CFG_LPM(GPIO93, AF4, FLOAT) +#define GPIO94_UART3_RXD MFP_CFG_LPM(GPIO94, AF2, FLOAT) +#define GPIO109_UART3_RXD MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO110_UART3_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) + +#define GPIO7_UART3_TXD MFP_CFG_LPM(GPIO7, AF6, FLOAT) +#define GPIO8_UART3_TXD MFP_CFG_LPM(GPIO8, AF2, FLOAT) +#define GPIO93_UART3_TXD MFP_CFG_LPM(GPIO93, AF2, FLOAT) +#define GPIO94_UART3_TXD MFP_CFG_LPM(GPIO94, AF4, FLOAT) +#define GPIO109_UART3_TXD MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO110_UART3_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) + +/* USB Host */ +#define GPIO0_2_USBH_PEN MFP_CFG(GPIO0_2, AF1) +#define GPIO1_2_USBH_PWR MFP_CFG(GPIO1_2, AF1) + +/* USB P3 */ +#define GPIO77_USB_P3_1 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_2 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_3 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_4 MFP_CFG(GPIO80, AF2) +#define GPIO81_USB_P3_5 MFP_CFG(GPIO81, AF2) +#define GPIO82_USB_P3_6 MFP_CFG(GPIO82, AF2) + +/* PWM */ +#define GPIO17_PWM0_OUT MFP_CFG(GPIO17, AF1) +#define GPIO18_PWM1_OUT MFP_CFG(GPIO18, AF1) +#define GPIO19_PWM2_OUT MFP_CFG(GPIO19, AF1) +#define GPIO20_PWM3_OUT MFP_CFG(GPIO20, AF1) + +/* CIR */ +#define GPIO8_CIR_OUT MFP_CFG(GPIO8, AF5) +#define GPIO16_CIR_OUT MFP_CFG(GPIO16, AF3) + +#define GPIO20_OW_DQ_IN MFP_CFG(GPIO20, AF5) +#define GPIO126_OW_DQ MFP_CFG(GPIO126, AF2) + +#define GPIO0_DF_RDY MFP_CFG(GPIO0, AF1) +#define GPIO7_CLK_BYPASS_XSC MFP_CFG(GPIO7, AF7) +#define GPIO17_EXT_SYNC_MVT_0 MFP_CFG(GPIO17, AF6) +#define GPIO18_EXT_SYNC_MVT_1 MFP_CFG(GPIO18, AF6) +#define GPIO19_OST_CHOUT_MVT_0 MFP_CFG(GPIO19, AF6) +#define GPIO20_OST_CHOUT_MVT_1 MFP_CFG(GPIO20, AF6) +#define GPIO49_48M_CLK MFP_CFG(GPIO49, AF2) +#define GPIO126_EXT_CLK MFP_CFG(GPIO126, AF3) +#define GPIO127_CLK_BYPASS_GB MFP_CFG(GPIO127, AF7) +#define GPIO71_EXT_MATCH_MVT MFP_CFG(GPIO71, AF6) + +#define GPIO3_uIO_IN MFP_CFG(GPIO3, AF1) + +#define GPIO4_uSIM_CARD_STATE MFP_CFG(GPIO4, AF1) +#define GPIO5_uSIM_uCLK MFP_CFG(GPIO5, AF1) +#define GPIO6_uSIM_uRST MFP_CFG(GPIO6, AF1) +#define GPIO16_uSIM_UVS_0 MFP_CFG(GPIO16, AF1) + +#define GPIO9_SCIO MFP_CFG(GPIO9, AF1) +#define GPIO20_RTC_MVT MFP_CFG(GPIO20, AF4) +#define GPIO126_RTC_MVT MFP_CFG(GPIO126, AF1) + +/* + * PXA300 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA300 +#define GPIO99_USB_P2_2 MFP_CFG(GPIO99, AF2) +#define GPIO99_USB_P2_5 MFP_CFG(GPIO99, AF3) +#define GPIO99_USB_P2_6 MFP_CFG(GPIO99, AF4) +#define GPIO100_USB_P2_2 MFP_CFG(GPIO100, AF4) +#define GPIO100_USB_P2_5 MFP_CFG(GPIO100, AF5) +#define GPIO101_USB_P2_1 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_4 MFP_CFG(GPIO102, AF2) +#define GPIO104_USB_P2_3 MFP_CFG(GPIO104, AF2) +#define GPIO105_USB_P2_5 MFP_CFG(GPIO105, AF2) +#define GPIO100_USB_P2_6 MFP_CFG(GPIO100, AF2) +#define GPIO106_USB_P2_7 MFP_CFG(GPIO106, AF2) +#define GPIO103_USB_P2_8 MFP_CFG(GPIO103, AF2) + +/* U2D UTMI */ +#define GPIO38_UTM_CLK MFP_CFG(GPIO38, AF1) +#define GPIO26_U2D_RXERROR MFP_CFG(GPIO26, AF3) +#define GPIO50_U2D_RXERROR MFP_CFG(GPIO50, AF1) +#define GPIO89_U2D_RXERROR MFP_CFG(GPIO89, AF5) +#define GPIO24_UTM_RXVALID MFP_CFG(GPIO24, AF3) +#define GPIO48_UTM_RXVALID MFP_CFG(GPIO48, AF2) +#define GPIO87_UTM_RXVALID MFP_CFG(GPIO87, AF5) +#define GPIO25_UTM_RXACTIVE MFP_CFG(GPIO25, AF3) +#define GPIO47_UTM_RXACTIVE MFP_CFG(GPIO47, AF2) +#define GPIO49_UTM_RXACTIVE MFP_CFG(GPIO49, AF1) +#define GPIO88_UTM_RXACTIVE MFP_CFG(GPIO88, AF5) +#define GPIO53_UTM_TXREADY MFP_CFG(GPIO53, AF1) +#define GPIO67_UTM_LINESTATE_0 MFP_CFG(GPIO67, AF3) +#define GPIO92_UTM_LINESTATE_0 MFP_CFG(GPIO92, AF3) +#define GPIO104_UTM_LINESTATE_0 MFP_CFG(GPIO104, AF3) +#define GPIO109_UTM_LINESTATE_0 MFP_CFG(GPIO109, AF4) +#define GPIO68_UTM_LINESTATE_1 MFP_CFG(GPIO68, AF3) +#define GPIO93_UTM_LINESTATE_1 MFP_CFG(GPIO93, AF3) +#define GPIO105_UTM_LINESTATE_1 MFP_CFG(GPIO105, AF3) +#define GPIO27_U2D_OPMODE_0 MFP_CFG(GPIO27, AF4) +#define GPIO51_U2D_OPMODE_0 MFP_CFG(GPIO51, AF2) +#define GPIO90_U2D_OPMODE_0 MFP_CFG(GPIO90, AF7) +#define GPIO28_U2D_OPMODE_1 MFP_CFG(GPIO28, AF4) +#define GPIO52_U2D_OPMODE_1 MFP_CFG(GPIO52, AF2) +#define GPIO106_U2D_OPMODE_1 MFP_CFG(GPIO106, AF3) +#define GPIO110_U2D_OPMODE_1 MFP_CFG(GPIO110, AF5) +#define GPIO76_U2D_RESET MFP_CFG(GPIO76, AF1) +#define GPIO95_U2D_RESET MFP_CFG(GPIO95, AF2) +#define GPIO100_U2D_RESET MFP_CFG(GPIO100, AF3) +#define GPIO66_U2D_SUSPEND MFP_CFG(GPIO66, AF3) +#define GPIO98_U2D_SUSPEND MFP_CFG(GPIO98, AF2) +#define GPIO103_U2D_SUSPEND MFP_CFG(GPIO103, AF3) +#define GPIO65_U2D_TERM_SEL MFP_CFG(GPIO65, AF5) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF3) +#define GPIO102_U2D_TERM_SEL MFP_CFG(GPIO102, AF5) +#define GPIO29_U2D_TXVALID MFP_CFG(GPIO29, AF3) +#define GPIO52_U2D_TXVALID MFP_CFG(GPIO52, AF4) +#define GPIO69_U2D_TXVALID MFP_CFG(GPIO69, AF3) +#define GPIO85_U2D_TXVALID MFP_CFG(GPIO85, AF7) +#define GPIO64_U2D_XCVR_SEL MFP_CFG(GPIO64, AF5) +#define GPIO96_U2D_XCVR_SEL MFP_CFG(GPIO96, AF3) +#define GPIO101_U2D_XCVR_SEL MFP_CFG(GPIO101, AF5) +#define GPIO30_UTM_PHYDATA_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_UTM_PHYDATA_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_UTM_PHYDATA_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_UTM_PHYDATA_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_UTM_PHYDATA_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_UTM_PHYDATA_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_UTM_PHYDATA_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_UTM_PHYDATA_7 MFP_CFG(GPIO37, AF3) +#define GPIO39_UTM_PHYDATA_0 MFP_CFG(GPIO39, AF3) +#define GPIO40_UTM_PHYDATA_1 MFP_CFG(GPIO40, AF3) +#define GPIO41_UTM_PHYDATA_2 MFP_CFG(GPIO41, AF3) +#define GPIO42_UTM_PHYDATA_3 MFP_CFG(GPIO42, AF3) +#define GPIO43_UTM_PHYDATA_4 MFP_CFG(GPIO43, AF3) +#define GPIO44_UTM_PHYDATA_5 MFP_CFG(GPIO44, AF3) +#define GPIO45_UTM_PHYDATA_6 MFP_CFG(GPIO45, AF3) +#define GPIO46_UTM_PHYDATA_7 MFP_CFG(GPIO46, AF3) +#endif /* CONFIG_CPU_PXA300 */ + +/* + * PXA310 specific MFP configurations + */ +#ifdef CONFIG_CPU_PXA310 +/* USB P2 */ +#define GPIO36_USB_P2_1 MFP_CFG(GPIO36, AF1) +#define GPIO30_USB_P2_2 MFP_CFG(GPIO30, AF1) +#define GPIO35_USB_P2_3 MFP_CFG(GPIO35, AF1) +#define GPIO32_USB_P2_4 MFP_CFG(GPIO32, AF1) +#define GPIO34_USB_P2_5 MFP_CFG(GPIO34, AF1) +#define GPIO31_USB_P2_6 MFP_CFG(GPIO31, AF1) + +/* MMC1 */ +#define GPIO24_MMC1_CMD MFP_CFG(GPIO24, AF3) +#define GPIO29_MMC1_DAT0 MFP_CFG(GPIO29, AF3) + +/* MMC3 */ +#define GPIO103_MMC3_CLK MFP_CFG(GPIO103, AF2) +#define GPIO105_MMC3_CMD MFP_CFG(GPIO105, AF2) +#define GPIO11_2_MMC3_CLK MFP_CFG(GPIO11_2, AF1) +#define GPIO12_2_MMC3_CMD MFP_CFG(GPIO12_2, AF1) +#define GPIO7_2_MMC3_DAT0 MFP_CFG(GPIO7_2, AF1) +#define GPIO8_2_MMC3_DAT1 MFP_CFG(GPIO8_2, AF1) +#define GPIO9_2_MMC3_DAT2 MFP_CFG(GPIO9_2, AF1) +#define GPIO10_2_MMC3_DAT3 MFP_CFG(GPIO10_2, AF1) + +/* ULPI */ +#define GPIO38_ULPI_CLK MFP_CFG(GPIO38, AF1) +#define GPIO30_ULPI_DATA_OUT_0 MFP_CFG(GPIO30, AF3) +#define GPIO31_ULPI_DATA_OUT_1 MFP_CFG(GPIO31, AF3) +#define GPIO32_ULPI_DATA_OUT_2 MFP_CFG(GPIO32, AF3) +#define GPIO33_ULPI_DATA_OUT_3 MFP_CFG(GPIO33, AF3) +#define GPIO34_ULPI_DATA_OUT_4 MFP_CFG(GPIO34, AF3) +#define GPIO35_ULPI_DATA_OUT_5 MFP_CFG(GPIO35, AF3) +#define GPIO36_ULPI_DATA_OUT_6 MFP_CFG(GPIO36, AF3) +#define GPIO37_ULPI_DATA_OUT_7 MFP_CFG(GPIO37, AF3) +#define GPIO33_ULPI_OTG_INTR MFP_CFG(GPIO33, AF1) + +#define ULPI_DIR MFP_CFG_DRV(ULPI_DIR, MFP_AF0, MFP_DS01X) +#define ULPI_NXT MFP_CFG_DRV(ULPI_NXT, MFP_AF0, MFP_DS01X) +#define ULPI_STP MFP_CFG_DRV(ULPI_STP, MFP_AF0, MFP_DS01X) +#endif /* CONFIG_CPU_PXA310 */ + +#endif /* __ASM_ARCH_MFP_PXA300_H */ diff --git a/include/asm-arm/arch-pxa/mfp-pxa320.h b/include/asm-arm/arch-pxa/mfp-pxa320.h new file mode 100644 index 0000000..ae8ba34 --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp-pxa320.h @@ -0,0 +1,446 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp-pxa320.h + * + * PXA320 specific MFP configuration definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * 2007-08-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_PXA320_H +#define __ASM_ARCH_MFP_PXA320_H + +#include <asm/arch/mfp.h> + +/* GPIO */ +#define GPIO46_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO49_GPIO MFP_CFG(GPIO49, AF0) +#define GPIO50_GPIO MFP_CFG(GPIO50, AF0) +#define GPIO51_GPIO MFP_CFG(GPIO51, AF0) +#define GPIO52_GPIO MFP_CFG(GPIO52, AF0) + +#define GPIO7_2_GPIO MFP_CFG(GPIO7_2, AF0) +#define GPIO8_2_GPIO MFP_CFG(GPIO8_2, AF0) +#define GPIO9_2_GPIO MFP_CFG(GPIO9_2, AF0) +#define GPIO10_2_GPIO MFP_CFG(GPIO10_2, AF0) +#define GPIO11_2_GPIO MFP_CFG(GPIO11_2, AF0) +#define GPIO12_2_GPIO MFP_CFG(GPIO12_2, AF0) +#define GPIO13_2_GPIO MFP_CFG(GPIO13_2, AF0) +#define GPIO14_2_GPIO MFP_CFG(GPIO14_2, AF0) +#define GPIO15_2_GPIO MFP_CFG(GPIO15_2, AF0) +#define GPIO16_2_GPIO MFP_CFG(GPIO16_2, AF0) +#define GPIO17_2_GPIO MFP_CFG(GPIO17_2, AF0) + +/* Chip Select */ +#define GPIO4_nCS3 MFP_CFG(GPIO4, AF1) + +/* AC97 */ +#define GPIO34_AC97_SYSCLK MFP_CFG(GPIO34, AF1) +#define GPIO39_AC97_BITCLK MFP_CFG(GPIO39, AF1) +#define GPIO40_AC97_nACRESET MFP_CFG(GPIO40, AF1) +#define GPIO35_AC97_SDATA_IN_0 MFP_CFG(GPIO35, AF1) +#define GPIO36_AC97_SDATA_IN_1 MFP_CFG(GPIO36, AF1) +#define GPIO32_AC97_SDATA_IN_2 MFP_CFG(GPIO32, AF2) +#define GPIO33_AC97_SDATA_IN_3 MFP_CFG(GPIO33, AF2) +#define GPIO11_AC97_SDATA_IN_2 MFP_CFG(GPIO11, AF3) +#define GPIO12_AC97_SDATA_IN_3 MFP_CFG(GPIO12, AF3) +#define GPIO37_AC97_SDATA_OUT MFP_CFG(GPIO37, AF1) +#define GPIO38_AC97_SYNC MFP_CFG(GPIO38, AF1) + +/* I2C */ +#define GPIO32_I2C_SCL MFP_CFG_LPM(GPIO32, AF1, PULL_HIGH) +#define GPIO33_I2C_SDA MFP_CFG_LPM(GPIO33, AF1, PULL_HIGH) + +/* QCI */ +#define GPIO49_CI_DD_0 MFP_CFG_DRV(GPIO49, AF1, DS04X) +#define GPIO50_CI_DD_1 MFP_CFG_DRV(GPIO50, AF1, DS04X) +#define GPIO51_CI_DD_2 MFP_CFG_DRV(GPIO51, AF1, DS04X) +#define GPIO52_CI_DD_3 MFP_CFG_DRV(GPIO52, AF1, DS04X) +#define GPIO53_CI_DD_4 MFP_CFG_DRV(GPIO53, AF1, DS04X) +#define GPIO54_CI_DD_5 MFP_CFG_DRV(GPIO54, AF1, DS04X) +#define GPIO55_CI_DD_6 MFP_CFG_DRV(GPIO55, AF1, DS04X) +#define GPIO56_CI_DD_7 MFP_CFG_DRV(GPIO56, AF0, DS04X) +#define GPIO57_CI_DD_8 MFP_CFG_DRV(GPIO57, AF1, DS04X) +#define GPIO58_CI_DD_9 MFP_CFG_DRV(GPIO58, AF1, DS04X) +#define GPIO59_CI_MCLK MFP_CFG_DRV(GPIO59, AF0, DS04X) +#define GPIO60_CI_PCLK MFP_CFG_DRV(GPIO60, AF0, DS04X) +#define GPIO61_CI_HSYNC MFP_CFG_DRV(GPIO61, AF0, DS04X) +#define GPIO62_CI_VSYNC MFP_CFG_DRV(GPIO62, AF0, DS04X) + +#define GPIO31_CIR_OUT MFP_CFG(GPIO31, AF5) + +#define GPIO0_2_CLK_EXT MFP_CFG(GPIO0_2, AF3) +#define GPIO0_DRQ MFP_CFG(GPIO0, AF2) +#define GPIO11_EXT_SYNC0 MFP_CFG(GPIO11, AF5) +#define GPIO12_EXT_SYNC1 MFP_CFG(GPIO12, AF6) +#define GPIO0_2_HZ_CLK MFP_CFG(GPIO0_2, AF1) +#define GPIO14_HZ_CLK MFP_CFG(GPIO14, AF4) +#define GPIO30_ICP_RXD MFP_CFG(GPIO30, AF1) +#define GPIO31_ICP_TXD MFP_CFG(GPIO31, AF1) + +#define GPIO83_KP_DKIN_0 MFP_CFG_LPM(GPIO83, AF3, FLOAT) +#define GPIO84_KP_DKIN_1 MFP_CFG_LPM(GPIO84, AF3, FLOAT) +#define GPIO85_KP_DKIN_2 MFP_CFG_LPM(GPIO85, AF3, FLOAT) +#define GPIO86_KP_DKIN_3 MFP_CFG_LPM(GPIO86, AF3, FLOAT) + +#define GPIO105_KP_DKIN_0 MFP_CFG_LPM(GPIO105, AF2, FLOAT) +#define GPIO106_KP_DKIN_1 MFP_CFG_LPM(GPIO106, AF2, FLOAT) +#define GPIO107_KP_DKIN_2 MFP_CFG_LPM(GPIO107, AF2, FLOAT) +#define GPIO108_KP_DKIN_3 MFP_CFG_LPM(GPIO108, AF2, FLOAT) +#define GPIO109_KP_DKIN_4 MFP_CFG_LPM(GPIO109, AF2, FLOAT) +#define GPIO110_KP_DKIN_5 MFP_CFG_LPM(GPIO110, AF2, FLOAT) +#define GPIO111_KP_DKIN_6 MFP_CFG_LPM(GPIO111, AF2, FLOAT) +#define GPIO112_KP_DKIN_7 MFP_CFG_LPM(GPIO112, AF2, FLOAT) + +#define GPIO113_KP_DKIN_0 MFP_CFG_LPM(GPIO113, AF2, FLOAT) +#define GPIO114_KP_DKIN_1 MFP_CFG_LPM(GPIO114, AF2, FLOAT) +#define GPIO115_KP_DKIN_2 MFP_CFG_LPM(GPIO115, AF2, FLOAT) +#define GPIO116_KP_DKIN_3 MFP_CFG_LPM(GPIO116, AF2, FLOAT) +#define GPIO117_KP_DKIN_4 MFP_CFG_LPM(GPIO117, AF2, FLOAT) +#define GPIO118_KP_DKIN_5 MFP_CFG_LPM(GPIO118, AF2, FLOAT) +#define GPIO119_KP_DKIN_6 MFP_CFG_LPM(GPIO119, AF2, FLOAT) +#define GPIO120_KP_DKIN_7 MFP_CFG_LPM(GPIO120, AF2, FLOAT) + +#define GPIO127_KP_DKIN_0 MFP_CFG_LPM(GPIO127, AF2, FLOAT) +#define GPIO126_KP_DKIN_1 MFP_CFG_LPM(GPIO126, AF2, FLOAT) + +#define GPIO2_2_KP_DKIN_0 MFP_CFG_LPM(GPIO2_2, AF2, FLOAT) +#define GPIO3_2_KP_DKIN_1 MFP_CFG_LPM(GPIO3_2, AF2, FLOAT) +#define GPIO125_KP_DKIN_2 MFP_CFG_LPM(GPIO125, AF2, FLOAT) +#define GPIO124_KP_DKIN_3 MFP_CFG_LPM(GPIO124, AF2, FLOAT) +#define GPIO123_KP_DKIN_4 MFP_CFG_LPM(GPIO123, AF2, FLOAT) +#define GPIO122_KP_DKIN_5 MFP_CFG_LPM(GPIO122, AF2, FLOAT) +#define GPIO121_KP_DKIN_6 MFP_CFG_LPM(GPIO121, AF2, FLOAT) +#define GPIO4_2_KP_DKIN_7 MFP_CFG_LPM(GPIO4_2, AF2, FLOAT) + +#define GPIO113_KP_MKIN_0 MFP_CFG_LPM(GPIO113, AF1, FLOAT) +#define GPIO114_KP_MKIN_1 MFP_CFG_LPM(GPIO114, AF1, FLOAT) +#define GPIO115_KP_MKIN_2 MFP_CFG_LPM(GPIO115, AF1, FLOAT) +#define GPIO116_KP_MKIN_3 MFP_CFG_LPM(GPIO116, AF1, FLOAT) +#define GPIO117_KP_MKIN_4 MFP_CFG_LPM(GPIO117, AF1, FLOAT) +#define GPIO118_KP_MKIN_5 MFP_CFG_LPM(GPIO118, AF1, FLOAT) +#define GPIO119_KP_MKIN_6 MFP_CFG_LPM(GPIO119, AF1, FLOAT) +#define GPIO120_KP_MKIN_7 MFP_CFG_LPM(GPIO120, AF1, FLOAT) + +#define GPIO83_KP_MKOUT_0 MFP_CFG_LPM(GPIO83, AF2, DRIVE_HIGH) +#define GPIO84_KP_MKOUT_1 MFP_CFG_LPM(GPIO84, AF2, DRIVE_HIGH) +#define GPIO85_KP_MKOUT_2 MFP_CFG_LPM(GPIO85, AF2, DRIVE_HIGH) +#define GPIO86_KP_MKOUT_3 MFP_CFG_LPM(GPIO86, AF2, DRIVE_HIGH) +#define GPIO13_KP_MKOUT_4 MFP_CFG_LPM(GPIO13, AF3, DRIVE_HIGH) +#define GPIO14_KP_MKOUT_5 MFP_CFG_LPM(GPIO14, AF3, DRIVE_HIGH) + +#define GPIO121_KP_MKOUT_0 MFP_CFG_LPM(GPIO121, AF1, DRIVE_HIGH) +#define GPIO122_KP_MKOUT_1 MFP_CFG_LPM(GPIO122, AF1, DRIVE_HIGH) +#define GPIO123_KP_MKOUT_2 MFP_CFG_LPM(GPIO123, AF1, DRIVE_HIGH) +#define GPIO124_KP_MKOUT_3 MFP_CFG_LPM(GPIO124, AF1, DRIVE_HIGH) +#define GPIO125_KP_MKOUT_4 MFP_CFG_LPM(GPIO125, AF1, DRIVE_HIGH) +#define GPIO126_KP_MKOUT_5 MFP_CFG_LPM(GPIO126, AF1, DRIVE_HIGH) +#define GPIO127_KP_MKOUT_6 MFP_CFG_LPM(GPIO127, AF1, DRIVE_HIGH) +#define GPIO5_2_KP_MKOUT_7 MFP_CFG_LPM(GPIO5_2, AF1, DRIVE_HIGH) + +/* LCD */ +#define GPIO6_2_LCD_LDD_0 MFP_CFG_DRV(GPIO6_2, AF1, DS01X) +#define GPIO7_2_LCD_LDD_1 MFP_CFG_DRV(GPIO7_2, AF1, DS01X) +#define GPIO8_2_LCD_LDD_2 MFP_CFG_DRV(GPIO8_2, AF1, DS01X) +#define GPIO9_2_LCD_LDD_3 MFP_CFG_DRV(GPIO9_2, AF1, DS01X) +#define GPIO10_2_LCD_LDD_4 MFP_CFG_DRV(GPIO10_2, AF1, DS01X) +#define GPIO11_2_LCD_LDD_5 MFP_CFG_DRV(GPIO11_2, AF1, DS01X) +#define GPIO12_2_LCD_LDD_6 MFP_CFG_DRV(GPIO12_2, AF1, DS01X) +#define GPIO13_2_LCD_LDD_7 MFP_CFG_DRV(GPIO13_2, AF1, DS01X) +#define GPIO63_LCD_LDD_8 MFP_CFG_DRV(GPIO63, AF1, DS01X) +#define GPIO64_LCD_LDD_9 MFP_CFG_DRV(GPIO64, AF1, DS01X) +#define GPIO65_LCD_LDD_10 MFP_CFG_DRV(GPIO65, AF1, DS01X) +#define GPIO66_LCD_LDD_11 MFP_CFG_DRV(GPIO66, AF1, DS01X) +#define GPIO67_LCD_LDD_12 MFP_CFG_DRV(GPIO67, AF1, DS01X) +#define GPIO68_LCD_LDD_13 MFP_CFG_DRV(GPIO68, AF1, DS01X) +#define GPIO69_LCD_LDD_14 MFP_CFG_DRV(GPIO69, AF1, DS01X) +#define GPIO70_LCD_LDD_15 MFP_CFG_DRV(GPIO70, AF1, DS01X) +#define GPIO71_LCD_LDD_16 MFP_CFG_DRV(GPIO71, AF1, DS01X) +#define GPIO72_LCD_LDD_17 MFP_CFG_DRV(GPIO72, AF1, DS01X) +#define GPIO73_LCD_CS_N MFP_CFG_DRV(GPIO73, AF2, DS01X) +#define GPIO74_LCD_VSYNC MFP_CFG_DRV(GPIO74, AF2, DS01X) +#define GPIO14_2_LCD_FCLK MFP_CFG_DRV(GPIO14_2, AF1, DS01X) +#define GPIO15_2_LCD_LCLK MFP_CFG_DRV(GPIO15_2, AF1, DS01X) +#define GPIO16_2_LCD_PCLK MFP_CFG_DRV(GPIO16_2, AF1, DS01X) +#define GPIO17_2_LCD_BIAS MFP_CFG_DRV(GPIO17_2, AF1, DS01X) +#define GPIO64_LCD_VSYNC MFP_CFG_DRV(GPIO64, AF2, DS01X) +#define GPIO63_LCD_CS_N MFP_CFG_DRV(GPIO63, AF2, DS01X) + +#define GPIO6_2_MLCD_DD_0 MFP_CFG_DRV(GPIO6_2, AF7, DS08X) +#define GPIO7_2_MLCD_DD_1 MFP_CFG_DRV(GPIO7_2, AF7, DS08X) +#define GPIO8_2_MLCD_DD_2 MFP_CFG_DRV(GPIO8_2, AF7, DS08X) +#define GPIO9_2_MLCD_DD_3 MFP_CFG_DRV(GPIO9_2, AF7, DS08X) +#define GPIO10_2_MLCD_DD_4 MFP_CFG_DRV(GPIO10_2, AF7, DS08X) +#define GPIO11_2_MLCD_DD_5 MFP_CFG_DRV(GPIO11_2, AF7, DS08X) +#define GPIO12_2_MLCD_DD_6 MFP_CFG_DRV(GPIO12_2, AF7, DS08X) +#define GPIO13_2_MLCD_DD_7 MFP_CFG_DRV(GPIO13_2, AF7, DS08X) +#define GPIO63_MLCD_DD_8 MFP_CFG_DRV(GPIO63, AF7, DS08X) +#define GPIO64_MLCD_DD_9 MFP_CFG_DRV(GPIO64, AF7, DS08X) +#define GPIO65_MLCD_DD_10 MFP_CFG_DRV(GPIO65, AF7, DS08X) +#define GPIO66_MLCD_DD_11 MFP_CFG_DRV(GPIO66, AF7, DS08X) +#define GPIO67_MLCD_DD_12 MFP_CFG_DRV(GPIO67, AF7, DS08X) +#define GPIO68_MLCD_DD_13 MFP_CFG_DRV(GPIO68, AF7, DS08X) +#define GPIO69_MLCD_DD_14 MFP_CFG_DRV(GPIO69, AF7, DS08X) +#define GPIO70_MLCD_DD_15 MFP_CFG_DRV(GPIO70, AF7, DS08X) +#define GPIO71_MLCD_DD_16 MFP_CFG_DRV(GPIO71, AF7, DS08X) +#define GPIO72_MLCD_DD_17 MFP_CFG_DRV(GPIO72, AF7, DS08X) +#define GPIO73_MLCD_CS MFP_CFG_DRV(GPIO73, AF7, DS08X) +#define GPIO74_MLCD_VSYNC MFP_CFG_DRV(GPIO74, AF7, DS08X) +#define GPIO14_2_MLCD_FCLK MFP_CFG_DRV(GPIO14_2, AF7, DS08X) +#define GPIO15_2_MLCD_LCLK MFP_CFG_DRV(GPIO15_2, AF7, DS08X) +#define GPIO16_2_MLCD_PCLK MFP_CFG_DRV(GPIO16_2, AF7, DS08X) +#define GPIO17_2_MLCD_BIAS MFP_CFG_DRV(GPIO17_2, AF7, DS08X) + +/* MMC1 */ +#define GPIO9_MMC1_CMD MFP_CFG_LPM(GPIO9, AF4, DRIVE_HIGH) +#define GPIO22_MMC1_CLK MFP_CFG_LPM(GPIO22, AF4, DRIVE_HIGH) +#define GPIO23_MMC1_CMD MFP_CFG_LPM(GPIO23, AF4, DRIVE_HIGH) +#define GPIO30_MMC1_CLK MFP_CFG_LPM(GPIO30, AF4, DRIVE_HIGH) +#define GPIO31_MMC1_CMD MFP_CFG_LPM(GPIO31, AF4, DRIVE_HIGH) +#define GPIO5_MMC1_DAT0 MFP_CFG_LPM(GPIO5, AF4, DRIVE_HIGH) +#define GPIO6_MMC1_DAT1 MFP_CFG_LPM(GPIO6, AF4, DRIVE_HIGH) +#define GPIO7_MMC1_DAT2 MFP_CFG_LPM(GPIO7, AF4, DRIVE_HIGH) +#define GPIO8_MMC1_DAT3 MFP_CFG_LPM(GPIO8, AF4, DRIVE_HIGH) +#define GPIO18_MMC1_DAT0 MFP_CFG_LPM(GPIO18, AF4, DRIVE_HIGH) +#define GPIO19_MMC1_DAT1 MFP_CFG_LPM(GPIO19, AF4, DRIVE_HIGH) +#define GPIO20_MMC1_DAT2 MFP_CFG_LPM(GPIO20, AF4, DRIVE_HIGH) +#define GPIO21_MMC1_DAT3 MFP_CFG_LPM(GPIO21, AF4, DRIVE_HIGH) + +#define GPIO28_MMC2_CLK MFP_CFG_LPM(GPIO28, AF4, PULL_HIGH) +#define GPIO29_MMC2_CMD MFP_CFG_LPM(GPIO29, AF4, PULL_HIGH) +#define GPIO30_MMC2_CLK MFP_CFG_LPM(GPIO30, AF3, PULL_HIGH) +#define GPIO31_MMC2_CMD MFP_CFG_LPM(GPIO31, AF3, PULL_HIGH) +#define GPIO79_MMC2_CLK MFP_CFG_LPM(GPIO79, AF4, PULL_HIGH) +#define GPIO80_MMC2_CMD MFP_CFG_LPM(GPIO80, AF4, PULL_HIGH) + +#define GPIO5_MMC2_DAT0 MFP_CFG_LPM(GPIO5, AF2, PULL_HIGH) +#define GPIO6_MMC2_DAT1 MFP_CFG_LPM(GPIO6, AF2, PULL_HIGH) +#define GPIO7_MMC2_DAT2 MFP_CFG_LPM(GPIO7, AF2, PULL_HIGH) +#define GPIO8_MMC2_DAT3 MFP_CFG_LPM(GPIO8, AF2, PULL_HIGH) +#define GPIO24_MMC2_DAT0 MFP_CFG_LPM(GPIO24, AF4, PULL_HIGH) +#define GPIO75_MMC2_DAT0 MFP_CFG_LPM(GPIO75, AF4, PULL_HIGH) +#define GPIO25_MMC2_DAT1 MFP_CFG_LPM(GPIO25, AF4, PULL_HIGH) +#define GPIO76_MMC2_DAT1 MFP_CFG_LPM(GPIO76, AF4, PULL_HIGH) +#define GPIO26_MMC2_DAT2 MFP_CFG_LPM(GPIO26, AF4, PULL_HIGH) +#define GPIO77_MMC2_DAT2 MFP_CFG_LPM(GPIO77, AF4, PULL_HIGH) +#define GPIO27_MMC2_DAT3 MFP_CFG_LPM(GPIO27, AF4, PULL_HIGH) +#define GPIO78_MMC2_DAT3 MFP_CFG_LPM(GPIO78, AF4, PULL_HIGH) + +/* 1-Wire */ +#define GPIO14_ONE_WIRE MFP_CFG_LPM(GPIO14, AF5, FLOAT) +#define GPIO0_2_ONE_WIRE MFP_CFG_LPM(GPIO0_2, AF2, FLOAT) + +/* SSP1 */ +#define GPIO87_SSP1_EXTCLK MFP_CFG(GPIO87, AF1) +#define GPIO88_SSP1_SYSCLK MFP_CFG(GPIO88, AF1) +#define GPIO83_SSP1_SCLK MFP_CFG(GPIO83, AF1) +#define GPIO84_SSP1_SFRM MFP_CFG(GPIO84, AF1) +#define GPIO85_SSP1_RXD MFP_CFG(GPIO85, AF6) +#define GPIO85_SSP1_TXD MFP_CFG(GPIO85, AF1) +#define GPIO86_SSP1_RXD MFP_CFG(GPIO86, AF1) +#define GPIO86_SSP1_TXD MFP_CFG(GPIO86, AF6) + +/* SSP2 */ +#define GPIO39_SSP2_EXTCLK MFP_CFG(GPIO39, AF2) +#define GPIO40_SSP2_SYSCLK MFP_CFG(GPIO40, AF2) +#define GPIO12_SSP2_SCLK MFP_CFG(GPIO12, AF2) +#define GPIO35_SSP2_SCLK MFP_CFG(GPIO35, AF2) +#define GPIO36_SSP2_SFRM MFP_CFG(GPIO36, AF2) +#define GPIO37_SSP2_RXD MFP_CFG(GPIO37, AF5) +#define GPIO37_SSP2_TXD MFP_CFG(GPIO37, AF2) +#define GPIO38_SSP2_RXD MFP_CFG(GPIO38, AF2) +#define GPIO38_SSP2_TXD MFP_CFG(GPIO38, AF5) + +#define GPIO69_SSP3_SCLK MFP_CFG(GPIO69, AF2, DS08X, FLOAT) +#define GPIO70_SSP3_FRM MFP_CFG(GPIO70, AF2, DS08X, DRIVE_LOW) +#define GPIO89_SSP3_SCLK MFP_CFG(GPIO89, AF1, DS08X, FLOAT) +#define GPIO90_SSP3_FRM MFP_CFG(GPIO90, AF1, DS08X, DRIVE_LOW) +#define GPIO71_SSP3_RXD MFP_CFG_X(GPIO71, AF5, DS08X, FLOAT) +#define GPIO71_SSP3_TXD MFP_CFG_X(GPIO71, AF2, DS08X, DRIVE_LOW) +#define GPIO72_SSP3_RXD MFP_CFG_X(GPIO72, AF2, DS08X, FLOAT) +#define GPIO72_SSP3_TXD MFP_CFG_X(GPIO72, AF5, DS08X, DRIVE_LOW) +#define GPIO91_SSP3_RXD MFP_CFG_X(GPIO91, AF5, DS08X, FLOAT) +#define GPIO91_SSP3_TXD MFP_CFG_X(GPIO91, AF1, DS08X, DRIVE_LOW) +#define GPIO92_SSP3_RXD MFP_CFG_X(GPIO92, AF1, DS08X, FLOAT) +#define GPIO92_SSP3_TXD MFP_CFG_X(GPIO92, AF5, DS08X, DRIVE_LOW) + +#define GPIO93_SSP4_SCLK MFP_CFG_LPM(GPIO93, AF1, PULL_HIGH) +#define GPIO94_SSP4_FRM MFP_CFG_LPM(GPIO94, AF1, PULL_HIGH) +#define GPIO94_SSP4_RXD MFP_CFG_LPM(GPIO94, AF5, PULL_HIGH) +#define GPIO95_SSP4_RXD MFP_CFG_LPM(GPIO95, AF5, PULL_HIGH) +#define GPIO95_SSP4_TXD MFP_CFG_LPM(GPIO95, AF1, PULL_HIGH) +#define GPIO96_SSP4_RXD MFP_CFG_LPM(GPIO96, AF1, PULL_HIGH) +#define GPIO96_SSP4_TXD MFP_CFG_LPM(GPIO96, AF5, PULL_HIGH) + +/* UART1 */ +#define GPIO41_UART1_RXD MFP_CFG_LPM(GPIO41, AF2, FLOAT) +#define GPIO41_UART1_TXD MFP_CFG_LPM(GPIO41, AF4, FLOAT) +#define GPIO42_UART1_RXD MFP_CFG_LPM(GPIO42, AF4, FLOAT) +#define GPIO42_UART1_TXD MFP_CFG_LPM(GPIO42, AF2, FLOAT) +#define GPIO97_UART1_RXD MFP_CFG_LPM(GPIO97, AF1, FLOAT) +#define GPIO97_UART1_TXD MFP_CFG_LPM(GPIO97, AF6, FLOAT) +#define GPIO98_UART1_RXD MFP_CFG_LPM(GPIO98, AF6, FLOAT) +#define GPIO98_UART1_TXD MFP_CFG_LPM(GPIO98, AF1, FLOAT) +#define GPIO43_UART1_CTS MFP_CFG_LPM(GPIO43, AF2, FLOAT) +#define GPIO43_UART1_RTS MFP_CFG_LPM(GPIO43, AF4, FLOAT) +#define GPIO48_UART1_CTS MFP_CFG_LPM(GPIO48, AF4, FLOAT) +#define GPIO48_UART1_RTS MFP_CFG_LPM(GPIO48, AF2, FLOAT) +#define GPIO99_UART1_CTS MFP_CFG_LPM(GPIO99, AF1, FLOAT) +#define GPIO99_UART1_RTS MFP_CFG_LPM(GPIO99, AF6, FLOAT) +#define GPIO104_UART1_CTS MFP_CFG_LPM(GPIO104, AF6, FLOAT) +#define GPIO104_UART1_RTS MFP_CFG_LPM(GPIO104, AF1, FLOAT) +#define GPIO45_UART1_DTR MFP_CFG_LPM(GPIO45, AF4, FLOAT) +#define GPIO45_UART1_DSR MFP_CFG_LPM(GPIO45, AF2, FLOAT) +#define GPIO47_UART1_DTR MFP_CFG_LPM(GPIO47, AF2, FLOAT) +#define GPIO47_UART1_DSR MFP_CFG_LPM(GPIO47, AF4, FLOAT) +#define GPIO101_UART1_DTR MFP_CFG_LPM(GPIO101, AF6, FLOAT) +#define GPIO101_UART1_DSR MFP_CFG_LPM(GPIO101, AF1, FLOAT) +#define GPIO103_UART1_DTR MFP_CFG_LPM(GPIO103, AF1, FLOAT) +#define GPIO103_UART1_DSR MFP_CFG_LPM(GPIO103, AF6, FLOAT) +#define GPIO44_UART1_DCD MFP_CFG_LPM(GPIO44, AF2, FLOAT) +#define GPIO100_UART1_DCD MFP_CFG_LPM(GPIO100, AF1, FLOAT) +#define GPIO46_UART1_RI MFP_CFG_LPM(GPIO46, AF2, FLOAT) +#define GPIO102_UART1_RI MFP_CFG_LPM(GPIO102, AF1, FLOAT) + +/* UART2 */ +#define GPIO109_UART2_CTS MFP_CFG_LPM(GPIO109, AF3, FLOAT) +#define GPIO109_UART2_RTS MFP_CFG_LPM(GPIO109, AF1, FLOAT) +#define GPIO112_UART2_CTS MFP_CFG_LPM(GPIO112, AF1, FLOAT) +#define GPIO112_UART2_RTS MFP_CFG_LPM(GPIO112, AF3, FLOAT) +#define GPIO110_UART2_RXD MFP_CFG_LPM(GPIO110, AF1, FLOAT) +#define GPIO110_UART2_TXD MFP_CFG_LPM(GPIO110, AF3, FLOAT) +#define GPIO111_UART2_RXD MFP_CFG_LPM(GPIO111, AF3, FLOAT) +#define GPIO111_UART2_TXD MFP_CFG_LPM(GPIO111, AF1, FLOAT) + +/* UART3 */ +#define GPIO89_UART3_CTS MFP_CFG_LPM(GPIO89, AF2, FLOAT) +#define GPIO89_UART3_RTS MFP_CFG_LPM(GPIO89, AF4, FLOAT) +#define GPIO90_UART3_CTS MFP_CFG_LPM(GPIO90, AF4, FLOAT) +#define GPIO90_UART3_RTS MFP_CFG_LPM(GPIO90, AF2, FLOAT) +#define GPIO105_UART3_CTS MFP_CFG_LPM(GPIO105, AF1, FLOAT) +#define GPIO105_UART3_RTS MFP_CFG_LPM(GPIO105, AF3, FLOAT) +#define GPIO106_UART3_CTS MFP_CFG_LPM(GPIO106, AF3, FLOAT) +#define GPIO106_UART3_RTS MFP_CFG_LPM(GPIO106, AF1, FLOAT) +#define GPIO30_UART3_RXD MFP_CFG_LPM(GPIO30, AF2, FLOAT) +#define GPIO30_UART3_TXD MFP_CFG_LPM(GPIO30, AF6, FLOAT) +#define GPIO31_UART3_RXD MFP_CFG_LPM(GPIO31, AF6, FLOAT) +#define GPIO31_UART3_TXD MFP_CFG_LPM(GPIO31, AF2, FLOAT) +#define GPIO91_UART3_RXD MFP_CFG_LPM(GPIO91, AF4, FLOAT) +#define GPIO91_UART3_TXD MFP_CFG_LPM(GPIO91, AF2, FLOAT) +#define GPIO92_UART3_RXD MFP_CFG_LPM(GPIO92, AF2, FLOAT) +#define GPIO92_UART3_TXD MFP_CFG_LPM(GPIO92, AF4, FLOAT) +#define GPIO107_UART3_RXD MFP_CFG_LPM(GPIO107, AF3, FLOAT) +#define GPIO107_UART3_TXD MFP_CFG_LPM(GPIO107, AF1, FLOAT) +#define GPIO108_UART3_RXD MFP_CFG_LPM(GPIO108, AF1, FLOAT) +#define GPIO108_UART3_TXD MFP_CFG_LPM(GPIO108, AF3, FLOAT) + + +/* USB 2.0 UTMI */ +#define GPIO10_UTM_CLK MFP_CFG(GPIO10, AF1) +#define GPIO36_U2D_RXERROR MFP_CFG(GPIO36, AF3) +#define GPIO60_U2D_RXERROR MFP_CFG(GPIO60, AF1) +#define GPIO87_U2D_RXERROR MFP_CFG(GPIO87, AF5) +#define GPIO34_UTM_RXVALID MFP_CFG(GPIO34, AF3) +#define GPIO58_UTM_RXVALID MFP_CFG(GPIO58, AF2) +#define GPIO85_UTM_RXVALID MFP_CFG(GPIO85, AF5) +#define GPIO35_UTM_RXACTIVE MFP_CFG(GPIO35, AF3) +#define GPIO59_UTM_RXACTIVE MFP_CFG(GPIO59, AF1) +#define GPIO86_UTM_RXACTIVE MFP_CFG(GPIO86, AF5) +#define GPIO73_UTM_TXREADY MFP_CFG(GPIO73, AF1) +#define GPIO68_UTM_LINESTATE_0 MFP_CFG(GPIO68, AF3) +#define GPIO90_UTM_LINESTATE_0 MFP_CFG(GPIO90, AF3) +#define GPIO102_UTM_LINESTATE_0 MFP_CFG(GPIO102, AF3) +#define GPIO107_UTM_LINESTATE_0 MFP_CFG(GPIO107, AF4) +#define GPIO69_UTM_LINESTATE_1 MFP_CFG(GPIO69, AF3) +#define GPIO91_UTM_LINESTATE_1 MFP_CFG(GPIO91, AF3) +#define GPIO103_UTM_LINESTATE_1 MFP_CFG(GPIO103, AF3) + +#define GPIO41_U2D_PHYDATA_0 MFP_CFG(GPIO41, AF3) +#define GPIO42_U2D_PHYDATA_1 MFP_CFG(GPIO42, AF3) +#define GPIO43_U2D_PHYDATA_2 MFP_CFG(GPIO43, AF3) +#define GPIO44_U2D_PHYDATA_3 MFP_CFG(GPIO44, AF3) +#define GPIO45_U2D_PHYDATA_4 MFP_CFG(GPIO45, AF3) +#define GPIO46_U2D_PHYDATA_5 MFP_CFG(GPIO46, AF3) +#define GPIO47_U2D_PHYDATA_6 MFP_CFG(GPIO47, AF3) +#define GPIO48_U2D_PHYDATA_7 MFP_CFG(GPIO48, AF3) + +#define GPIO49_U2D_PHYDATA_0 MFP_CFG(GPIO49, AF3) +#define GPIO50_U2D_PHYDATA_1 MFP_CFG(GPIO50, AF3) +#define GPIO51_U2D_PHYDATA_2 MFP_CFG(GPIO51, AF3) +#define GPIO52_U2D_PHYDATA_3 MFP_CFG(GPIO52, AF3) +#define GPIO53_U2D_PHYDATA_4 MFP_CFG(GPIO53, AF3) +#define GPIO54_U2D_PHYDATA_5 MFP_CFG(GPIO54, AF3) +#define GPIO55_U2D_PHYDATA_6 MFP_CFG(GPIO55, AF3) +#define GPIO56_U2D_PHYDATA_7 MFP_CFG(GPIO56, AF3) + +#define GPIO37_U2D_OPMODE0 MFP_CFG(GPIO37, AF4) +#define GPIO61_U2D_OPMODE0 MFP_CFG(GPIO61, AF2) +#define GPIO88_U2D_OPMODE0 MFP_CFG(GPIO88, AF7) + +#define GPIO38_U2D_OPMODE1 MFP_CFG(GPIO38, AF4) +#define GPIO62_U2D_OPMODE1 MFP_CFG(GPIO62, AF2) +#define GPIO104_U2D_OPMODE1 MFP_CFG(GPIO104, AF4) +#define GPIO108_U2D_OPMODE1 MFP_CFG(GPIO108, AF5) + +#define GPIO74_U2D_RESET MFP_CFG(GPIO74, AF1) +#define GPIO93_U2D_RESET MFP_CFG(GPIO93, AF2) +#define GPIO98_U2D_RESET MFP_CFG(GPIO98, AF3) + +#define GPIO67_U2D_SUSPEND MFP_CFG(GPIO67, AF3) +#define GPIO96_U2D_SUSPEND MFP_CFG(GPIO96, AF2) +#define GPIO101_U2D_SUSPEND MFP_CFG(GPIO101, AF3) + +#define GPIO66_U2D_TERM_SEL MFP_CFG(GPIO66, AF5) +#define GPIO95_U2D_TERM_SEL MFP_CFG(GPIO95, AF3) +#define GPIO97_U2D_TERM_SEL MFP_CFG(GPIO97, AF7) +#define GPIO100_U2D_TERM_SEL MFP_CFG(GPIO100, AF5) + +#define GPIO39_U2D_TXVALID MFP_CFG(GPIO39, AF4) +#define GPIO70_U2D_TXVALID MFP_CFG(GPIO70, AF5) +#define GPIO83_U2D_TXVALID MFP_CFG(GPIO83, AF7) + +#define GPIO65_U2D_XCVR_SEL MFP_CFG(GPIO65, AF5) +#define GPIO94_U2D_XCVR_SEL MFP_CFG(GPIO94, AF3) +#define GPIO99_U2D_XCVR_SEL MFP_CFG(GPIO99, AF5) + +/* USB Host 1.1 */ +#define GPIO2_2_USBH_PEN MFP_CFG(GPIO2_2, AF1) +#define GPIO3_2_USBH_PWR MFP_CFG(GPIO3_2, AF1) + +/* USB P2 */ +#define GPIO97_USB_P2_2 MFP_CFG(GPIO97, AF2) +#define GPIO97_USB_P2_6 MFP_CFG(GPIO97, AF4) +#define GPIO98_USB_P2_2 MFP_CFG(GPIO98, AF4) +#define GPIO98_USB_P2_6 MFP_CFG(GPIO98, AF2) +#define GPIO99_USB_P2_1 MFP_CFG(GPIO99, AF2) +#define GPIO100_USB_P2_4 MFP_CFG(GPIO100, AF2) +#define GPIO101_USB_P2_8 MFP_CFG(GPIO101, AF2) +#define GPIO102_USB_P2_3 MFP_CFG(GPIO102, AF2) +#define GPIO103_USB_P2_5 MFP_CFG(GPIO103, AF2) +#define GPIO104_USB_P2_7 MFP_CFG(GPIO104, AF2) + +/* USB P3 */ +#define GPIO75_USB_P3_1 MFP_CFG(GPIO75, AF2) +#define GPIO76_USB_P3_2 MFP_CFG(GPIO76, AF2) +#define GPIO77_USB_P3_3 MFP_CFG(GPIO77, AF2) +#define GPIO78_USB_P3_4 MFP_CFG(GPIO78, AF2) +#define GPIO79_USB_P3_5 MFP_CFG(GPIO79, AF2) +#define GPIO80_USB_P3_6 MFP_CFG(GPIO80, AF2) + +#define GPIO13_CHOUT0 MFP_CFG(GPIO13, AF6) +#define GPIO14_CHOUT1 MFP_CFG(GPIO14, AF6) + +#define GPIO2_RDY MFP_CFG(GPIO2, AF1) +#define GPIO5_NPIOR MFP_CFG(GPIO5, AF3) + +#define GPIO11_PWM0_OUT MFP_CFG(GPIO11, AF1) +#define GPIO12_PWM1_OUT MFP_CFG(GPIO12, AF1) +#define GPIO13_PWM2_OUT MFP_CFG(GPIO13, AF1) +#define GPIO14_PWM3_OUT MFP_CFG(GPIO14, AF1) + +#endif /* __ASM_ARCH_MFP_PXA320_H */ diff --git a/include/asm-arm/arch-pxa/mfp.h b/include/asm-arm/arch-pxa/mfp.h new file mode 100644 index 0000000..6029174 --- /dev/null +++ b/include/asm-arm/arch-pxa/mfp.h @@ -0,0 +1,576 @@ +/* + * linux/include/asm-arm/arch-pxa/mfp.h + * + * Multi-Function Pin Definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * 2007-8-21: eric miao <eric.y.miao@gmail.com> + * initial version + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_MFP_H +#define __ASM_ARCH_MFP_H + +#define MFPR_BASE (0x40e10000) +#define MFPR_SIZE (PAGE_SIZE) + +#define mfp_to_gpio(m) ((m) % 128) + +/* list of all the configurable MFP pins */ +enum { + MFP_PIN_INVALID = -1, + + MFP_PIN_GPIO0 = 0, + MFP_PIN_GPIO1, + MFP_PIN_GPIO2, + MFP_PIN_GPIO3, + MFP_PIN_GPIO4, + MFP_PIN_GPIO5, + MFP_PIN_GPIO6, + MFP_PIN_GPIO7, + MFP_PIN_GPIO8, + MFP_PIN_GPIO9, + MFP_PIN_GPIO10, + MFP_PIN_GPIO11, + MFP_PIN_GPIO12, + MFP_PIN_GPIO13, + MFP_PIN_GPIO14, + MFP_PIN_GPIO15, + MFP_PIN_GPIO16, + MFP_PIN_GPIO17, + MFP_PIN_GPIO18, + MFP_PIN_GPIO19, + MFP_PIN_GPIO20, + MFP_PIN_GPIO21, + MFP_PIN_GPIO22, + MFP_PIN_GPIO23, + MFP_PIN_GPIO24, + MFP_PIN_GPIO25, + MFP_PIN_GPIO26, + MFP_PIN_GPIO27, + MFP_PIN_GPIO28, + MFP_PIN_GPIO29, + MFP_PIN_GPIO30, + MFP_PIN_GPIO31, + MFP_PIN_GPIO32, + MFP_PIN_GPIO33, + MFP_PIN_GPIO34, + MFP_PIN_GPIO35, + MFP_PIN_GPIO36, + MFP_PIN_GPIO37, + MFP_PIN_GPIO38, + MFP_PIN_GPIO39, + MFP_PIN_GPIO40, + MFP_PIN_GPIO41, + MFP_PIN_GPIO42, + MFP_PIN_GPIO43, + MFP_PIN_GPIO44, + MFP_PIN_GPIO45, + MFP_PIN_GPIO46, + MFP_PIN_GPIO47, + MFP_PIN_GPIO48, + MFP_PIN_GPIO49, + MFP_PIN_GPIO50, + MFP_PIN_GPIO51, + MFP_PIN_GPIO52, + MFP_PIN_GPIO53, + MFP_PIN_GPIO54, + MFP_PIN_GPIO55, + MFP_PIN_GPIO56, + MFP_PIN_GPIO57, + MFP_PIN_GPIO58, + MFP_PIN_GPIO59, + MFP_PIN_GPIO60, + MFP_PIN_GPIO61, + MFP_PIN_GPIO62, + MFP_PIN_GPIO63, + MFP_PIN_GPIO64, + MFP_PIN_GPIO65, + MFP_PIN_GPIO66, + MFP_PIN_GPIO67, + MFP_PIN_GPIO68, + MFP_PIN_GPIO69, + MFP_PIN_GPIO70, + MFP_PIN_GPIO71, + MFP_PIN_GPIO72, + MFP_PIN_GPIO73, + MFP_PIN_GPIO74, + MFP_PIN_GPIO75, + MFP_PIN_GPIO76, + MFP_PIN_GPIO77, + MFP_PIN_GPIO78, + MFP_PIN_GPIO79, + MFP_PIN_GPIO80, + MFP_PIN_GPIO81, + MFP_PIN_GPIO82, + MFP_PIN_GPIO83, + MFP_PIN_GPIO84, + MFP_PIN_GPIO85, + MFP_PIN_GPIO86, + MFP_PIN_GPIO87, + MFP_PIN_GPIO88, + MFP_PIN_GPIO89, + MFP_PIN_GPIO90, + MFP_PIN_GPIO91, + MFP_PIN_GPIO92, + MFP_PIN_GPIO93, + MFP_PIN_GPIO94, + MFP_PIN_GPIO95, + MFP_PIN_GPIO96, + MFP_PIN_GPIO97, + MFP_PIN_GPIO98, + MFP_PIN_GPIO99, + MFP_PIN_GPIO100, + MFP_PIN_GPIO101, + MFP_PIN_GPIO102, + MFP_PIN_GPIO103, + MFP_PIN_GPIO104, + MFP_PIN_GPIO105, + MFP_PIN_GPIO106, + MFP_PIN_GPIO107, + MFP_PIN_GPIO108, + MFP_PIN_GPIO109, + MFP_PIN_GPIO110, + MFP_PIN_GPIO111, + MFP_PIN_GPIO112, + MFP_PIN_GPIO113, + MFP_PIN_GPIO114, + MFP_PIN_GPIO115, + MFP_PIN_GPIO116, + MFP_PIN_GPIO117, + MFP_PIN_GPIO118, + MFP_PIN_GPIO119, + MFP_PIN_GPIO120, + MFP_PIN_GPIO121, + MFP_PIN_GPIO122, + MFP_PIN_GPIO123, + MFP_PIN_GPIO124, + MFP_PIN_GPIO125, + MFP_PIN_GPIO126, + MFP_PIN_GPIO127, + MFP_PIN_GPIO0_2, + MFP_PIN_GPIO1_2, + MFP_PIN_GPIO2_2, + MFP_PIN_GPIO3_2, + MFP_PIN_GPIO4_2, + MFP_PIN_GPIO5_2, + MFP_PIN_GPIO6_2, + MFP_PIN_GPIO7_2, + MFP_PIN_GPIO8_2, + MFP_PIN_GPIO9_2, + MFP_PIN_GPIO10_2, + MFP_PIN_GPIO11_2, + MFP_PIN_GPIO12_2, + MFP_PIN_GPIO13_2, + MFP_PIN_GPIO14_2, + MFP_PIN_GPIO15_2, + MFP_PIN_GPIO16_2, + MFP_PIN_GPIO17_2, + + MFP_PIN_ULPI_STP, + MFP_PIN_ULPI_NXT, + MFP_PIN_ULPI_DIR, + + MFP_PIN_nXCVREN, + MFP_PIN_DF_CLE_nOE, + MFP_PIN_DF_nADV1_ALE, + MFP_PIN_DF_SCLK_E, + MFP_PIN_DF_SCLK_S, + MFP_PIN_nBE0, + MFP_PIN_nBE1, + MFP_PIN_DF_nADV2_ALE, + MFP_PIN_DF_INT_RnB, + MFP_PIN_DF_nCS0, + MFP_PIN_DF_nCS1, + MFP_PIN_nLUA, + MFP_PIN_nLLA, + MFP_PIN_DF_nWE, + MFP_PIN_DF_ALE_nWE, + MFP_PIN_DF_nRE_nOE, + MFP_PIN_DF_ADDR0, + MFP_PIN_DF_ADDR1, + MFP_PIN_DF_ADDR2, + MFP_PIN_DF_ADDR3, + MFP_PIN_DF_IO0, + MFP_PIN_DF_IO1, + MFP_PIN_DF_IO2, + MFP_PIN_DF_IO3, + MFP_PIN_DF_IO4, + MFP_PIN_DF_IO5, + MFP_PIN_DF_IO6, + MFP_PIN_DF_IO7, + MFP_PIN_DF_IO8, + MFP_PIN_DF_IO9, + MFP_PIN_DF_IO10, + MFP_PIN_DF_IO11, + MFP_PIN_DF_IO12, + MFP_PIN_DF_IO13, + MFP_PIN_DF_IO14, + MFP_PIN_DF_IO15, + + MFP_PIN_MAX, +}; + +/* + * Table that determines the low power modes outputs, with actual settings + * used in parentheses for don't-care values. Except for the float output, + * the configured driven and pulled levels match, so if there is a need for + * non-LPM pulled output, the same configuration could probably be used. + * + * Output value sleep_oe_n sleep_data pullup_en pulldown_en pull_sel + * (bit 7) (bit 8) (bit 14d) (bit 13d) + * + * Drive 0 0 0 0 X (1) 0 + * Drive 1 0 1 X (1) 0 0 + * Pull hi (1) 1 X(1) 1 0 0 + * Pull lo (0) 1 X(0) 0 1 0 + * Z (float) 1 X(0) 0 0 0 + */ +#define MFP_LPM_DRIVE_LOW 0x8 +#define MFP_LPM_DRIVE_HIGH 0x6 +#define MFP_LPM_PULL_HIGH 0x7 +#define MFP_LPM_PULL_LOW 0x9 +#define MFP_LPM_FLOAT 0x1 +#define MFP_LPM_PULL_NEITHER 0x0 + +/* + * The pullup and pulldown state of the MFP pin is by default determined by + * selected alternate function. In case some buggy devices need to override + * this default behavior, pxa3xx_mfp_set_pull() can be invoked with one of + * the following definition as the parameter. + * + * Definition pull_sel pullup_en pulldown_en + * MFP_PULL_HIGH 1 1 0 + * MFP_PULL_LOW 1 0 1 + * MFP_PULL_BOTH 1 1 1 + * MFP_PULL_NONE 1 0 0 + * MFP_PULL_DEFAULT 0 X X + * + * NOTE: pxa3xx_mfp_set_pull() will modify the PULLUP_EN and PULLDOWN_EN + * bits, which will cause potential conflicts with the low power mode + * setting, device drivers should take care of this + */ +#define MFP_PULL_BOTH (0x7u) +#define MFP_PULL_HIGH (0x6u) +#define MFP_PULL_LOW (0x5u) +#define MFP_PULL_NONE (0x4u) +#define MFP_PULL_DEFAULT (0x0u) + +#define MFP_AF0 (0) +#define MFP_AF1 (1) +#define MFP_AF2 (2) +#define MFP_AF3 (3) +#define MFP_AF4 (4) +#define MFP_AF5 (5) +#define MFP_AF6 (6) +#define MFP_AF7 (7) + +#define MFP_DS01X (0) +#define MFP_DS02X (1) +#define MFP_DS03X (2) +#define MFP_DS04X (3) +#define MFP_DS06X (4) +#define MFP_DS08X (5) +#define MFP_DS10X (6) +#define MFP_DS12X (7) + +#define MFP_EDGE_BOTH 0x3 +#define MFP_EDGE_RISE 0x2 +#define MFP_EDGE_FALL 0x1 +#define MFP_EDGE_NONE 0x0 + +#define MFPR_AF_MASK 0x0007 +#define MFPR_DRV_MASK 0x1c00 +#define MFPR_RDH_MASK 0x0200 +#define MFPR_LPM_MASK 0xe180 +#define MFPR_PULL_MASK 0xe000 +#define MFPR_EDGE_MASK 0x0070 + +#define MFPR_ALT_OFFSET 0 +#define MFPR_ERE_OFFSET 4 +#define MFPR_EFE_OFFSET 5 +#define MFPR_EC_OFFSET 6 +#define MFPR_SON_OFFSET 7 +#define MFPR_SD_OFFSET 8 +#define MFPR_SS_OFFSET 9 +#define MFPR_DRV_OFFSET 10 +#define MFPR_PD_OFFSET 13 +#define MFPR_PU_OFFSET 14 +#define MFPR_PS_OFFSET 15 + +#define MFPR(af, drv, rdh, lpm, edge) \ + (((af) & 0x7) | (((drv) & 0x7) << 10) |\ + (((rdh) & 0x1) << 9) |\ + (((lpm) & 0x3) << 7) |\ + (((lpm) & 0x4) << 12)|\ + (((lpm) & 0x8) << 10)|\ + ((!(edge)) << 6) |\ + (((edge) & 0x1) << 5) |\ + (((edge) & 0x2) << 3)) + +/* + * a possible MFP configuration is represented by a 32-bit integer + * bit 0..15 - MFPR value (16-bit) + * bit 16..31 - mfp pin index (used to obtain the MFPR offset) + * + * to facilitate the definition, the following macros are provided + * + * MFPR_DEFAULT - default MFPR value, with + * alternate function = 0, + * drive strength = fast 1mA (MFP_DS01X) + * low power mode = default + * release dalay hold = false (RDH bit) + * edge detection = none + * + * MFP_CFG - default MFPR value with alternate function + * MFP_CFG_DRV - default MFPR value with alternate function and + * pin drive strength + * MFP_CFG_LPM - default MFPR value with alternate function and + * low power mode + * MFP_CFG_X - default MFPR value with alternate function, + * pin drive strength and low power mode + * + * use + * + * MFP_CFG_PIN - to get the MFP pin index + * MFP_CFG_VAL - to get the corresponding MFPR value + */ + +typedef uint32_t mfp_cfg_t; + +#define MFP_CFG_PIN(mfp_cfg) (((mfp_cfg) >> 16) & 0xffff) +#define MFP_CFG_VAL(mfp_cfg) ((mfp_cfg) & 0xffff) + +#define MFPR_DEFAULT (0x0000) + +#define MFP_CFG(pin, af) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af)) + +#define MFP_CFG_DRV(pin, af, drv) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af)) + +#define MFP_CFG_LPM(pin, af, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +#define MFP_CFG_X(pin, af, drv, lpm) \ + ((MFP_PIN_##pin << 16) | MFPR_DEFAULT |\ + ((MFP_##drv) << 10) | (MFP_##af) |\ + (((MFP_LPM_##lpm) & 0x3) << 7) |\ + (((MFP_LPM_##lpm) & 0x4) << 12) |\ + (((MFP_LPM_##lpm) & 0x8) << 10)) + +/* common MFP configurations - processor specific ones defined + * in mfp-pxa3xx.h + */ +#define GPIO0_GPIO MFP_CFG(GPIO0, AF0) +#define GPIO1_GPIO MFP_CFG(GPIO1, AF0) +#define GPIO2_GPIO MFP_CFG(GPIO2, AF0) +#define GPIO3_GPIO MFP_CFG(GPIO3, AF0) +#define GPIO4_GPIO MFP_CFG(GPIO4, AF0) +#define GPIO5_GPIO MFP_CFG(GPIO5, AF0) +#define GPIO6_GPIO MFP_CFG(GPIO6, AF0) +#define GPIO7_GPIO MFP_CFG(GPIO7, AF0) +#define GPIO8_GPIO MFP_CFG(GPIO8, AF0) +#define GPIO9_GPIO MFP_CFG(GPIO9, AF0) +#define GPIO10_GPIO MFP_CFG(GPIO10, AF0) +#define GPIO11_GPIO MFP_CFG(GPIO11, AF0) +#define GPIO12_GPIO MFP_CFG(GPIO12, AF0) +#define GPIO13_GPIO MFP_CFG(GPIO13, AF0) +#define GPIO14_GPIO MFP_CFG(GPIO14, AF0) +#define GPIO15_GPIO MFP_CFG(GPIO15, AF0) +#define GPIO16_GPIO MFP_CFG(GPIO16, AF0) +#define GPIO17_GPIO MFP_CFG(GPIO17, AF0) +#define GPIO18_GPIO MFP_CFG(GPIO18, AF0) +#define GPIO19_GPIO MFP_CFG(GPIO19, AF0) +#define GPIO20_GPIO MFP_CFG(GPIO20, AF0) +#define GPIO21_GPIO MFP_CFG(GPIO21, AF0) +#define GPIO22_GPIO MFP_CFG(GPIO22, AF0) +#define GPIO23_GPIO MFP_CFG(GPIO23, AF0) +#define GPIO24_GPIO MFP_CFG(GPIO24, AF0) +#define GPIO25_GPIO MFP_CFG(GPIO25, AF0) +#define GPIO26_GPIO MFP_CFG(GPIO26, AF0) +#define GPIO27_GPIO MFP_CFG(GPIO27, AF0) +#define GPIO28_GPIO MFP_CFG(GPIO28, AF0) +#define GPIO29_GPIO MFP_CFG(GPIO29, AF0) +#define GPIO30_GPIO MFP_CFG(GPIO30, AF0) +#define GPIO31_GPIO MFP_CFG(GPIO31, AF0) +#define GPIO32_GPIO MFP_CFG(GPIO32, AF0) +#define GPIO33_GPIO MFP_CFG(GPIO33, AF0) +#define GPIO34_GPIO MFP_CFG(GPIO34, AF0) +#define GPIO35_GPIO MFP_CFG(GPIO35, AF0) +#define GPIO36_GPIO MFP_CFG(GPIO36, AF0) +#define GPIO37_GPIO MFP_CFG(GPIO37, AF0) +#define GPIO38_GPIO MFP_CFG(GPIO38, AF0) +#define GPIO39_GPIO MFP_CFG(GPIO39, AF0) +#define GPIO40_GPIO MFP_CFG(GPIO40, AF0) +#define GPIO41_GPIO MFP_CFG(GPIO41, AF0) +#define GPIO42_GPIO MFP_CFG(GPIO42, AF0) +#define GPIO43_GPIO MFP_CFG(GPIO43, AF0) +#define GPIO44_GPIO MFP_CFG(GPIO44, AF0) +#define GPIO45_GPIO MFP_CFG(GPIO45, AF0) + +#define GPIO47_GPIO MFP_CFG(GPIO47, AF0) +#define GPIO48_GPIO MFP_CFG(GPIO48, AF0) + +#define GPIO53_GPIO MFP_CFG(GPIO53, AF0) +#define GPIO54_GPIO MFP_CFG(GPIO54, AF0) +#define GPIO55_GPIO MFP_CFG(GPIO55, AF0) + +#define GPIO57_GPIO MFP_CFG(GPIO57, AF0) + +#define GPIO63_GPIO MFP_CFG(GPIO63, AF0) +#define GPIO64_GPIO MFP_CFG(GPIO64, AF0) +#define GPIO65_GPIO MFP_CFG(GPIO65, AF0) +#define GPIO66_GPIO MFP_CFG(GPIO66, AF0) +#define GPIO67_GPIO MFP_CFG(GPIO67, AF0) +#define GPIO68_GPIO MFP_CFG(GPIO68, AF0) +#define GPIO69_GPIO MFP_CFG(GPIO69, AF0) +#define GPIO70_GPIO MFP_CFG(GPIO70, AF0) +#define GPIO71_GPIO MFP_CFG(GPIO71, AF0) +#define GPIO72_GPIO MFP_CFG(GPIO72, AF0) +#define GPIO73_GPIO MFP_CFG(GPIO73, AF0) +#define GPIO74_GPIO MFP_CFG(GPIO74, AF0) +#define GPIO75_GPIO MFP_CFG(GPIO75, AF0) +#define GPIO76_GPIO MFP_CFG(GPIO76, AF0) +#define GPIO77_GPIO MFP_CFG(GPIO77, AF0) +#define GPIO78_GPIO MFP_CFG(GPIO78, AF0) +#define GPIO79_GPIO MFP_CFG(GPIO79, AF0) +#define GPIO80_GPIO MFP_CFG(GPIO80, AF0) +#define GPIO81_GPIO MFP_CFG(GPIO81, AF0) +#define GPIO82_GPIO MFP_CFG(GPIO82, AF0) +#define GPIO83_GPIO MFP_CFG(GPIO83, AF0) +#define GPIO84_GPIO MFP_CFG(GPIO84, AF0) +#define GPIO85_GPIO MFP_CFG(GPIO85, AF0) +#define GPIO86_GPIO MFP_CFG(GPIO86, AF0) +#define GPIO87_GPIO MFP_CFG(GPIO87, AF0) +#define GPIO88_GPIO MFP_CFG(GPIO88, AF0) +#define GPIO89_GPIO MFP_CFG(GPIO89, AF0) +#define GPIO90_GPIO MFP_CFG(GPIO90, AF0) +#define GPIO91_GPIO MFP_CFG(GPIO91, AF0) +#define GPIO92_GPIO MFP_CFG(GPIO92, AF0) +#define GPIO93_GPIO MFP_CFG(GPIO93, AF0) +#define GPIO94_GPIO MFP_CFG(GPIO94, AF0) +#define GPIO95_GPIO MFP_CFG(GPIO95, AF0) +#define GPIO96_GPIO MFP_CFG(GPIO96, AF0) +#define GPIO97_GPIO MFP_CFG(GPIO97, AF0) +#define GPIO98_GPIO MFP_CFG(GPIO98, AF0) +#define GPIO99_GPIO MFP_CFG(GPIO99, AF0) +#define GPIO100_GPIO MFP_CFG(GPIO100, AF0) +#define GPIO101_GPIO MFP_CFG(GPIO101, AF0) +#define GPIO102_GPIO MFP_CFG(GPIO102, AF0) +#define GPIO103_GPIO MFP_CFG(GPIO103, AF0) +#define GPIO104_GPIO MFP_CFG(GPIO104, AF0) +#define GPIO105_GPIO MFP_CFG(GPIO105, AF0) +#define GPIO106_GPIO MFP_CFG(GPIO106, AF0) +#define GPIO107_GPIO MFP_CFG(GPIO107, AF0) +#define GPIO108_GPIO MFP_CFG(GPIO108, AF0) +#define GPIO109_GPIO MFP_CFG(GPIO109, AF0) +#define GPIO110_GPIO MFP_CFG(GPIO110, AF0) +#define GPIO111_GPIO MFP_CFG(GPIO111, AF0) +#define GPIO112_GPIO MFP_CFG(GPIO112, AF0) +#define GPIO113_GPIO MFP_CFG(GPIO113, AF0) +#define GPIO114_GPIO MFP_CFG(GPIO114, AF0) +#define GPIO115_GPIO MFP_CFG(GPIO115, AF0) +#define GPIO116_GPIO MFP_CFG(GPIO116, AF0) +#define GPIO117_GPIO MFP_CFG(GPIO117, AF0) +#define GPIO118_GPIO MFP_CFG(GPIO118, AF0) +#define GPIO119_GPIO MFP_CFG(GPIO119, AF0) +#define GPIO120_GPIO MFP_CFG(GPIO120, AF0) +#define GPIO121_GPIO MFP_CFG(GPIO121, AF0) +#define GPIO122_GPIO MFP_CFG(GPIO122, AF0) +#define GPIO123_GPIO MFP_CFG(GPIO123, AF0) +#define GPIO124_GPIO MFP_CFG(GPIO124, AF0) +#define GPIO125_GPIO MFP_CFG(GPIO125, AF0) +#define GPIO126_GPIO MFP_CFG(GPIO126, AF0) +#define GPIO127_GPIO MFP_CFG(GPIO127, AF0) + +#define GPIO0_2_GPIO MFP_CFG(GPIO0_2, AF0) +#define GPIO1_2_GPIO MFP_CFG(GPIO1_2, AF0) +#define GPIO2_2_GPIO MFP_CFG(GPIO2_2, AF0) +#define GPIO3_2_GPIO MFP_CFG(GPIO3_2, AF0) +#define GPIO4_2_GPIO MFP_CFG(GPIO4_2, AF0) +#define GPIO5_2_GPIO MFP_CFG(GPIO5_2, AF0) +#define GPIO6_2_GPIO MFP_CFG(GPIO6_2, AF0) + +/* + * each MFP pin will have a MFPR register, since the offset of the + * register varies between processors, the processor specific code + * should initialize the pin offsets by pxa3xx_mfp_init_addr() + * + * pxa3xx_mfp_init_addr - accepts a table of "pxa3xx_mfp_addr_map" + * structure, which represents a range of MFP pins from "start" to + * "end", with the offset begining at "offset", to define a single + * pin, let "end" = -1 + * + * use + * + * MFP_ADDR_X() to define a range of pins + * MFP_ADDR() to define a single pin + * MFP_ADDR_END to signal the end of pin offset definitions + */ +struct pxa3xx_mfp_addr_map { + unsigned int start; + unsigned int end; + unsigned long offset; +}; + +#define MFP_ADDR_X(start, end, offset) \ + { MFP_PIN_##start, MFP_PIN_##end, offset } + +#define MFP_ADDR(pin, offset) \ + { MFP_PIN_##pin, -1, offset } + +#define MFP_ADDR_END { MFP_PIN_INVALID, 0 } + +struct pxa3xx_mfp_pin { + unsigned long mfpr_off; /* MFPRxx register offset */ + unsigned long mfpr_val; /* MFPRxx register value */ +}; + +/* + * pxa3xx_mfp_read()/pxa3xx_mfp_write() - for direct read/write access + * to the MFPR register + */ +unsigned long pxa3xx_mfp_read(int mfp); +void pxa3xx_mfp_write(int mfp, unsigned long mfpr_val); + +/* + * pxa3xx_mfp_set_afds - set MFP alternate function and drive strength + * pxa3xx_mfp_set_rdh - set MFP release delay hold on/off + * pxa3xx_mfp_set_lpm - set MFP low power mode state + * pxa3xx_mfp_set_edge - set MFP edge detection in low power mode + * + * use these functions to override/change the default configuration + * done by pxa3xx_mfp_set_config(s) + */ +void pxa3xx_mfp_set_afds(int mfp, int af, int ds); +void pxa3xx_mfp_set_rdh(int mfp, int rdh); +void pxa3xx_mfp_set_lpm(int mfp, int lpm); +void pxa3xx_mfp_set_edge(int mfp, int edge); + +/* + * pxa3xx_mfp_config - configure the MFPR registers + * + * used by board specific initialization code + */ +void pxa3xx_mfp_config(mfp_cfg_t *mfp_cfgs, int num); + +/* + * pxa3xx_mfp_init_addr() - initialize the mapping between mfp pin + * index and MFPR register offset + * + * used by processor specific code + */ +void __init pxa3xx_mfp_init_addr(struct pxa3xx_mfp_addr_map *); +void __init pxa3xx_init_mfp(void); + +#endif /* __ASM_ARCH_MFP_H */ diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h index e68b593..67f53e0 100644 --- a/include/asm-arm/arch-pxa/pxa-regs.h +++ b/include/asm-arm/arch-pxa/pxa-regs.h @@ -1177,7 +1177,7 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#ifdef CONFIG_PXA27x +#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) /* Interrupt Controller */ diff --git a/include/asm-arm/arch-pxa/pxa3xx-regs.h b/include/asm-arm/arch-pxa/pxa3xx-regs.h new file mode 100644 index 0000000..3900a0c --- /dev/null +++ b/include/asm-arm/arch-pxa/pxa3xx-regs.h @@ -0,0 +1,75 @@ +/* + * linux/include/asm-arm/arch-pxa/pxa3xx-regs.h + * + * PXA3xx specific register definitions + * + * Copyright (C) 2007 Marvell International Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARCH_PXA3XX_REGS_H +#define __ASM_ARCH_PXA3XX_REGS_H + +/* + * Application Subsystem Clock + */ +#define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */ +#define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */ +#define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */ +#define CKENA __REG(0x4134000C) /* A Clock Enable Register */ +#define CKENB __REG(0x41340010) /* B Clock Enable Register */ +#define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */ + +/* + * Clock Enable Bit + */ +#define CKEN_LCD 1 /* < LCD Clock Enable */ +#define CKEN_USBH 2 /* < USB host clock enable */ +#define CKEN_CAMERA 3 /* < Camera interface clock enable */ +#define CKEN_NAND 4 /* < NAND Flash Controller Clock Enable */ +#define CKEN_USB2 6 /* < USB 2.0 client clock enable. */ +#define CKEN_DMC 8 /* < Dynamic Memory Controller clock enable */ +#define CKEN_SMC 9 /* < Static Memory Controller clock enable */ +#define CKEN_ISC 10 /* < Internal SRAM Controller clock enable */ +#define CKEN_BOOT 11 /* < Boot rom clock enable */ +#define CKEN_MMC1 12 /* < MMC1 Clock enable */ +#define CKEN_MMC2 13 /* < MMC2 clock enable */ +#define CKEN_KEYPAD 14 /* < Keypand Controller Clock Enable */ +#define CKEN_CIR 15 /* < Consumer IR Clock Enable */ +#define CKEN_USIM0 17 /* < USIM[0] Clock Enable */ +#define CKEN_USIM1 18 /* < USIM[1] Clock Enable */ +#define CKEN_TPM 19 /* < TPM clock enable */ +#define CKEN_UDC 20 /* < UDC clock enable */ +#define CKEN_BTUART 21 /* < BTUART clock enable */ +#define CKEN_FFUART 22 /* < FFUART clock enable */ +#define CKEN_STUART 23 /* < STUART clock enable */ +#define CKEN_AC97 24 /* < AC97 clock enable */ +#define CKEN_TOUCH 25 /* < Touch screen Interface Clock Enable */ +#define CKEN_SSP1 26 /* < SSP1 clock enable */ +#define CKEN_SSP2 27 /* < SSP2 clock enable */ +#define CKEN_SSP3 28 /* < SSP3 clock enable */ +#define CKEN_SSP4 29 /* < SSP4 clock enable */ +#define CKEN_MSL0 30 /* < MSL0 clock enable */ +#define CKEN_PWM0 32 /* < PWM[0] clock enable */ +#define CKEN_PWM1 33 /* < PWM[1] clock enable */ +#define CKEN_I2C 36 /* < I2C clock enable */ +#define CKEN_INTC 38 /* < Interrupt controller clock enable */ +#define CKEN_GPIO 39 /* < GPIO clock enable */ +#define CKEN_1WIRE 40 /* < 1-wire clock enable */ +#define CKEN_HSIO2 41 /* < HSIO2 clock enable */ +#define CKEN_MINI_IM 48 /* < Mini-IM */ +#define CKEN_MINI_LCD 49 /* < Mini LCD */ + +#if defined(CONFIG_CPU_PXA310) +#define CKEN_MMC3 5 /* < MMC3 Clock Enable */ +#define CKEN_MVED 43 /* < MVED clock enable */ +#endif + +/* Note: GCU clock enable bit differs on PXA300/PXA310 and PXA320 */ +#define PXA300_CKEN_GRAPHICS 42 /* Graphics controller clock enable */ +#define PXA320_CKEN_GRAPHICS 7 /* Graphics controller clock enable */ + +#endif /* __ASM_ARCH_PXA3XX_REGS_H */ diff --git a/include/asm-arm/arch-pxa/timex.h b/include/asm-arm/arch-pxa/timex.h index 2473bb5..8d882f0 100644 --- a/include/asm-arm/arch-pxa/timex.h +++ b/include/asm-arm/arch-pxa/timex.h @@ -21,4 +21,6 @@ #else #define CLOCK_TICK_RATE 3250000 #endif +#else +#define CLOCK_TICK_RATE 3250000 #endif diff --git a/include/asm-arm/arch-pxa/zylonite.h b/include/asm-arm/arch-pxa/zylonite.h new file mode 100644 index 0000000..f58b591 --- /dev/null +++ b/include/asm-arm/arch-pxa/zylonite.h @@ -0,0 +1,35 @@ +#ifndef __ASM_ARCH_ZYLONITE_H +#define __ASM_ARCH_ZYLONITE_H + +#define ZYLONITE_ETH_PHYS 0x14000000 + +/* the following variables are processor specific and initialized + * by the corresponding zylonite_pxa3xx_init() + */ +extern int gpio_backlight; +extern int gpio_eth_irq; + +extern int lcd_id; +extern int lcd_orientation; + +#ifdef CONFIG_CPU_PXA300 +extern void zylonite_pxa300_init(void); +#else +static inline void zylonite_pxa300_init(void) +{ + if (cpu_is_pxa300() || cpu_is_pxa310()) + panic("%s: PXA300/PXA310 not supported\n", __FUNCTION__); +} +#endif + +#ifdef CONFIG_CPU_PXA320 +extern void zylonite_pxa320_init(void); +#else +static inline void zylonite_pxa320_init(void) +{ + if (cpu_is_pxa320()) + panic("%s: PXA320 not supported\n", __FUNCTION__); +} +#endif + +#endif /* __ASM_ARCH_ZYLONITE_H */ diff --git a/include/asm-arm/arch-rpc/uncompress.h b/include/asm-arm/arch-rpc/uncompress.h index 06231ed..b8e29ef 100644 --- a/include/asm-arm/arch-rpc/uncompress.h +++ b/include/asm-arm/arch-rpc/uncompress.h @@ -11,9 +11,11 @@ #include <asm/hardware.h> #include <asm/io.h> +#include <asm/setup.h> +#include <asm/page.h> -int video_num_columns, video_num_lines, video_size_row; -int white, bytes_per_char_h; +int video_size_row; +unsigned char bytes_per_char_h; extern unsigned long con_charconvtable[256]; struct param_struct { @@ -64,6 +66,13 @@ extern __attribute__((pure)) struct param_struct *params(void); #define params (params()) #ifndef STANDALONE_DEBUG +static unsigned long video_num_cols; +static unsigned long video_num_rows; +static unsigned long video_x; +static unsigned long video_y; +static unsigned char bytes_per_char_v; +static int white; + /* * This does not append a newline */ @@ -73,27 +82,27 @@ static void putc(int c) int x,y; char *ptr; - x = params->video_x; - y = params->video_y; + x = video_x; + y = video_y; if (c == '\n') { - if (++y >= video_num_lines) + if (++y >= video_num_rows) y--; } else if (c == '\r') { x = 0; } else { - ptr = VIDMEM + ((y*video_num_columns*params->bytes_per_char_v+x)*bytes_per_char_h); + ptr = VIDMEM + ((y*video_num_cols*bytes_per_char_v+x)*bytes_per_char_h); ll_write_char(ptr, c, white); - if (++x >= video_num_columns) { + if (++x >= video_num_cols) { x = 0; - if ( ++y >= video_num_lines ) { + if ( ++y >= video_num_rows ) { y--; } } } - params->video_x = x; - params->video_y = y; + video_x = x; + video_y = y; } static inline void flush(void) @@ -108,11 +117,44 @@ static void error(char *x); static void arch_decomp_setup(void) { int i; + struct tag *t = (struct tag *)params; + unsigned int nr_pages = 0, page_size = PAGE_SIZE; + + if (t->hdr.tag == ATAG_CORE) + { + for (; t->hdr.size; t = tag_next(t)) + { + if (t->hdr.tag == ATAG_VIDEOTEXT) + { + video_num_rows = t->u.videotext.video_lines; + video_num_cols = t->u.videotext.video_cols; + bytes_per_char_h = t->u.videotext.video_points; + bytes_per_char_v = t->u.videotext.video_points; + video_x = t->u.videotext.x; + video_y = t->u.videotext.y; + } + + if (t->hdr.tag == ATAG_MEM) + { + page_size = PAGE_SIZE; + nr_pages += (t->u.mem.size / PAGE_SIZE); + } + } + } + else + { + nr_pages = params->nr_pages; + page_size = params->page_size; + video_num_rows = params->video_num_rows; + video_num_cols = params->video_num_cols; + video_x = params->video_x; + video_y = params->video_y; + bytes_per_char_h = params->bytes_per_char_h; + bytes_per_char_v = params->bytes_per_char_v; + } + + video_size_row = video_num_cols * bytes_per_char_h; - video_num_lines = params->video_num_rows; - video_num_columns = params->video_num_cols; - bytes_per_char_h = params->bytes_per_char_h; - video_size_row = video_num_columns * bytes_per_char_h; if (bytes_per_char_h == 4) for (i = 0; i < 256; i++) con_charconvtable[i] = @@ -146,7 +188,7 @@ static void arch_decomp_setup(void) white = 7; } - if (params->nr_pages * params->page_size < 4096*1024) error("<4M of mem\n"); + if (nr_pages * page_size < 4096*1024) error("<4M of mem\n"); } #endif diff --git a/include/asm-arm/arch-s3c2410/irqs.h b/include/asm-arm/arch-s3c2410/irqs.h index 3b49cd1..996f654 100644 --- a/include/asm-arm/arch-s3c2410/irqs.h +++ b/include/asm-arm/arch-s3c2410/irqs.h @@ -112,6 +112,13 @@ #define IRQ_TC S3C2410_IRQSUB(9) #define IRQ_ADC S3C2410_IRQSUB(10) +/* extra irqs for s3c2412 */ + +#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21) + +#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13) +#define IRQ_S3C2412_CF S3C2410_IRQSUB(14) + /* extra irqs for s3c2440 */ #define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */ diff --git a/include/asm-arm/arch-s3c2410/regs-gpio.h b/include/asm-arm/arch-s3c2410/regs-gpio.h index dea578b..b693158 100644 --- a/include/asm-arm/arch-s3c2410/regs-gpio.h +++ b/include/asm-arm/arch-s3c2410/regs-gpio.h @@ -1140,10 +1140,16 @@ /* definitions for each pin bit */ #define S3C2412_SLPCON_LOW(x) ( 0x00 << ((x) * 2)) -#define S3C2412_SLPCON_HI(x) ( 0x01 << ((x) * 2)) +#define S3C2412_SLPCON_HIGH(x) ( 0x01 << ((x) * 2)) #define S3C2412_SLPCON_IN(x) ( 0x02 << ((x) * 2)) -#define S3C2412_SLPCON_PDWN(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_PULL(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_EINT(x) ( 0x02 << ((x) * 2)) /* only IRQ pins */ #define S3C2412_SLPCON_MASK(x) ( 0x03 << ((x) * 2)) +#define S3C2412_SLPCON_ALL_LOW (0x0) +#define S3C2412_SLPCON_ALL_HIGH (0x11111111 | 0x44444444) +#define S3C2412_SLPCON_ALL_IN (0x22222222 | 0x88888888) +#define S3C2412_SLPCON_ALL_PULL (0x33333333) + #endif /* __ASM_ARCH_REGS_GPIO_H */ diff --git a/include/asm-arm/arch-s3c2410/regs-power.h b/include/asm-arm/arch-s3c2410/regs-power.h index 94ff965..f79987b 100644 --- a/include/asm-arm/arch-s3c2410/regs-power.h +++ b/include/asm-arm/arch-s3c2410/regs-power.h @@ -18,6 +18,11 @@ #define S3C2412_PWRMODECON S3C24XX_PWRREG(0x20) #define S3C2412_PWRCFG S3C24XX_PWRREG(0x24) +#define S3C2412_INFORM0 S3C24XX_PWRREG(0x70) +#define S3C2412_INFORM1 S3C24XX_PWRREG(0x74) +#define S3C2412_INFORM2 S3C24XX_PWRREG(0x78) +#define S3C2412_INFORM3 S3C24XX_PWRREG(0x7C) + #define S3C2412_PWRCFG_BATF_IGNORE (0<<0) #define S3C2412_PWRCFG_BATF_SLEEP (3<<0) #define S3C2412_PWRCFG_BATF_MASK (3<<0) diff --git a/include/asm-arm/arch-s3c2410/regs-s3c2412.h b/include/asm-arm/arch-s3c2410/regs-s3c2412.h index 8ca6a3b..783b18f 100644 --- a/include/asm-arm/arch-s3c2410/regs-s3c2412.h +++ b/include/asm-arm/arch-s3c2410/regs-s3c2412.h @@ -17,5 +17,7 @@ #define S3C2412_SWRST (S3C24XX_VA_CLKPWR + 0x30) #define S3C2412_SWRST_RESET (0x533C2412) +/* see regs-power.h for the other registers in the power block. */ + #endif /* __ASM_ARCH_REGS_S3C2412_H */ diff --git a/include/asm-arm/arch-sa1100/SA-1101.h b/include/asm-arm/arch-sa1100/SA-1101.h index 527d887..65ca8c7 100644 --- a/include/asm-arm/arch-sa1100/SA-1101.h +++ b/include/asm-arm/arch-sa1100/SA-1101.h @@ -106,7 +106,7 @@ #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \ (( (x) - 8 ) << FShft (SMCR_DCAC)) #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\ - (( (x) - 9 ) << FShft (SMCR_DRAC) + (( (x) - 9 ) << FShft (SMCR_DRAC)) #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */ #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */ @@ -394,7 +394,7 @@ #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus))) #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask))) #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette))) -#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl)) +#define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))) #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest))) #define VideoControl_VgaEn 0x00000000 diff --git a/include/asm-arm/dma-mapping.h b/include/asm-arm/dma-mapping.h index c8b5d0d..678134b 100644 --- a/include/asm-arm/dma-mapping.h +++ b/include/asm-arm/dma-mapping.h @@ -17,7 +17,7 @@ * platforms with CONFIG_DMABOUNCE. * Use the driver DMA support - see dma-mapping.h (dma_sync_*) */ -extern void consistent_sync(const void *kaddr, size_t size, int rw); +extern void dma_cache_maint(const void *kaddr, size_t size, int rw); /* * Return whether the given device DMA address mask can be supported @@ -165,7 +165,7 @@ dma_map_single(struct device *dev, void *cpu_addr, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync(cpu_addr, size, dir); + dma_cache_maint(cpu_addr, size, dir); return virt_to_dma(dev, (unsigned long)cpu_addr); } @@ -278,7 +278,7 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } return nents; @@ -334,7 +334,7 @@ dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); } static inline void @@ -342,7 +342,7 @@ dma_sync_single_for_device(struct device *dev, dma_addr_t handle, size_t size, enum dma_data_direction dir) { if (!arch_is_coherent()) - consistent_sync((void *)dma_to_virt(dev, handle), size, dir); + dma_cache_maint((void *)dma_to_virt(dev, handle), size, dir); } #else extern void dma_sync_single_for_cpu(struct device*, dma_addr_t, size_t, enum dma_data_direction); @@ -373,7 +373,7 @@ dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } } @@ -386,7 +386,7 @@ dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, int nents, for (i = 0; i < nents; i++, sg++) { char *virt = page_address(sg->page) + sg->offset; if (!arch_is_coherent()) - consistent_sync(virt, sg->length, dir); + dma_cache_maint(virt, sg->length, dir); } } #else diff --git a/include/asm-arm/hardware/it8152.h b/include/asm-arm/hardware/it8152.h new file mode 100644 index 0000000..aaebb61 --- /dev/null +++ b/include/asm-arm/hardware/it8152.h @@ -0,0 +1,99 @@ +/* + * linux/include/arm/hardware/it8152.h + * + * Copyright Compulab Ltd., 2006,2007 + * Mike Rapoport <mike@compulab.co.il> + * + * ITE 8152 companion chip register definitions + */ + +#ifndef __ASM_HARDWARE_IT8152_H +#define __ASM_HARDWARE_IT8152_H +extern unsigned long it8152_base_address; + +#define IT8152_IO_BASE (it8152_base_address + 0x03e00000) +#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000) + +#define __REG_IT8152(x) (it8152_base_address + (x)) + +#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800) +#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804) + +#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300) +#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304) +#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308) +#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C) +#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310) +#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314) +#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320) +#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324) +#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328) +#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C) +#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330) +#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334) +#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340) +#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344) +#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348) +#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C) +#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350) +#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354) +#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC) + +#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500) + +/* + Interrup contoler per register summary: + --------------------------------------- + LCDNIRR: + IT8152_LD_IRQ(8) PCICLK stop + IT8152_LD_IRQ(7) MCLK ready + IT8152_LD_IRQ(6) s/w + IT8152_LD_IRQ(5) UART + IT8152_LD_IRQ(4) GPIO + IT8152_LD_IRQ(3) TIMER 4 + IT8152_LD_IRQ(2) TIMER 3 + IT8152_LD_IRQ(1) TIMER 2 + IT8152_LD_IRQ(0) TIMER 1 + + LPCNIRR: + IT8152_LP_IRQ(x) serial IRQ x + + PCIDNIRR: + IT8152_PD_IRQ(14) PCISERR + IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR) + IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR) + IT8152_PD_IRQ(11) PCI INTD + IT8152_PD_IRQ(10) PCI INTC + IT8152_PD_IRQ(9) PCI INTB + IT8152_PD_IRQ(8) PCI INTA + IT8152_PD_IRQ(7) serial INTD + IT8152_PD_IRQ(6) serial INTC + IT8152_PD_IRQ(5) serial INTB + IT8152_PD_IRQ(4) serial INTA + IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR) + IT8152_PD_IRQ(2) chaining DMA (CDMAR) + IT8152_PD_IRQ(1) USB (USBR) + IT8152_PD_IRQ(0) Audio controller (ACR) + */ +/* frequently used interrupts */ +#define IT8152_PCISERR IT8152_PD_IRQ(14) +#define IT8152_H2PTADR IT8152_PD_IRQ(13) +#define IT8152_H2PMAR IT8152_PD_IRQ(12) +#define IT8152_PCI_INTD IT8152_PD_IRQ(11) +#define IT8152_PCI_INTC IT8152_PD_IRQ(10) +#define IT8152_PCI_INTB IT8152_PD_IRQ(9) +#define IT8152_PCI_INTA IT8152_PD_IRQ(8) +#define IT8152_CDMA_INT IT8152_PD_IRQ(2) +#define IT8152_USB_INT IT8152_PD_IRQ(1) +#define IT8152_AUDIO_INT IT8152_PD_IRQ(0) + +struct pci_dev; +struct pci_sys_data; + +extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc); +extern void it8152_init_irq(void); +extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); +extern int it8152_pci_setup(int nr, struct pci_sys_data *sys); +extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys); + +#endif /* __ASM_HARDWARE_IT8152_H */ diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h index b5b030e..46dcc4d 100644 --- a/include/asm-arm/kexec.h +++ b/include/asm-arm/kexec.h @@ -14,6 +14,8 @@ #define KEXEC_ARCH KEXEC_ARCH_ARM +#define KEXEC_BOOT_PARAMS_SIZE 1536 + #ifndef __ASSEMBLY__ struct kimage; diff --git a/include/asm-arm/pci.h b/include/asm-arm/pci.h index ed3f898..75feb15 100644 --- a/include/asm-arm/pci.h +++ b/include/asm-arm/pci.h @@ -8,10 +8,17 @@ #define pcibios_scan_all_fns(a, b) 0 +#ifdef CONFIG_PCI_HOST_ITE8152 +/* ITE bridge requires setting latency timer to avoid early bus access + termination by PIC bus mater devices +*/ +extern void pcibios_set_master(struct pci_dev *dev); +#else static inline void pcibios_set_master(struct pci_dev *dev) { /* No special bus mastering setup handling */ } +#endif static inline void pcibios_penalize_isa_irq(int irq, int active) { diff --git a/include/asm-arm/unistd.h b/include/asm-arm/unistd.h index d327b25..88e868b 100644 --- a/include/asm-arm/unistd.h +++ b/include/asm-arm/unistd.h @@ -378,6 +378,7 @@ #define __NR_signalfd (__NR_SYSCALL_BASE+349) #define __NR_timerfd (__NR_SYSCALL_BASE+350) #define __NR_eventfd (__NR_SYSCALL_BASE+351) +#define __NR_fallocate (__NR_SYSCALL_BASE+352) /* * The following SWIs are ARM private. diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 2aaf1c1..2c49561 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -1636,6 +1636,7 @@ #define PCI_DEVICE_ID_ITE_8211 0x8211 #define PCI_DEVICE_ID_ITE_8212 0x8212 #define PCI_DEVICE_ID_ITE_8213 0x8213 +#define PCI_DEVICE_ID_ITE_8152 0x8152 #define PCI_DEVICE_ID_ITE_8872 0x8872 #define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 |
