diff options
Diffstat (limited to 'include')
44 files changed, 950 insertions, 121 deletions
diff --git a/include/acpi/acdispat.h b/include/acpi/acdispat.h index cb8d286..7f690bb 100644 --- a/include/acpi/acdispat.h +++ b/include/acpi/acdispat.h @@ -290,12 +290,9 @@ acpi_ds_obj_stack_push(void *object, struct acpi_walk_state *walk_state); acpi_status acpi_ds_obj_stack_pop(u32 pop_count, struct acpi_walk_state *walk_state); -struct acpi_walk_state *acpi_ds_create_walk_state(acpi_owner_id owner_id, - union acpi_parse_object - *origin, - union acpi_operand_object - *mth_desc, - struct acpi_thread_state +struct acpi_walk_state *acpi_ds_create_walk_state(acpi_owner_id owner_id, union acpi_parse_object + *origin, union acpi_operand_object + *mth_desc, struct acpi_thread_state *thread); acpi_status diff --git a/include/acpi/acglobal.h b/include/acpi/acglobal.h index 24c3f05..347a911 100644 --- a/include/acpi/acglobal.h +++ b/include/acpi/acglobal.h @@ -319,7 +319,7 @@ ACPI_EXTERN struct acpi_fixed_event_handler acpi_gbl_fixed_event_handlers[ACPI_NUM_FIXED_EVENTS]; ACPI_EXTERN struct acpi_gpe_xrupt_info *acpi_gbl_gpe_xrupt_list_head; ACPI_EXTERN struct acpi_gpe_block_info - *acpi_gbl_gpe_fadt_blocks[ACPI_MAX_GPE_BLOCKS]; +*acpi_gbl_gpe_fadt_blocks[ACPI_MAX_GPE_BLOCKS]; /***************************************************************************** * diff --git a/include/acpi/acinterp.h b/include/acpi/acinterp.h index 4409830..ce7c9d6 100644 --- a/include/acpi/acinterp.h +++ b/include/acpi/acinterp.h @@ -253,8 +253,7 @@ acpi_ex_release_mutex(union acpi_operand_object *obj_desc, void acpi_ex_release_all_mutexes(struct acpi_thread_state *thread); -void acpi_ex_unlink_mutex(union acpi_operand_object *obj_desc, - struct acpi_thread_state *thread); +void acpi_ex_unlink_mutex(union acpi_operand_object *obj_desc); /* * exprep - ACPI AML execution - prep utilities @@ -446,10 +445,14 @@ acpi_ex_copy_integer_to_buffer_field(union acpi_operand_object *source_desc, /* * exutils - interpreter/scanner utilities */ -acpi_status acpi_ex_enter_interpreter(void); +void acpi_ex_enter_interpreter(void); void acpi_ex_exit_interpreter(void); +void acpi_ex_reacquire_interpreter(void); + +void acpi_ex_relinquish_interpreter(void); + void acpi_ex_truncate_for32bit_table(union acpi_operand_object *obj_desc); u8 acpi_ex_acquire_global_lock(u32 rule); diff --git a/include/acpi/aclocal.h b/include/acpi/aclocal.h index 6f83ddb..202cd42 100644 --- a/include/acpi/aclocal.h +++ b/include/acpi/aclocal.h @@ -630,7 +630,7 @@ ACPI_PARSE_COMMON}; * and bytelists. */ struct acpi_parse_obj_named { - ACPI_PARSE_COMMON u8 * path; + ACPI_PARSE_COMMON u8 *path; u8 *data; /* AML body or bytelist data */ u32 length; /* AML length */ u32 name; /* 4-byte name or zero if no name */ diff --git a/include/acpi/acnamesp.h b/include/acpi/acnamesp.h index 535b7e1..5ef38a6 100644 --- a/include/acpi/acnamesp.h +++ b/include/acpi/acnamesp.h @@ -100,10 +100,8 @@ acpi_ns_walk_namespace(acpi_object_type type, acpi_walk_callback user_function, void *context, void **return_value); -struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, - struct acpi_namespace_node - *parent, - struct acpi_namespace_node +struct acpi_namespace_node *acpi_ns_get_next_node(acpi_object_type type, struct acpi_namespace_node + *parent, struct acpi_namespace_node *child); /* diff --git a/include/acpi/acobject.h b/include/acpi/acobject.h index 5206d61..7e1211a 100644 --- a/include/acpi/acobject.h +++ b/include/acpi/acobject.h @@ -155,7 +155,7 @@ struct acpi_object_event { struct acpi_object_mutex { ACPI_OBJECT_COMMON_HEADER u8 sync_level; /* 0-15, specified in Mutex() call */ u16 acquisition_depth; /* Allow multiple Acquires, same thread */ - acpi_thread_id owner_thread_id; /* Current owner of the mutex */ + struct acpi_thread_state *owner_thread; /* Current owner of the mutex */ acpi_mutex os_mutex; /* Actual OS synchronization object */ union acpi_operand_object *prev; /* Link for list of acquired mutexes */ union acpi_operand_object *next; /* Link for list of acquired mutexes */ @@ -216,7 +216,7 @@ struct acpi_object_processor { /* The next two fields take advantage of the 3-byte space before NOTIFY_INFO */ u8 proc_id; u8 length; - ACPI_COMMON_NOTIFY_INFO acpi_io_address address; + ACPI_COMMON_NOTIFY_INFO acpi_io_address address; }; struct acpi_object_thermal_zone { diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 9cfd5b1..c6fa5e0 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -91,7 +91,8 @@ typedef int (*acpi_op_remove) (struct acpi_device * device, int type); typedef int (*acpi_op_lock) (struct acpi_device * device, int type); typedef int (*acpi_op_start) (struct acpi_device * device); typedef int (*acpi_op_stop) (struct acpi_device * device, int type); -typedef int (*acpi_op_suspend) (struct acpi_device * device, pm_message_t state); +typedef int (*acpi_op_suspend) (struct acpi_device * device, + pm_message_t state); typedef int (*acpi_op_resume) (struct acpi_device * device); typedef int (*acpi_op_scan) (struct acpi_device * device); typedef int (*acpi_op_bind) (struct acpi_device * device); @@ -296,7 +297,7 @@ struct acpi_device { void *driver_data; struct device dev; struct acpi_bus_ops bus_ops; /* workaround for different code path for hotplug */ - enum acpi_bus_removal_type removal_type; /* indicate for different removal type */ + enum acpi_bus_removal_type removal_type; /* indicate for different removal type */ }; #define acpi_driver_data(d) ((d)->driver_data) @@ -338,7 +339,7 @@ int acpi_bus_add(struct acpi_device **child, struct acpi_device *parent, acpi_handle handle, int type); int acpi_bus_trim(struct acpi_device *start, int rmdevice); int acpi_bus_start(struct acpi_device *device); -acpi_status acpi_bus_get_ejd(acpi_handle handle, acpi_handle *ejd); +acpi_status acpi_bus_get_ejd(acpi_handle handle, acpi_handle * ejd); int acpi_match_ids(struct acpi_device *device, char *ids); int acpi_create_dir(struct acpi_device *); void acpi_remove_dir(struct acpi_device *); @@ -363,6 +364,6 @@ acpi_handle acpi_get_child(acpi_handle, acpi_integer); acpi_handle acpi_get_pci_rootbridge_handle(unsigned int, unsigned int); #define DEVICE_ACPI_HANDLE(dev) ((acpi_handle)((dev)->archdata.acpi_handle)) -#endif /* CONFIG_ACPI */ +#endif /* CONFIG_ACPI */ #endif /*__ACPI_BUS_H__*/ diff --git a/include/acpi/acpi_drivers.h b/include/acpi/acpi_drivers.h index f6275b0..5535159 100644 --- a/include/acpi/acpi_drivers.h +++ b/include/acpi/acpi_drivers.h @@ -113,7 +113,8 @@ extern int is_dock_device(acpi_handle handle); extern int register_dock_notifier(struct notifier_block *nb); extern void unregister_dock_notifier(struct notifier_block *nb); extern int register_hotplug_dock_device(acpi_handle handle, - acpi_notify_handler handler, void *context); + acpi_notify_handler handler, + void *context); extern void unregister_hotplug_dock_device(acpi_handle handle); #else static inline int is_dock_device(acpi_handle handle) @@ -128,7 +129,8 @@ static inline void unregister_dock_notifier(struct notifier_block *nb) { } static inline int register_hotplug_dock_device(acpi_handle handle, - acpi_notify_handler handler, void *context) + acpi_notify_handler handler, + void *context) { return -ENODEV; } diff --git a/include/acpi/acpi_numa.h b/include/acpi/acpi_numa.h index 1049f2a..f9d2bde 100644 --- a/include/acpi/acpi_numa.h +++ b/include/acpi/acpi_numa.h @@ -8,7 +8,7 @@ #if MAX_NUMNODES > 256 #define MAX_PXM_DOMAINS MAX_NUMNODES #else -#define MAX_PXM_DOMAINS (256) /* Old pxm spec is defined 8 bit */ +#define MAX_PXM_DOMAINS (256) /* Old pxm spec is defined 8 bit */ #endif extern int __cpuinitdata pxm_to_node_map[MAX_PXM_DOMAINS]; diff --git a/include/acpi/acpiosxf.h b/include/acpi/acpiosxf.h index 2785058..5e07db0 100644 --- a/include/acpi/acpiosxf.h +++ b/include/acpi/acpiosxf.h @@ -143,7 +143,8 @@ void acpi_os_release_mutex(acpi_mutex handle); */ void *acpi_os_allocate(acpi_size size); -void __iomem *acpi_os_map_memory(acpi_physical_address where, acpi_native_uint length); +void __iomem *acpi_os_map_memory(acpi_physical_address where, + acpi_native_uint length); void acpi_os_unmap_memory(void __iomem * logical_address, acpi_size size); diff --git a/include/acpi/actypes.h b/include/acpi/actypes.h index 56bf492..fe8abc2 100644 --- a/include/acpi/actypes.h +++ b/include/acpi/actypes.h @@ -344,7 +344,7 @@ typedef u32 acpi_integer; /* 64-bit integers */ -typedef unsigned long long acpi_integer; +typedef unsigned long long acpi_integer; #define ACPI_INTEGER_MAX ACPI_UINT64_MAX #define ACPI_INTEGER_BIT_SIZE 64 #define ACPI_MAX_DECIMAL_DIGITS 20 /* 2^64 = 18,446,744,073,709,551,616 */ diff --git a/include/acpi/acutils.h b/include/acpi/acutils.h index 883ffe9..15a8388 100644 --- a/include/acpi/acutils.h +++ b/include/acpi/acutils.h @@ -498,7 +498,8 @@ acpi_ut_display_init_pathname(u8 type, acpi_status acpi_ut_walk_aml_resources(u8 * aml, acpi_size aml_length, - acpi_walk_aml_callback user_function, void **context); + acpi_walk_aml_callback user_function, + void **context); acpi_status acpi_ut_validate_resource(void *aml, u8 * return_index); diff --git a/include/acpi/platform/aclinux.h b/include/acpi/platform/aclinux.h index 5f532d2..a568717 100644 --- a/include/acpi/platform/aclinux.h +++ b/include/acpi/platform/aclinux.h @@ -103,7 +103,10 @@ #define acpi_thread_id struct task_struct * -static inline acpi_thread_id acpi_os_get_thread_id(void) { return current; } +static inline acpi_thread_id acpi_os_get_thread_id(void) +{ + return current; +} /* * The irqs_disabled() check is for resume from RAM. @@ -112,15 +115,19 @@ static inline acpi_thread_id acpi_os_get_thread_id(void) { return current; } * to quiet __might_sleep() in kmalloc() and resume does not. */ #include <acpi/actypes.h> -static inline void *acpi_os_allocate(acpi_size size) { - return kmalloc(size, irqs_disabled() ? GFP_ATOMIC : GFP_KERNEL); +static inline void *acpi_os_allocate(acpi_size size) +{ + return kmalloc(size, irqs_disabled()? GFP_ATOMIC : GFP_KERNEL); } -static inline void *acpi_os_allocate_zeroed(acpi_size size) { - return kzalloc(size, irqs_disabled() ? GFP_ATOMIC : GFP_KERNEL); +static inline void *acpi_os_allocate_zeroed(acpi_size size) +{ + return kzalloc(size, irqs_disabled()? GFP_ATOMIC : GFP_KERNEL); } -static inline void *acpi_os_acquire_object(acpi_cache_t * cache) { - return kmem_cache_zalloc(cache, irqs_disabled() ? GFP_ATOMIC : GFP_KERNEL); +static inline void *acpi_os_acquire_object(acpi_cache_t * cache) +{ + return kmem_cache_zalloc(cache, + irqs_disabled()? GFP_ATOMIC : GFP_KERNEL); } #define ACPI_ALLOCATE(a) acpi_os_allocate(a) diff --git a/include/acpi/processor.h b/include/acpi/processor.h index 916c010..b4b0ffd 100644 --- a/include/acpi/processor.h +++ b/include/acpi/processor.h @@ -18,7 +18,7 @@ #define ACPI_PDC_REVISION_ID 0x1 -#define ACPI_PSD_REV0_REVISION 0 /* Support for _PSD as in ACPI 3.0 */ +#define ACPI_PSD_REV0_REVISION 0 /* Support for _PSD as in ACPI 3.0 */ #define ACPI_PSD_REV0_ENTRIES 5 /* @@ -189,8 +189,9 @@ struct acpi_processor_errata { } piix4; }; -extern int acpi_processor_preregister_performance( - struct acpi_processor_performance **performance); +extern int acpi_processor_preregister_performance(struct + acpi_processor_performance + **performance); extern int acpi_processor_register_performance(struct acpi_processor_performance *performance, unsigned int cpu); @@ -213,7 +214,8 @@ void arch_acpi_processor_init_pdc(struct acpi_processor *pr); void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags, unsigned int cpu); int acpi_processor_ffh_cstate_probe(unsigned int cpu, - struct acpi_processor_cx *cx, struct acpi_power_register *reg); + struct acpi_processor_cx *cx, + struct acpi_power_register *reg); void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cstate); #else static inline void acpi_processor_power_init_bm_check(struct @@ -224,12 +226,14 @@ static inline void acpi_processor_power_init_bm_check(struct return; } static inline int acpi_processor_ffh_cstate_probe(unsigned int cpu, - struct acpi_processor_cx *cx, struct acpi_power_register *reg) + struct acpi_processor_cx *cx, + struct acpi_power_register + *reg) { return -1; } -static inline void acpi_processor_ffh_cstate_enter( - struct acpi_processor_cx *cstate) +static inline void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx + *cstate) { return; } diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h index 28133e0..1c14382 100644 --- a/include/asm-arm/arch-at91/hardware.h +++ b/include/asm-arm/arch-at91/hardware.h @@ -69,22 +69,5 @@ /* Clocks */ #define AT91_SLOW_CLOCK 32768 /* slow clock */ -#ifndef __ASSEMBLY__ -#include <asm/io.h> - -static inline unsigned int at91_sys_read(unsigned int reg_offset) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - return __raw_readl(addr + reg_offset); -} - -static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) -{ - void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; - - __raw_writel(value, addr + reg_offset); -} -#endif #endif diff --git a/include/asm-arm/arch-at91/io.h b/include/asm-arm/arch-at91/io.h index 401f327..80073fd 100644 --- a/include/asm-arm/arch-at91/io.h +++ b/include/asm-arm/arch-at91/io.h @@ -29,4 +29,22 @@ #define __mem_pci(a) (a) +#ifndef __ASSEMBLY__ + +static inline unsigned int at91_sys_read(unsigned int reg_offset) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + return __raw_readl(addr + reg_offset); +} + +static inline void at91_sys_write(unsigned int reg_offset, unsigned long value) +{ + void __iomem *addr = (void __iomem *)AT91_VA_BASE_SYS; + + __raw_writel(value, addr + reg_offset); +} + +#endif + #endif diff --git a/include/asm-arm/arch-at91/irqs.h b/include/asm-arm/arch-at91/irqs.h index 1ffa3bb..1127a3b 100644 --- a/include/asm-arm/arch-at91/irqs.h +++ b/include/asm-arm/arch-at91/irqs.h @@ -21,6 +21,7 @@ #ifndef __ASM_ARCH_IRQS_H #define __ASM_ARCH_IRQS_H +#include <asm/io.h> #include <asm/arch/at91_aic.h> #define NR_AIC_IRQS 32 diff --git a/include/asm-arm/arch-at91/uncompress.h b/include/asm-arm/arch-at91/uncompress.h index a193d28..30ac587 100644 --- a/include/asm-arm/arch-at91/uncompress.h +++ b/include/asm-arm/arch-at91/uncompress.h @@ -21,7 +21,7 @@ #ifndef __ASM_ARCH_UNCOMPRESS_H #define __ASM_ARCH_UNCOMPRESS_H -#include <asm/hardware.h> +#include <asm/io.h> #include <asm/arch/at91_dbgu.h> /* diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h index 7dfff4a..a6e0f9e 100644 --- a/include/asm-arm/arch-iop13xx/io.h +++ b/include/asm-arm/arch-iop13xx/io.h @@ -27,7 +27,7 @@ extern void __iomem * __iop13xx_io(unsigned long io_addr); extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop13xx_iounmap(void __iomem *addr); extern u32 iop13xx_atue_mem_base; diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h index 994f16a..958af75 100644 --- a/include/asm-arm/arch-iop32x/io.h +++ b/include/asm-arm/arch-iop32x/io.h @@ -14,7 +14,7 @@ #include <asm/hardware.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h index 993f758..fec9c53 100644 --- a/include/asm-arm/arch-iop33x/io.h +++ b/include/asm-arm/arch-iop33x/io.h @@ -14,7 +14,7 @@ #include <asm/hardware.h> extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size, - unsigned long flags); + unsigned int mtype); extern void __iop3xx_iounmap(void __iomem *addr); #define IO_SPACE_LIMIT 0xffffffff diff --git a/include/asm-i386/paravirt.h b/include/asm-i386/paravirt.h index bc5c12c..d7a0512 100644 --- a/include/asm-i386/paravirt.h +++ b/include/asm-i386/paravirt.h @@ -222,11 +222,6 @@ struct paravirt_ops void (*iret)(void); }; -/* Mark a paravirt probe function. */ -#define paravirt_probe(fn) \ - static asmlinkage void (*__paravirtprobe_##fn)(void) __attribute_used__ \ - __attribute__((__section__(".paravirtprobe"))) = fn - extern struct paravirt_ops paravirt_ops; #define PARAVIRT_PATCH(x) \ diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h index e2ca55b..b8dca30 100644 --- a/include/asm-powerpc/mmu-hash64.h +++ b/include/asm-powerpc/mmu-hash64.h @@ -73,8 +73,9 @@ extern char initial_stab[]; #define HPTES_PER_GROUP 8 +#define HPTE_V_SSIZE_SHIFT 62 #define HPTE_V_AVPN_SHIFT 7 -#define HPTE_V_AVPN ASM_CONST(0xffffffffffffff80) +#define HPTE_V_AVPN ASM_CONST(0x3fffffffffffff80) #define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT) #define HPTE_V_COMPARE(x,y) (!(((x) ^ (y)) & HPTE_V_AVPN)) #define HPTE_V_BOLTED ASM_CONST(0x0000000000000010) @@ -151,6 +152,15 @@ struct mmu_psize_def #define MMU_PAGE_16G 5 /* 16G */ #define MMU_PAGE_COUNT 6 +/* + * Segment sizes. + * These are the values used by hardware in the B field of + * SLB entries and the first dword of MMU hashtable entries. + * The B field is 2 bits; the values 2 and 3 are unused and reserved. + */ +#define MMU_SEGSIZE_256M 0 +#define MMU_SEGSIZE_1T 1 + #ifndef __ASSEMBLY__ /* diff --git a/include/asm-powerpc/mmzone.h b/include/asm-powerpc/mmzone.h index d484ca9..19f299b 100644 --- a/include/asm-powerpc/mmzone.h +++ b/include/asm-powerpc/mmzone.h @@ -43,9 +43,5 @@ extern unsigned long max_pfn; #endif /* CONFIG_NEED_MULTIPLE_NODES */ -#ifdef CONFIG_HAVE_ARCH_EARLY_PFN_TO_NID -extern int __init early_pfn_to_nid(unsigned long pfn); -#endif - #endif /* __KERNEL__ */ #endif /* _ASM_MMZONE_H_ */ diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h index 6dcd7a8..8e20051 100644 --- a/include/asm-powerpc/ppc-pci.h +++ b/include/asm-powerpc/ppc-pci.h @@ -62,11 +62,14 @@ struct pci_dev *pci_get_device_by_addr(unsigned long addr); /** * eeh_slot_error_detail -- record and EEH error condition to the log - * @severity: 1 if temporary, 2 if permanent failure. + * @pdn: pci device node + * @severity: EEH_LOG_TEMP_FAILURE or EEH_LOG_PERM_FAILURE * * Obtains the EEH error details from the RTAS subsystem, * and then logs these details with the RTAS error log system. */ +#define EEH_LOG_TEMP_FAILURE 1 +#define EEH_LOG_PERM_FAILURE 2 void eeh_slot_error_detail (struct pci_dn *pdn, int severity); /** @@ -82,6 +85,7 @@ int rtas_pci_enable(struct pci_dn *pdn, int function); /** * rtas_set_slot_reset -- unfreeze a frozen slot + * @pdn: pci device node * * Clear the EEH-frozen condition on a slot. This routine * does this by asserting the PCI #RST line for 1/8th of @@ -95,6 +99,7 @@ int eeh_wait_for_slot_status(struct pci_dn *pdn, int max_wait_msecs); /** * eeh_restore_bars - Restore device configuration info. + * @pdn: pci device node * * A reset of a PCI device will clear out its config space. * This routines will restore the config space for this @@ -105,6 +110,7 @@ void eeh_restore_bars(struct pci_dn *); /** * rtas_configure_bridge -- firmware initialization of pci bridge + * @pdn: pci device node * * Ask the firmware to configure all PCI bridges devices * located behind the indicated node. Required after a @@ -118,16 +124,22 @@ int rtas_write_config(struct pci_dn *, int where, int size, u32 val); int rtas_read_config(struct pci_dn *, int where, int size, u32 *val); /** + * eeh_mark_slot -- set mode flags for pertition endpoint + * @pdn: pci device node + * * mark and clear slots: find "partition endpoint" PE and set or * clear the flags for each subnode of the PE. */ void eeh_mark_slot (struct device_node *dn, int mode_flag); void eeh_clear_slot (struct device_node *dn, int mode_flag); -/* Find the associated "Partiationable Endpoint" PE */ +/** + * find_device_pe -- Find the associated "Partiationable Endpoint" PE + * @pdn: pci device node + */ struct device_node * find_device_pe(struct device_node *dn); -#endif +#endif /* CONFIG_EEH */ #else /* CONFIG_PCI */ static inline void find_and_init_phbs(void) { } diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h index 13c372d..1e04651 100644 --- a/include/asm-powerpc/ps3.h +++ b/include/asm-powerpc/ps3.h @@ -377,8 +377,13 @@ int ps3_vuart_port_device_register(struct ps3_vuart_port_device *dev); /* system manager */ +#ifdef CONFIG_PS3_SYS_MANAGER void ps3_sys_manager_restart(void); void ps3_sys_manager_power_off(void); +#else +static inline void ps3_sys_manager_restart(void) {} +static inline void ps3_sys_manager_power_off(void) {} +#endif struct ps3_prealloc { const char *name; diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h index a62168ec..9d304b1 100644 --- a/include/asm-powerpc/qe.h +++ b/include/asm-powerpc/qe.h @@ -38,11 +38,11 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); void qe_setbrg(u32 brg, u32 rate); int qe_get_snum(void); void qe_put_snum(u8 snum); -u32 qe_muram_alloc(u32 size, u32 align); -int qe_muram_free(u32 offset); -u32 qe_muram_alloc_fixed(u32 offset, u32 size); +unsigned long qe_muram_alloc(int size, int align); +int qe_muram_free(unsigned long offset); +unsigned long qe_muram_alloc_fixed(unsigned long offset, int size); void qe_muram_dump(void); -void *qe_muram_addr(u32 offset); +void *qe_muram_addr(unsigned long offset); /* Buffer descriptors */ struct qe_bd { @@ -448,10 +448,5 @@ struct ucc_slow_pram { #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 -static inline long IS_MURAM_ERR(const u32 offset) -{ - return offset > (u32) - 1000L; -} - #endif /* __KERNEL__ */ #endif /* _ASM_POWERPC_QE_H */ diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h new file mode 100644 index 0000000..064405c --- /dev/null +++ b/include/asm-powerpc/reg_booke.h @@ -0,0 +1,469 @@ +/* + * Contains register definitions common to the Book E PowerPC + * specification. Notice that while the IBM-40x series of CPUs + * are not true Book E PowerPCs, they borrowed a number of features + * before Book E was finalized, and are included here as well. Unfortunatly, + * they sometimes used different locations than true Book E CPUs did. + */ +#ifdef __KERNEL__ +#ifndef __ASM_POWERPC_REG_BOOKE_H__ +#define __ASM_POWERPC_REG_BOOKE_H__ + +#ifndef __ASSEMBLY__ +/* Performance Monitor Registers */ +#define mfpmr(rn) ({unsigned int rval; \ + asm volatile("mfpmr %0," __stringify(rn) \ + : "=r" (rval)); rval;}) +#define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v)) +#endif /* __ASSEMBLY__ */ + +/* Freescale Book E Performance Monitor APU Registers */ +#define PMRN_PMC0 0x010 /* Performance Monitor Counter 0 */ +#define PMRN_PMC1 0x011 /* Performance Monitor Counter 1 */ +#define PMRN_PMC2 0x012 /* Performance Monitor Counter 1 */ +#define PMRN_PMC3 0x013 /* Performance Monitor Counter 1 */ +#define PMRN_PMLCA0 0x090 /* PM Local Control A0 */ +#define PMRN_PMLCA1 0x091 /* PM Local Control A1 */ +#define PMRN_PMLCA2 0x092 /* PM Local Control A2 */ +#define PMRN_PMLCA3 0x093 /* PM Local Control A3 */ + +#define PMLCA_FC 0x80000000 /* Freeze Counter */ +#define PMLCA_FCS 0x40000000 /* Freeze in Supervisor */ +#define PMLCA_FCU 0x20000000 /* Freeze in User */ +#define PMLCA_FCM1 0x10000000 /* Freeze when PMM==1 */ +#define PMLCA_FCM0 0x08000000 /* Freeze when PMM==0 */ +#define PMLCA_CE 0x04000000 /* Condition Enable */ + +#define PMLCA_EVENT_MASK 0x007f0000 /* Event field */ +#define PMLCA_EVENT_SHIFT 16 + +#define PMRN_PMLCB0 0x110 /* PM Local Control B0 */ +#define PMRN_PMLCB1 0x111 /* PM Local Control B1 */ +#define PMRN_PMLCB2 0x112 /* PM Local Control B2 */ +#define PMRN_PMLCB3 0x113 /* PM Local Control B3 */ + +#define PMLCB_THRESHMUL_MASK 0x0700 /* Threshhold Multiple Field */ +#define PMLCB_THRESHMUL_SHIFT 8 + +#define PMLCB_THRESHOLD_MASK 0x003f /* Threshold Field */ +#define PMLCB_THRESHOLD_SHIFT 0 + +#define PMRN_PMGC0 0x190 /* PM Global Control 0 */ + +#define PMGC0_FAC 0x80000000 /* Freeze all Counters */ +#define PMGC0_PMIE 0x40000000 /* Interrupt Enable */ +#define PMGC0_FCECE 0x20000000 /* Freeze countes on + Enabled Condition or + Event */ + +#define PMRN_UPMC0 0x000 /* User Performance Monitor Counter 0 */ +#define PMRN_UPMC1 0x001 /* User Performance Monitor Counter 1 */ +#define PMRN_UPMC2 0x002 /* User Performance Monitor Counter 1 */ +#define PMRN_UPMC3 0x003 /* User Performance Monitor Counter 1 */ +#define PMRN_UPMLCA0 0x080 /* User PM Local Control A0 */ +#define PMRN_UPMLCA1 0x081 /* User PM Local Control A1 */ +#define PMRN_UPMLCA2 0x082 /* User PM Local Control A2 */ +#define PMRN_UPMLCA3 0x083 /* User PM Local Control A3 */ +#define PMRN_UPMLCB0 0x100 /* User PM Local Control B0 */ +#define PMRN_UPMLCB1 0x101 /* User PM Local Control B1 */ +#define PMRN_UPMLCB2 0x102 /* User PM Local Control B2 */ +#define PMRN_UPMLCB3 0x103 /* User PM Local Control B3 */ +#define PMRN_UPMGC0 0x180 /* User PM Global Control 0 */ + + +/* Machine State Register (MSR) Fields */ +#define MSR_UCLE (1<<26) /* User-mode cache lock enable */ +#define MSR_SPE (1<<25) /* Enable SPE */ +#define MSR_DWE (1<<10) /* Debug Wait Enable */ +#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */ +#define MSR_IS MSR_IR /* Instruction Space */ +#define MSR_DS MSR_DR /* Data Space */ +#define MSR_PMM (1<<2) /* Performance monitor mark bit */ + +/* Default MSR for kernel mode. */ +#if defined (CONFIG_40x) +#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE) +#elif defined(CONFIG_BOOKE) +#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE) +#endif + +/* Special Purpose Registers (SPRNs)*/ +#define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */ +#define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */ +#define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */ +#define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */ +#define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */ +#define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */ +#define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */ +#define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */ +#define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */ +#define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */ +#define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */ +#define SPRN_DBCR2 0x136 /* Debug Control Register 2 */ +#define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */ +#define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */ +#define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */ +#define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */ +#define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */ +#define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */ +#define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */ +#define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */ +#define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */ +#define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */ +#define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */ +#define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */ +#define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */ +#define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */ +#define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */ +#define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */ +#define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */ +#define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */ +#define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */ +#define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */ +#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ +#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ +#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ +#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ +#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ +#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ +#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ +#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ +#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ +#define SPRN_MCSR 0x23C /* Machine Check Status Register */ +#define SPRN_MCAR 0x23D /* Machine Check Address Register */ +#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ +#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ +#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ +#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ +#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ +#define SPRN_MAS3 0x273 /* MMU Assist Register 3 */ +#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ +#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ +#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ +#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */ +#define SPRN_PID1 0x279 /* Process ID Register 1 */ +#define SPRN_PID2 0x27A /* Process ID Register 2 */ +#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ +#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ +#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ +#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ +#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ +#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ +#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ +#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ +#define SPRN_SLER 0x3BB /* Little-endian real mode */ +#define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */ +#define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */ +#define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ +#define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */ +#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ +#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ +#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ +#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ +#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ +#define SPRN_SVR 0x3FF /* System Version Register */ + +/* + * SPRs which have conflicting definitions on true Book E versus classic, + * or IBM 40x. + */ +#ifdef CONFIG_BOOKE +#define SPRN_PID 0x030 /* Process ID */ +#define SPRN_PID0 SPRN_PID/* Process ID Register 0 */ +#define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */ +#define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */ +#define SPRN_DEAR 0x03D /* Data Error Address Register */ +#define SPRN_ESR 0x03E /* Exception Syndrome Register */ +#define SPRN_PIR 0x11E /* Processor Identification Register */ +#define SPRN_DBSR 0x130 /* Debug Status Register */ +#define SPRN_DBCR0 0x134 /* Debug Control Register 0 */ +#define SPRN_DBCR1 0x135 /* Debug Control Register 1 */ +#define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */ +#define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */ +#define SPRN_DAC1 0x13C /* Data Address Compare 1 */ +#define SPRN_DAC2 0x13D /* Data Address Compare 2 */ +#define SPRN_TSR 0x150 /* Timer Status Register */ +#define SPRN_TCR 0x154 /* Timer Control Register */ +#endif /* Book E */ +#ifdef CONFIG_40x +#define SPRN_PID 0x3B1 /* Process ID */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_ESR 0x3D4 /* Exception Syndrome Register */ +#define SPRN_DEAR 0x3D5 /* Data Error Address Register */ +#define SPRN_TSR 0x3D8 /* Timer Status Register */ +#define SPRN_TCR 0x3DA /* Timer Control Register */ +#define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ +#define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ +#define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */ +#define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */ +#define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */ +#define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */ +#endif + +/* Bit definitions for CCR1. */ +#define CCR1_DPC 0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */ +#define CCR1_TCS 0x00000080 /* Timer Clock Select */ + +/* Bit definitions for the MCSR. */ +#ifdef CONFIG_440A +#define MCSR_MCS 0x80000000 /* Machine Check Summary */ +#define MCSR_IB 0x40000000 /* Instruction PLB Error */ +#define MCSR_DRB 0x20000000 /* Data Read PLB Error */ +#define MCSR_DWB 0x10000000 /* Data Write PLB Error */ +#define MCSR_TLBP 0x08000000 /* TLB Parity Error */ +#define MCSR_ICP 0x04000000 /* I-Cache Parity Error */ +#define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */ +#define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */ +#define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */ +#endif +#ifdef CONFIG_E500 +#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ +#define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */ +#define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */ +#define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */ +#define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */ +#define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */ +#define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */ +#define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */ +#define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */ +#define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */ +#define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */ +#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ +#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ +#endif +#ifdef CONFIG_E200 +#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ +#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ +#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ +#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn + fetch for an exception handler */ +#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ +#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ +#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered + store or cache line push */ +#endif + +/* Bit definitions for the DBSR. */ +/* + * DBSR bits which have conflicting definitions on true Book E versus IBM 40x. + */ +#ifdef CONFIG_BOOKE +#define DBSR_IC 0x08000000 /* Instruction Completion */ +#define DBSR_BT 0x04000000 /* Branch Taken */ +#define DBSR_TIE 0x01000000 /* Trap Instruction Event */ +#define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */ +#define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */ +#define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */ +#define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */ +#define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */ +#define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */ +#define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */ +#define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */ +#endif +#ifdef CONFIG_40x +#define DBSR_IC 0x80000000 /* Instruction Completion */ +#define DBSR_BT 0x40000000 /* Branch taken */ +#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ +#define DBSR_IAC1 0x04000000 /* Instruction Address Compare 1 Event */ +#define DBSR_IAC2 0x02000000 /* Instruction Address Compare 2 Event */ +#define DBSR_IAC3 0x00080000 /* Instruction Address Compare 3 Event */ +#define DBSR_IAC4 0x00040000 /* Instruction Address Compare 4 Event */ +#define DBSR_DAC1R 0x01000000 /* Data Address Compare 1 Read Event */ +#define DBSR_DAC1W 0x00800000 /* Data Address Compare 1 Write Event */ +#define DBSR_DAC2R 0x00400000 /* Data Address Compare 2 Read Event */ +#define DBSR_DAC2W 0x00200000 /* Data Address Compare 2 Write Event */ +#endif + +/* Bit definitions related to the ESR. */ +#define ESR_MCI 0x80000000 /* Machine Check - Instruction */ +#define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */ +#define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */ +#define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */ +#define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */ +#define ESR_PIL 0x08000000 /* Program Exception - Illegal */ +#define ESR_PPR 0x04000000 /* Program Exception - Priveleged */ +#define ESR_PTR 0x02000000 /* Program Exception - Trap */ +#define ESR_FP 0x01000000 /* Floating Point Operation */ +#define ESR_DST 0x00800000 /* Storage Exception - Data miss */ +#define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */ +#define ESR_ST 0x00800000 /* Store Operation */ +#define ESR_DLK 0x00200000 /* Data Cache Locking */ +#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ +#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ +#define ESR_BO 0x00020000 /* Byte Ordering */ + +/* Bit definitions related to the DBCR0. */ +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ +#define DBCR0_IC 0x08000000 /* Instruction Completion */ +#define DBCR0_BT 0x04000000 /* Branch Taken */ +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ +#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ +#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ +#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ +#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ +#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ +#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ +#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ + +/* Bit definitions related to the TCR. */ +#define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define TCR_WP_MASK TCR_WP(3) +#define WP_2_17 0 /* 2^17 clocks */ +#define WP_2_21 1 /* 2^21 clocks */ +#define WP_2_25 2 /* 2^25 clocks */ +#define WP_2_29 3 /* 2^29 clocks */ +#define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define TCR_WRC_MASK TCR_WRC(3) +#define WRC_NONE 0 /* No reset will occur */ +#define WRC_CORE 1 /* Core reset will occur */ +#define WRC_CHIP 2 /* Chip reset will occur */ +#define WRC_SYSTEM 3 /* System reset will occur */ +#define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ +#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ +#define TCR_DIE TCR_PIE /* DEC Interrupt Enable */ +#define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define TCR_FP_MASK TCR_FP(3) +#define FP_2_9 0 /* 2^9 clocks */ +#define FP_2_13 1 /* 2^13 clocks */ +#define FP_2_17 2 /* 2^17 clocks */ +#define FP_2_21 3 /* 2^21 clocks */ +#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ +#define TCR_ARE 0x00400000 /* Auto Reload Enable */ + +/* Bit definitions for the TSR. */ +#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ +#define TSR_WIS 0x40000000 /* WDT Interrupt Status */ +#define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */ +#define WRS_NONE 0 /* No WDT reset occurred */ +#define WRS_CORE 1 /* WDT forced core reset */ +#define WRS_CHIP 2 /* WDT forced chip reset */ +#define WRS_SYSTEM 3 /* WDT forced system reset */ +#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ +#define TSR_DIS TSR_PIS /* DEC Interrupt Status */ +#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ + +/* Bit definitions for the DCCR. */ +#define DCCR_NOCACHE 0 /* Noncacheable */ +#define DCCR_CACHE 1 /* Cacheable */ + +/* Bit definitions for DCWR. */ +#define DCWR_COPY 0 /* Copy-back */ +#define DCWR_WRITE 1 /* Write-through */ + +/* Bit definitions for ICCR. */ +#define ICCR_NOCACHE 0 /* Noncacheable */ +#define ICCR_CACHE 1 /* Cacheable */ + +/* Bit definitions for L1CSR0. */ +#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ +#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ +#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ +#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ + +/* Bit definitions for L1CSR1. */ +#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ +#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ +#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ + +/* Bit definitions for SGR. */ +#define SGR_NORMAL 0 /* Speculative fetching allowed. */ +#define SGR_GUARDED 1 /* Speculative fetching disallowed. */ + +/* Bit definitions for SPEFSCR. */ +#define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */ +#define SPEFSCR_OVH 0x40000000 /* Integer overflow high */ +#define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */ +#define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */ +#define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */ +#define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */ +#define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */ +#define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */ +#define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */ +#define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */ +#define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */ +#define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */ +#define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */ +#define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */ +#define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */ +#define SPEFSCR_OV 0x00004000 /* Integer overflow */ +#define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */ +#define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */ +#define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */ +#define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */ +#define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */ +#define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */ +#define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */ +#define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */ +#define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */ +#define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */ +#define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */ +#define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */ + +/* + * The IBM-403 is an even more odd special case, as it is much + * older than the IBM-405 series. We put these down here incase someone + * wishes to support these machines again. + */ +#ifdef CONFIG_403GCX +/* Special Purpose Registers (SPRNs)*/ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode */ +#define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */ +#define SPRN_TBHI 0x3DC /* Time Base High */ +#define SPRN_TBLO 0x3DD /* Time Base Low */ +#define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */ +#define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */ +#define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */ +#define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */ +#define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */ + + +/* Bit definitions for the DBCR. */ +#define DBCR_EDM DBCR0_EDM +#define DBCR_IDM DBCR0_IDM +#define DBCR_RST(x) (((x) & 0x3) << 28) +#define DBCR_RST_NONE 0 +#define DBCR_RST_CORE 1 +#define DBCR_RST_CHIP 2 +#define DBCR_RST_SYSTEM 3 +#define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */ +#define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */ +#define DBCR_EDE DBCR0_EDE /* Exception Debug Event */ +#define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */ +#define DBCR_FER 0x00F80000 /* First Events Remaining Mask */ +#define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */ +#define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */ +#define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */ +#define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */ +#define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */ +#define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */ +#define DAC_BYTE 0 +#define DAC_HALF 1 +#define DAC_WORD 2 +#define DAC_QUAD 3 +#define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */ +#define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */ +#define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */ +#define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */ +#define DBCR_SED 0x00000020 /* Second Exception Debug Event */ +#define DBCR_STD 0x00000010 /* Second Trap Debug Event */ +#define DBCR_SIA 0x00000008 /* Second IAC Enable */ +#define DBCR_SDA 0x00000004 /* Second DAC Enable */ +#define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ +#define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ +#endif /* 403GCX */ +#endif /* __ASM_POWERPC_REG_BOOKE_H__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/rheap.h b/include/asm-powerpc/rheap.h index 39a10d8..1723817 100644 --- a/include/asm-ppc/rheap.h +++ b/include/asm-powerpc/rheap.h @@ -18,7 +18,7 @@ typedef struct _rh_block { struct list_head list; - void *start; + unsigned long start; int size; const char *owner; } rh_block_t; @@ -37,8 +37,8 @@ typedef struct _rh_info { #define RHIF_STATIC_INFO 0x1 #define RHIF_STATIC_BLOCK 0x2 -typedef struct rh_stats_t { - void *start; +typedef struct _rh_stats { + unsigned long start; int size; const char *owner; } rh_stats_t; @@ -57,24 +57,24 @@ extern void rh_init(rh_info_t * info, unsigned int alignment, int max_blocks, rh_block_t * block); /* Attach a free region to manage */ -extern int rh_attach_region(rh_info_t * info, void *start, int size); +extern int rh_attach_region(rh_info_t * info, unsigned long start, int size); /* Detach a free region */ -extern void *rh_detach_region(rh_info_t * info, void *start, int size); +extern unsigned long rh_detach_region(rh_info_t * info, unsigned long start, int size); /* Allocate the given size from the remote heap (with alignment) */ -extern void *rh_alloc_align(rh_info_t * info, int size, int alignment, +extern unsigned long rh_alloc_align(rh_info_t * info, int size, int alignment, const char *owner); /* Allocate the given size from the remote heap */ -extern void *rh_alloc(rh_info_t * info, int size, const char *owner); +extern unsigned long rh_alloc(rh_info_t * info, int size, const char *owner); /* Allocate the given size from the given address */ -extern void *rh_alloc_fixed(rh_info_t * info, void *start, int size, +extern unsigned long rh_alloc_fixed(rh_info_t * info, unsigned long start, int size, const char *owner); /* Free the allocated area */ -extern int rh_free(rh_info_t * info, void *start); +extern int rh_free(rh_info_t * info, unsigned long start); /* Get stats for debugging purposes */ extern int rh_get_stats(rh_info_t * info, int what, int max_stats, @@ -84,6 +84,6 @@ extern int rh_get_stats(rh_info_t * info, int what, int max_stats, extern void rh_dump(rh_info_t * info); /* Set owner of taken block */ -extern int rh_set_owner(rh_info_t * info, void *start, const char *owner); +extern int rh_set_owner(rh_info_t * info, unsigned long start, const char *owner); #endif /* __ASM_PPC_RHEAP_H__ */ diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h index 0b00068..3d44446 100644 --- a/include/asm-powerpc/systbl.h +++ b/include/asm-powerpc/systbl.h @@ -307,3 +307,4 @@ COMPAT_SYS_SPU(set_robust_list) COMPAT_SYS_SPU(move_pages) SYSCALL_SPU(getcpu) COMPAT_SYS(epoll_pwait) +COMPAT_SYS_SPU(utimensat) diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h index 2baedbe..21f004a 100644 --- a/include/asm-powerpc/unistd.h +++ b/include/asm-powerpc/unistd.h @@ -326,10 +326,11 @@ #define __NR_move_pages 301 #define __NR_getcpu 302 #define __NR_epoll_pwait 303 +#define __NR_utimensat 304 #ifdef __KERNEL__ -#define __NR_syscalls 304 +#define __NR_syscalls 305 #define __NR__exit __NR_exit #define NR_syscalls __NR_syscalls diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h index 4f99df1..3972487 100644 --- a/include/asm-ppc/commproc.h +++ b/include/asm-ppc/commproc.h @@ -63,20 +63,15 @@ #define CPM_DATAONLY_SIZE ((uint)0x0700) #define CPM_DP_NOSPACE ((uint)0x7fffffff) -static inline long IS_DPERR(const uint offset) -{ - return (uint)offset > (uint)-1000L; -} - /* Export the base address of the communication processor registers * and dual port ram. */ extern cpm8xx_t *cpmp; /* Pointer to comm processor */ -extern uint cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(uint offset); -extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(uint offset); +extern void *cpm_dpram_addr(unsigned long offset); extern uint cpm_dpram_phys(u8* addr); extern void cpm_setbrg(uint brg, uint rate); diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h index 220cc2d..12a2860 100644 --- a/include/asm-ppc/cpm2.h +++ b/include/asm-ppc/cpm2.h @@ -104,21 +104,16 @@ */ #define NUM_CPM_HOST_PAGES 2 -static inline long IS_DPERR(const uint offset) -{ - return (uint)offset > (uint)-1000L; -} - /* Export the base address of the communication processor registers * and dual port ram. */ extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ -extern uint cpm_dpalloc(uint size, uint align); -extern int cpm_dpfree(uint offset); -extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); +extern unsigned long cpm_dpalloc(uint size, uint align); +extern int cpm_dpfree(unsigned long offset); +extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align); extern void cpm_dpdump(void); -extern void *cpm_dpram_addr(uint offset); +extern void *cpm_dpram_addr(unsigned long offset); extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); extern void cpm2_reset(void); diff --git a/include/asm-s390/ccwdev.h b/include/asm-s390/ccwdev.h index 6795ece..4c2e171 100644 --- a/include/asm-s390/ccwdev.h +++ b/include/asm-s390/ccwdev.h @@ -16,6 +16,7 @@ /* structs from asm/cio.h */ struct irb; struct ccw1; +struct ccw_dev_id; /* simplified initializers for struct ccw_device: * CCW_DEVICE and CCW_DEVICE_DEVTYPE initialize one @@ -175,6 +176,7 @@ extern int ccw_device_set_offline(struct ccw_device *cdev); extern struct ciw *ccw_device_get_ciw(struct ccw_device *, __u32 cmd); extern __u8 ccw_device_get_path_mask(struct ccw_device *); +extern void ccw_device_get_id(struct ccw_device *, struct ccw_dev_id *); #define get_ccwdev_lock(x) (x)->ccwlock @@ -184,7 +186,6 @@ extern __u8 ccw_device_get_path_mask(struct ccw_device *); extern struct ccw_device *ccw_device_probe_console(void); // FIXME: these have to go -extern int _ccw_device_get_device_number(struct ccw_device *); extern int _ccw_device_get_subchannel_number(struct ccw_device *); extern void *ccw_device_get_chp_desc(struct ccw_device *, int); diff --git a/include/asm-s390/ipl.h b/include/asm-s390/ipl.h index bdcd448..2c40fd3 100644 --- a/include/asm-s390/ipl.h +++ b/include/asm-s390/ipl.h @@ -79,8 +79,8 @@ struct ipl_parameter_block { * IPL validity flags */ extern u32 ipl_flags; - extern u32 dump_prefix_page; +extern unsigned int zfcpdump_prefix_array[]; extern void do_reipl(void); extern void ipl_save_parameters(void); diff --git a/include/asm-s390/param.h b/include/asm-s390/param.h index 085a7e2..34aaa46 100644 --- a/include/asm-s390/param.h +++ b/include/asm-s390/param.h @@ -10,7 +10,7 @@ #define _ASMS390_PARAM_H #ifdef __KERNEL__ -# define HZ 100 /* Internal kernel timer frequency */ +# define HZ CONFIG_HZ /* Internal kernel timer frequency */ # define USER_HZ 100 /* .. some user interfaces are in "ticks" */ # define CLOCKS_PER_SEC (USER_HZ) /* like times() */ #endif diff --git a/include/asm-sparc64/openprom.h b/include/asm-sparc64/openprom.h index e01b805..26ec046 100644 --- a/include/asm-sparc64/openprom.h +++ b/include/asm-sparc64/openprom.h @@ -177,7 +177,7 @@ struct linux_nodeops { /* More fun PROM structures for device probing. */ #define PROMREG_MAX 24 #define PROMVADDR_MAX 16 -#define PROMINTR_MAX 15 +#define PROMINTR_MAX 32 struct linux_prom_registers { unsigned which_io; /* hi part of physical address */ diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 8bcfaa4..fccd8b5 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -182,7 +182,8 @@ extern int ec_read(u8 addr, u8 *val); extern int ec_write(u8 addr, u8 val); extern int ec_transaction(u8 command, const u8 *wdata, unsigned wdata_len, - u8 *rdata, unsigned rdata_len); + u8 *rdata, unsigned rdata_len, + int force_poll); #endif /*CONFIG_ACPI_EC*/ diff --git a/include/linux/crc-itu-t.h b/include/linux/crc-itu-t.h new file mode 100644 index 0000000..84920f3 --- /dev/null +++ b/include/linux/crc-itu-t.h @@ -0,0 +1,28 @@ +/* + * crc-itu-t.h - CRC ITU-T V.41 routine + * + * Implements the standard CRC ITU-T V.41: + * Width 16 + * Poly 0x0x1021 (x^16 + x^12 + x^15 + 1) + * Init 0 + * + * This source code is licensed under the GNU General Public License, + * Version 2. See the file COPYING for more details. + */ + +#ifndef CRC_ITU_T_H +#define CRC_ITU_T_H + +#include <linux/types.h> + +extern u16 const crc_itu_t_table[256]; + +extern u16 crc_itu_t(u16 crc, const u8 *buffer, size_t len); + +static inline u16 crc_itu_t_byte(u16 crc, const u8 data) +{ + return (crc << 8) ^ crc_itu_t_table[((crc >> 8) ^ data) & 0xff]; +} + +#endif /* CRC_ITU_T_H */ + diff --git a/include/linux/firewire-cdev.h b/include/linux/firewire-cdev.h new file mode 100644 index 0000000..d4455eb --- /dev/null +++ b/include/linux/firewire-cdev.h @@ -0,0 +1,229 @@ +/* + * Char device interface. + * + * Copyright (C) 2005-2006 Kristian Hoegsberg <krh@bitplanet.net> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#ifndef _LINUX_FIREWIRE_CDEV_H +#define _LINUX_FIREWIRE_CDEV_H + +#include <linux/ioctl.h> +#include <linux/types.h> +#include <linux/firewire-constants.h> + +#define FW_CDEV_EVENT_BUS_RESET 0x00 +#define FW_CDEV_EVENT_RESPONSE 0x01 +#define FW_CDEV_EVENT_REQUEST 0x02 +#define FW_CDEV_EVENT_ISO_INTERRUPT 0x03 + +/* The 'closure' fields are for user space to use. Data passed in the + * 'closure' field for a request will be returned in the corresponding + * event. It's a 64-bit type so that it's a fixed size type big + * enough to hold a pointer on all platforms. */ + +struct fw_cdev_event_common { + __u64 closure; + __u32 type; +}; + +struct fw_cdev_event_bus_reset { + __u64 closure; + __u32 type; + __u32 node_id; + __u32 local_node_id; + __u32 bm_node_id; + __u32 irm_node_id; + __u32 root_node_id; + __u32 generation; +}; + +struct fw_cdev_event_response { + __u64 closure; + __u32 type; + __u32 rcode; + __u32 length; + __u32 data[0]; +}; + +struct fw_cdev_event_request { + __u64 closure; + __u32 type; + __u32 tcode; + __u64 offset; + __u32 handle; + __u32 length; + __u32 data[0]; +}; + +struct fw_cdev_event_iso_interrupt { + __u64 closure; + __u32 type; + __u32 cycle; + __u32 header_length; /* Length in bytes of following headers. */ + __u32 header[0]; +}; + +union fw_cdev_event { + struct fw_cdev_event_common common; + struct fw_cdev_event_bus_reset bus_reset; + struct fw_cdev_event_response response; + struct fw_cdev_event_request request; + struct fw_cdev_event_iso_interrupt iso_interrupt; +}; + +#define FW_CDEV_IOC_GET_INFO _IOWR('#', 0x00, struct fw_cdev_get_info) +#define FW_CDEV_IOC_SEND_REQUEST _IOW('#', 0x01, struct fw_cdev_send_request) +#define FW_CDEV_IOC_ALLOCATE _IOWR('#', 0x02, struct fw_cdev_allocate) +#define FW_CDEV_IOC_DEALLOCATE _IOW('#', 0x03, struct fw_cdev_deallocate) +#define FW_CDEV_IOC_SEND_RESPONSE _IOW('#', 0x04, struct fw_cdev_send_response) +#define FW_CDEV_IOC_INITIATE_BUS_RESET _IOW('#', 0x05, struct fw_cdev_initiate_bus_reset) +#define FW_CDEV_IOC_ADD_DESCRIPTOR _IOWR('#', 0x06, struct fw_cdev_add_descriptor) +#define FW_CDEV_IOC_REMOVE_DESCRIPTOR _IOW('#', 0x07, struct fw_cdev_remove_descriptor) + +#define FW_CDEV_IOC_CREATE_ISO_CONTEXT _IOWR('#', 0x08, struct fw_cdev_create_iso_context) +#define FW_CDEV_IOC_QUEUE_ISO _IOWR('#', 0x09, struct fw_cdev_queue_iso) +#define FW_CDEV_IOC_START_ISO _IOW('#', 0x0a, struct fw_cdev_start_iso) +#define FW_CDEV_IOC_STOP_ISO _IOW('#', 0x0b, struct fw_cdev_stop_iso) + +/* FW_CDEV_VERSION History + * + * 1 Feb 18, 2007: Initial version. + */ +#define FW_CDEV_VERSION 1 + +struct fw_cdev_get_info { + /* The version field is just a running serial number. We + * never break backwards compatibility. Userspace passes in + * the version it expects and the kernel passes back the + * highest version it can provide. Even if the structs in + * this interface are extended in a later version, the kernel + * will not copy back more data than what was present in the + * interface version userspace expects. */ + __u32 version; + + /* If non-zero, at most rom_length bytes of config rom will be + * copied into that user space address. In either case, + * rom_length is updated with the actual length of the config + * rom. */ + __u32 rom_length; + __u64 rom; + + /* If non-zero, a fw_cdev_event_bus_reset struct will be + * copied here with the current state of the bus. This does + * not cause a bus reset to happen. The value of closure in + * this and sub-sequent bus reset events is set to + * bus_reset_closure. */ + __u64 bus_reset; + __u64 bus_reset_closure; + + /* The index of the card this devices belongs to. */ + __u32 card; +}; + +struct fw_cdev_send_request { + __u32 tcode; + __u32 length; + __u64 offset; + __u64 closure; + __u64 data; + __u32 generation; +}; + +struct fw_cdev_send_response { + __u32 rcode; + __u32 length; + __u64 data; + __u32 handle; +}; + +struct fw_cdev_allocate { + __u64 offset; + __u64 closure; + __u32 length; + __u32 handle; +}; + +struct fw_cdev_deallocate { + __u32 handle; +}; + +#define FW_CDEV_LONG_RESET 0 +#define FW_CDEV_SHORT_RESET 1 + +struct fw_cdev_initiate_bus_reset { + __u32 type; +}; + +struct fw_cdev_add_descriptor { + __u32 immediate; + __u32 key; + __u64 data; + __u32 length; + __u32 handle; +}; + +struct fw_cdev_remove_descriptor { + __u32 handle; +}; + +#define FW_CDEV_ISO_CONTEXT_TRANSMIT 0 +#define FW_CDEV_ISO_CONTEXT_RECEIVE 1 + +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG0 1 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG1 2 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG2 4 +#define FW_CDEV_ISO_CONTEXT_MATCH_TAG3 8 +#define FW_CDEV_ISO_CONTEXT_MATCH_ALL_TAGS 15 + +struct fw_cdev_create_iso_context { + __u32 type; + __u32 header_size; + __u32 channel; + __u32 speed; + __u64 closure; + __u32 handle; +}; + +struct fw_cdev_iso_packet { + __u16 payload_length; /* Length of indirect payload. */ + __u32 interrupt : 1; /* Generate interrupt on this packet */ + __u32 skip : 1; /* Set to not send packet at all. */ + __u32 tag : 2; + __u32 sy : 4; + __u32 header_length : 8; /* Length of immediate header. */ + __u32 header[0]; +}; + +struct fw_cdev_queue_iso { + __u64 packets; + __u64 data; + __u32 size; + __u32 handle; +}; + +struct fw_cdev_start_iso { + __s32 cycle; + __u32 sync; + __u32 tags; + __u32 handle; +}; + +struct fw_cdev_stop_iso { + __u32 handle; +}; + +#endif /* _LINUX_FIREWIRE_CDEV_H */ diff --git a/include/linux/firewire-constants.h b/include/linux/firewire-constants.h new file mode 100644 index 0000000..b316770 --- /dev/null +++ b/include/linux/firewire-constants.h @@ -0,0 +1,67 @@ +#ifndef _LINUX_FIREWIRE_CONSTANTS_H +#define _LINUX_FIREWIRE_CONSTANTS_H + +#define TCODE_WRITE_QUADLET_REQUEST 0x0 +#define TCODE_WRITE_BLOCK_REQUEST 0x1 +#define TCODE_WRITE_RESPONSE 0x2 +#define TCODE_READ_QUADLET_REQUEST 0x4 +#define TCODE_READ_BLOCK_REQUEST 0x5 +#define TCODE_READ_QUADLET_RESPONSE 0x6 +#define TCODE_READ_BLOCK_RESPONSE 0x7 +#define TCODE_CYCLE_START 0x8 +#define TCODE_LOCK_REQUEST 0x9 +#define TCODE_STREAM_DATA 0xa +#define TCODE_LOCK_RESPONSE 0xb + +#define EXTCODE_MASK_SWAP 0x1 +#define EXTCODE_COMPARE_SWAP 0x2 +#define EXTCODE_FETCH_ADD 0x3 +#define EXTCODE_LITTLE_ADD 0x4 +#define EXTCODE_BOUNDED_ADD 0x5 +#define EXTCODE_WRAP_ADD 0x6 +#define EXTCODE_VENDOR_DEPENDENT 0x7 + +/* Juju specific tcodes */ +#define TCODE_LOCK_MASK_SWAP (0x10 | EXTCODE_MASK_SWAP) +#define TCODE_LOCK_COMPARE_SWAP (0x10 | EXTCODE_COMPARE_SWAP) +#define TCODE_LOCK_FETCH_ADD (0x10 | EXTCODE_FETCH_ADD) +#define TCODE_LOCK_LITTLE_ADD (0x10 | EXTCODE_LITTLE_ADD) +#define TCODE_LOCK_BOUNDED_ADD (0x10 | EXTCODE_BOUNDED_ADD) +#define TCODE_LOCK_WRAP_ADD (0x10 | EXTCODE_WRAP_ADD) +#define TCODE_LOCK_VENDOR_DEPENDENT (0x10 | EXTCODE_VENDOR_DEPENDENT) + +#define RCODE_COMPLETE 0x0 +#define RCODE_CONFLICT_ERROR 0x4 +#define RCODE_DATA_ERROR 0x5 +#define RCODE_TYPE_ERROR 0x6 +#define RCODE_ADDRESS_ERROR 0x7 + +/* Juju specific rcodes */ +#define RCODE_SEND_ERROR 0x10 +#define RCODE_CANCELLED 0x11 +#define RCODE_BUSY 0x12 +#define RCODE_GENERATION 0x13 +#define RCODE_NO_ACK 0x14 + +#define SCODE_100 0x0 +#define SCODE_200 0x1 +#define SCODE_400 0x2 +#define SCODE_800 0x3 +#define SCODE_1600 0x4 +#define SCODE_3200 0x5 +#define SCODE_BETA 0x3 + +#define ACK_COMPLETE 0x1 +#define ACK_PENDING 0x2 +#define ACK_BUSY_X 0x4 +#define ACK_BUSY_A 0x5 +#define ACK_BUSY_B 0x6 +#define ACK_DATA_ERROR 0xd +#define ACK_TYPE_ERROR 0xe + +#define RETRY_1 0x00 +#define RETRY_X 0x01 +#define RETRY_A 0x02 +#define RETRY_B 0x03 + +#endif /* _LINUX_FIREWIRE_CONSTANTS_H */ diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 144b615..8645181 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -41,6 +41,16 @@ extern const char linux_proc_banner[]; #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) +/** + * upper_32_bits - return bits 32-63 of a number + * @n: the number we're accessing + * + * A basic shift-right of a 64- or 32-bit quantity. Use this to suppress + * the "right shift count >= width of type" warning when that quantity is + * 32-bits. + */ +#define upper_32_bits(n) ((u32)(((n) >> 16) >> 16)) + #define KERN_EMERG "<0>" /* system is unusable */ #define KERN_ALERT "<1>" /* action must be taken immediately */ #define KERN_CRIT "<2>" /* critical conditions */ diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h index e30687b..d5bb179 100644 --- a/include/linux/mm_types.h +++ b/include/linux/mm_types.h @@ -50,13 +50,16 @@ struct page { spinlock_t ptl; #endif struct { /* SLUB uses */ - struct page *first_page; /* Compound pages */ + void **lockless_freelist; struct kmem_cache *slab; /* Pointer to slab */ }; + struct { + struct page *first_page; /* Compound pages */ + }; }; union { pgoff_t index; /* Our offset within mapping. */ - void *freelist; /* SLUB: pointer to free object */ + void *freelist; /* SLUB: freelist req. slab lock */ }; struct list_head lru; /* Pageout list, eg. active_list * protected by zone->lru_lock ! diff --git a/include/linux/pmu.h b/include/linux/pmu.h index 37ca573..5ad913f 100644 --- a/include/linux/pmu.h +++ b/include/linux/pmu.h @@ -226,7 +226,7 @@ extern unsigned int pmu_power_flags; extern void pmu_backlight_init(void); /* some code needs to know if the PMU was suspended for hibernation */ -#ifdef CONFIG_PM +#if defined(CONFIG_PM) && defined(CONFIG_PPC32) extern int pmu_sys_suspended; #else /* if power management is not configured it can't be suspended */ |
