diff options
Diffstat (limited to 'include')
25 files changed, 192 insertions, 104 deletions
diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h index 7b74b60..19c3ead 100644 --- a/include/acpi/acpi_bus.h +++ b/include/acpi/acpi_bus.h @@ -168,8 +168,7 @@ struct acpi_device_flags { u32 power_manageable:1; u32 performance_manageable:1; u32 wake_capable:1; /* Wakeup(_PRW) supported? */ - u32 force_power_state:1; - u32 reserved:19; + u32 reserved:20; }; /* File System */ diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h index 14cb8d3..0212e18 100644 --- a/include/asm-blackfin/bfin-global.h +++ b/include/asm-blackfin/bfin-global.h @@ -80,6 +80,7 @@ extern int atomic_sub32(void); extern int atomic_ior32(void); extern int atomic_and32(void); extern int atomic_xor32(void); +extern void safe_user_instruction(void); extern void sigreturn_stub(void); extern void *l1_data_A_sram_alloc(size_t); diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h index e6df84e..37db66c 100644 --- a/include/asm-blackfin/fixed_code.h +++ b/include/asm-blackfin/fixed_code.h @@ -17,4 +17,6 @@ #define ATOMIC_SEQS_END 0x480 -#define FIXED_CODE_END 0x480 +#define SAFE_USER_INSTRUCTION 0x480 + +#define FIXED_CODE_END 0x490 diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h index c97ab03..8265ea4 100644 --- a/include/asm-blackfin/gptimers.h +++ b/include/asm-blackfin/gptimers.h @@ -197,6 +197,8 @@ uint32_t get_gptimer_period (int timer_id); uint32_t get_gptimer_count (int timer_id); uint16_t get_gptimer_intr (int timer_id); void clear_gptimer_intr (int timer_id); +uint16_t get_gptimer_over (int timer_id); +void clear_gptimer_over (int timer_id); void set_gptimer_config (int timer_id, uint16_t config); uint16_t get_gptimer_config (int timer_id); void set_gptimer_pulse_hi (int timer_id); diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h index d6c24c54..fc69cf9 100644 --- a/include/asm-blackfin/mach-bf527/defBF52x_base.h +++ b/include/asm-blackfin/mach-bf527/defBF52x_base.h @@ -1718,55 +1718,55 @@ /* Bit masks for HOST_CONTROL */ -#define HOST_EN 0x1 /* Host Enable */ -#define nHOST_EN 0x0 -#define HOST_END 0x2 /* Host Endianess */ -#define nHOST_END 0x0 -#define DATA_SIZE 0x4 /* Data Size */ -#define nDATA_SIZE 0x0 -#define HOST_RST 0x8 /* Host Reset */ -#define nHOST_RST 0x0 -#define HRDY_OVR 0x20 /* Host Ready Override */ -#define nHRDY_OVR 0x0 -#define INT_MODE 0x40 /* Interrupt Mode */ -#define nINT_MODE 0x0 -#define BT_EN 0x80 /* Bus Timeout Enable */ -#define nBT_EN 0x0 -#define EHW 0x100 /* Enable Host Write */ -#define nEHW 0x0 -#define EHR 0x200 /* Enable Host Read */ -#define nEHR 0x0 -#define BDR 0x400 /* Burst DMA Requests */ -#define nBDR 0x0 +#define HOST_CNTR_HOST_EN 0x1 /* Host Enable */ +#define HOST_CNTR_nHOST_EN 0x0 +#define HOST_CNTR_HOST_END 0x2 /* Host Endianess */ +#define HOST_CNTR_nHOST_END 0x0 +#define HOST_CNTR_DATA_SIZE 0x4 /* Data Size */ +#define HOST_CNTR_nDATA_SIZE 0x0 +#define HOST_CNTR_HOST_RST 0x8 /* Host Reset */ +#define HOST_CNTR_nHOST_RST 0x0 +#define HOST_CNTR_HRDY_OVR 0x20 /* Host Ready Override */ +#define HOST_CNTR_nHRDY_OVR 0x0 +#define HOST_CNTR_INT_MODE 0x40 /* Interrupt Mode */ +#define HOST_CNTR_nINT_MODE 0x0 +#define HOST_CNTR_BT_EN 0x80 /* Bus Timeout Enable */ +#define HOST_CNTR_ nBT_EN 0x0 +#define HOST_CNTR_EHW 0x100 /* Enable Host Write */ +#define HOST_CNTR_nEHW 0x0 +#define HOST_CNTR_EHR 0x200 /* Enable Host Read */ +#define HOST_CNTR_nEHR 0x0 +#define HOST_CNTR_BDR 0x400 /* Burst DMA Requests */ +#define HOST_CNTR_nBDR 0x0 /* Bit masks for HOST_STATUS */ -#define READY 0x1 /* DMA Ready */ -#define nREADY 0x0 -#define FIFOFULL 0x2 /* FIFO Full */ -#define nFIFOFULL 0x0 -#define FIFOEMPTY 0x4 /* FIFO Empty */ -#define nFIFOEMPTY 0x0 -#define COMPLETE 0x8 /* DMA Complete */ -#define nCOMPLETE 0x0 -#define HSHK 0x10 /* Host Handshake */ -#define nHSHK 0x0 -#define TIMEOUT 0x20 /* Host Timeout */ -#define nTIMEOUT 0x0 -#define HIRQ 0x40 /* Host Interrupt Request */ -#define nHIRQ 0x0 -#define ALLOW_CNFG 0x80 /* Allow New Configuration */ -#define nALLOW_CNFG 0x0 -#define DMA_DIR 0x100 /* DMA Direction */ -#define nDMA_DIR 0x0 -#define BTE 0x200 /* Bus Timeout Enabled */ -#define nBTE 0x0 -#define HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ -#define nHOSTRD_DONE 0x0 +#define HOST_STAT_READY 0x1 /* DMA Ready */ +#define HOST_STAT_nREADY 0x0 +#define HOST_STAT_FIFOFULL 0x2 /* FIFO Full */ +#define HOST_STAT_nFIFOFULL 0x0 +#define HOST_STAT_FIFOEMPTY 0x4 /* FIFO Empty */ +#define HOST_STAT_nFIFOEMPTY 0x0 +#define HOST_STAT_COMPLETE 0x8 /* DMA Complete */ +#define HOST_STAT_nCOMPLETE 0x0 +#define HOST_STAT_HSHK 0x10 /* Host Handshake */ +#define HOST_STAT_nHSHK 0x0 +#define HOST_STAT_TIMEOUT 0x20 /* Host Timeout */ +#define HOST_STAT_nTIMEOUT 0x0 +#define HOST_STAT_HIRQ 0x40 /* Host Interrupt Request */ +#define HOST_STAT_nHIRQ 0x0 +#define HOST_STAT_ALLOW_CNFG 0x80 /* Allow New Configuration */ +#define HOST_STAT_nALLOW_CNFG 0x0 +#define HOST_STAT_DMA_DIR 0x100 /* DMA Direction */ +#define HOST_STAT_nDMA_DIR 0x0 +#define HOST_STAT_BTE 0x200 /* Bus Timeout Enabled */ +#define HOST_STAT_nBTE 0x0 +#define HOST_STAT_HOSTRD_DONE 0x8000 /* Host Read Completion Interrupt */ +#define HOST_STAT_nHOSTRD_DONE 0x0 /* Bit masks for HOST_TIMEOUT */ -#define COUNT_TIMEOUT 0x7ff /* Host Timeout count */ +#define HOST_COUNT_TIMEOUT 0x7ff /* Host Timeout count */ /* Bit masks for CNT_CONFIG */ diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h index a41627a..2dfee12 100644 --- a/include/asm-blackfin/mach-bf527/dma.h +++ b/include/asm-blackfin/mach-bf527/dma.h @@ -35,7 +35,6 @@ #define MAX_BLACKFIN_DMA_CHANNEL 16 #define CH_PPI 0 /* PPI receive/transmit or NFC */ -#define CH_NFC 0 /* PPI receive/transmit or NFC */ #define CH_EMAC_RX 1 /* Ethernet MAC receive or HOSTDP */ #define CH_EMAC_HOSTDP 1 /* Ethernet MAC receive or HOSTDP */ #define CH_EMAC_TX 2 /* Ethernet MAC transmit or NFC */ @@ -54,6 +53,12 @@ #define CH_MEM_STREAM1_DEST 14 /* TX */ #define CH_MEM_STREAM1_SRC 15 /* RX */ +#if defined(CONFIG_BF527_NAND_D_PORTF) +#define CH_NFC CH_PPI /* PPI receive/transmit or NFC */ +#elif defined(CONFIG_BF527_NAND_D_PORTH) +#define CH_NFC CH_EMAC_TX /* PPI receive/transmit or NFC */ +#endif + extern int channel2irq(unsigned int channel); extern struct dma_register *base_addr[]; diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h index 4e46d65..fcb72b4 100644 --- a/include/asm-blackfin/mach-bf548/defBF549.h +++ b/include/asm-blackfin/mach-bf548/defBF549.h @@ -1671,7 +1671,7 @@ /* Bit masks for MXVR_DMAx_CONFIG */ #define MDMAEN 0x1 /* DMA Channel Enable */ -#define DD 0x2 /* DMA Channel Direction */ +#define DMADD 0x2 /* DMA Channel Direction */ #define BY4SWAPEN 0x20 /* DMA Channel Four Byte Swap Enable */ #define LCHAN 0x3c0 /* DMA Channel Logical Channel */ #define BITSWAPEN 0x400 /* DMA Channel Bit Swap Enable */ diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h index 1d365c8..da979cb 100644 --- a/include/asm-blackfin/mach-bf548/defBF54x_base.h +++ b/include/asm-blackfin/mach-bf548/defBF54x_base.h @@ -2252,6 +2252,13 @@ #define PLL_OFF 0x2 /* Disable PLL */ #define DF 0x1 /* Divide Frequency */ +/* SWRST Masks */ +#define SYSTEM_RESET 0x0007 /* Initiates A System Software Reset */ +#define DOUBLE_FAULT 0x0008 /* Core Double Fault Causes Reset */ +#define RESET_DOUBLE 0x2000 /* SW Reset Generated By Core Double-Fault */ +#define RESET_WDOG 0x4000 /* SW Reset Generated By Watchdog Timer */ +#define RESET_SOFTWARE 0x8000 /* SW Reset Occurred Since Last Read Of SWRST */ + /* Bit masks for PLL_STAT */ #define PLL_LOCKED 0x20 /* PLL Locked Status */ diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h index b382deb..6b48512 100644 --- a/include/asm-blackfin/mach-bf548/portmux.h +++ b/include/asm-blackfin/mach-bf548/portmux.h @@ -267,4 +267,18 @@ #define P_AMC_BG (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0)) #define P_AMC_BGH (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0)) + +#define P_NAND_D0 (P_DONTCARE) +#define P_NAND_D1 (P_DONTCARE) +#define P_NAND_D2 (P_DONTCARE) +#define P_NAND_D3 (P_DONTCARE) +#define P_NAND_D4 (P_DONTCARE) +#define P_NAND_D5 (P_DONTCARE) +#define P_NAND_D6 (P_DONTCARE) +#define P_NAND_D7 (P_DONTCARE) +#define P_NAND_WE (P_DONTCARE) +#define P_NAND_RE (P_DONTCARE) +#define P_NAND_CLE (P_DONTCARE) +#define P_NAND_ALE (P_DONTCARE) + #endif /* _MACH_PORTMUX_H_ */ diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h index bf7dc4e..7945e8a 100644 --- a/include/asm-blackfin/mach-bf561/defBF561.h +++ b/include/asm-blackfin/mach-bf561/defBF561.h @@ -55,6 +55,9 @@ /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */ #define SWRST SICA_SWRST #define SYSCR SICA_SYSCR +#define RESET_DOUBLE (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A) +#define RESET_WDOG (SWRST_WDT_B|SWRST_WDT_A) +#define RESET_SOFTWARE (SWRST_OCCURRED) /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */ #define SICA_SWRST 0xFFC00100 /* Software Reset register */ diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h index 042f8218..ab5612f 100644 --- a/include/asm-mips/ip32/ip32_ints.h +++ b/include/asm-mips/ip32/ip32_ints.h @@ -22,10 +22,12 @@ enum ip32_irq_no { * CPU interrupts are 0 ... 7 */ + CRIME_IRQ_BASE = MIPS_CPU_IRQ_BASE, + /* * MACE */ - MACE_VID_IN1_IRQ = MIPS_CPU_IRQ_BASE + 8, + MACE_VID_IN1_IRQ = CRIME_IRQ_BASE, MACE_VID_IN2_IRQ, MACE_VID_OUT_IRQ, MACE_ETHERNET_IRQ, diff --git a/include/asm-mips/jmr3927/jmr3927.h b/include/asm-mips/jmr3927/jmr3927.h index b2dc35f..81602c8 100644 --- a/include/asm-mips/jmr3927/jmr3927.h +++ b/include/asm-mips/jmr3927/jmr3927.h @@ -132,9 +132,7 @@ #define JMR3927_IRQ_IRC_DMA (JMR3927_IRQ_IRC + TX3927_IR_DMA) #define JMR3927_IRQ_IRC_PIO (JMR3927_IRQ_IRC + TX3927_IR_PIO) #define JMR3927_IRQ_IRC_PCI (JMR3927_IRQ_IRC + TX3927_IR_PCI) -#define JMR3927_IRQ_IRC_TMR0 (JMR3927_IRQ_IRC + TX3927_IR_TMR0) -#define JMR3927_IRQ_IRC_TMR1 (JMR3927_IRQ_IRC + TX3927_IR_TMR1) -#define JMR3927_IRQ_IRC_TMR2 (JMR3927_IRQ_IRC + TX3927_IR_TMR2) +#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch)) #define JMR3927_IRQ_IOC_PCIA (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA) #define JMR3927_IRQ_IOC_PCIB (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB) #define JMR3927_IRQ_IOC_PCIC (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC) @@ -148,17 +146,12 @@ #define JMR3927_IRQ_IOCINT JMR3927_IRQ_IRC_INT1 /* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */ #define JMR3927_IRQ_ETHER0 JMR3927_IRQ_IRC_INT3 -/* Clock Tick (10ms) */ -#define JMR3927_IRQ_TICK JMR3927_IRQ_IRC_TMR0 /* Clocks */ #define JMR3927_CORECLK 132710400 /* 132.7MHz */ #define JMR3927_GBUSCLK (JMR3927_CORECLK / 2) /* 66.35MHz */ #define JMR3927_IMCLK (JMR3927_CORECLK / 4) /* 33.17MHz */ -#define jmr3927_tmrptr tx3927_tmrptr(0) /* TMR0 */ - - /* * TX3927 Pin Configuration: * diff --git a/include/asm-mips/jmr3927/tx3927.h b/include/asm-mips/jmr3927/tx3927.h index 211bcf4..338f998 100644 --- a/include/asm-mips/jmr3927/tx3927.h +++ b/include/asm-mips/jmr3927/tx3927.h @@ -222,9 +222,7 @@ struct tx3927_ccfg_reg { #define TX3927_IR_DMA 8 #define TX3927_IR_PIO 9 #define TX3927_IR_PCI 10 -#define TX3927_IR_TMR0 13 -#define TX3927_IR_TMR1 14 -#define TX3927_IR_TMR2 15 +#define TX3927_IR_TMR(ch) (13 + (ch)) #define TX3927_NUM_IR 16 /* diff --git a/include/asm-mips/jmr3927/txx927.h b/include/asm-mips/jmr3927/txx927.h index 58a8ff6..0474fe8 100644 --- a/include/asm-mips/jmr3927/txx927.h +++ b/include/asm-mips/jmr3927/txx927.h @@ -10,22 +10,6 @@ #ifndef __ASM_TXX927_H #define __ASM_TXX927_H -struct txx927_tmr_reg { - volatile unsigned long tcr; - volatile unsigned long tisr; - volatile unsigned long cpra; - volatile unsigned long cprb; - volatile unsigned long itmr; - volatile unsigned long unused0[3]; - volatile unsigned long ccdr; - volatile unsigned long unused1[3]; - volatile unsigned long pgmr; - volatile unsigned long unused2[3]; - volatile unsigned long wtmr; - volatile unsigned long unused3[43]; - volatile unsigned long trr; -}; - struct txx927_sio_reg { volatile unsigned long lcr; volatile unsigned long dicr; @@ -51,27 +35,6 @@ struct txx927_pio_reg { }; /* - * TMR - */ -/* TMTCR : Timer Control */ -#define TXx927_TMTCR_TCE 0x00000080 -#define TXx927_TMTCR_CCDE 0x00000040 -#define TXx927_TMTCR_CRE 0x00000020 -#define TXx927_TMTCR_ECES 0x00000008 -#define TXx927_TMTCR_CCS 0x00000004 -#define TXx927_TMTCR_TMODE_MASK 0x00000003 -#define TXx927_TMTCR_TMODE_ITVL 0x00000000 - -/* TMTISR : Timer Int. Status */ -#define TXx927_TMTISR_TPIBS 0x00000004 -#define TXx927_TMTISR_TPIAS 0x00000002 -#define TXx927_TMTISR_TIIS 0x00000001 - -/* TMTITMR : Interval Timer Mode */ -#define TXx927_TMTITMR_TIIE 0x00008000 -#define TXx927_TMTITMR_TZCE 0x00000001 - -/* * SIO */ /* SILCR : Line Control */ diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index bc47af3..0a6bc7d 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -58,7 +58,6 @@ extern void local_timer_interrupt(int irq, void *dev_id); */ struct irqaction; extern void plat_time_init(void); -extern void plat_timer_setup(struct irqaction *irq); /* * mips_hpt_frequency - must be set if you intend to use an R4k-compatible @@ -78,6 +77,7 @@ extern int (*perf_irq)(void); */ #ifdef CONFIG_CEVT_R4K extern void mips_clockevent_init(void); +extern unsigned int __weak get_c0_compare_int(void); #else static inline void mips_clockevent_init(void) { diff --git a/include/asm-mips/tx4927/tx4927_pci.h b/include/asm-mips/tx4927/tx4927_pci.h index f98b2bb..3f1e470 100644 --- a/include/asm-mips/tx4927/tx4927_pci.h +++ b/include/asm-mips/tx4927/tx4927_pci.h @@ -9,6 +9,7 @@ #define __ASM_TX4927_TX4927_PCI_H #define TX4927_CCFG_TOE 0x00004000 +#define TX4927_CCFG_TINTDIS 0x01000000 #define TX4927_PCIMEM 0x08000000 #define TX4927_PCIMEM_SIZE 0x08000000 @@ -20,6 +21,8 @@ #define TX4927_PCIC_REG 0xff1fd000 #define TX4927_CCFG_REG 0xff1fe000 #define TX4927_IRC_REG 0xff1ff600 +#define TX4927_NR_TMR 3 +#define TX4927_TMR_REG(ch) (0xff1ff000 + (ch) * 0x100) #define TX4927_CE3 0x17f00000 /* 1M */ #define TX4927_PCIRESET_ADDR 0xbc00f006 #define TX4927_PCI_CLK_ADDR (KSEG1 + TX4927_CE3 + 0x00040020) diff --git a/include/asm-mips/tx4938/tx4938.h b/include/asm-mips/tx4938/tx4938.h index 650b010..f7c448b 100644 --- a/include/asm-mips/tx4938/tx4938.h +++ b/include/asm-mips/tx4938/tx4938.h @@ -641,7 +641,6 @@ struct tx4938_ccfg_reg { #define tx4938_pcicptr ((struct tx4938_pcic_reg *)TX4938_PCIC_REG) #define tx4938_pcic1ptr ((struct tx4938_pcic_reg *)TX4938_PCIC1_REG) #define tx4938_ccfgptr ((struct tx4938_ccfg_reg *)TX4938_CCFG_REG) -#define tx4938_tmrptr(ch) ((struct tx4938_tmr_reg *)TX4938_TMR_REG(ch)) #define tx4938_sioptr(ch) ((struct tx4938_sio_reg *)TX4938_SIO_REG(ch)) #define tx4938_pioptr ((struct tx4938_pio_reg *)TX4938_PIO_REG) #define tx4938_aclcptr ((struct tx4938_aclc_reg *)TX4938_ACLC_REG) diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h new file mode 100644 index 0000000..67f70a8 --- /dev/null +++ b/include/asm-mips/txx9tmr.h @@ -0,0 +1,67 @@ +/* + * include/asm-mips/txx9tmr.h + * TX39/TX49 timer controller definitions. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_TXX9TMR_H +#define __ASM_TXX9TMR_H + +#include <linux/types.h> + +struct txx9_tmr_reg { + u32 tcr; + u32 tisr; + u32 cpra; + u32 cprb; + u32 itmr; + u32 unused0[3]; + u32 ccdr; + u32 unused1[3]; + u32 pgmr; + u32 unused2[3]; + u32 wtmr; + u32 unused3[43]; + u32 trr; +}; + +/* TMTCR : Timer Control */ +#define TXx9_TMTCR_TCE 0x00000080 +#define TXx9_TMTCR_CCDE 0x00000040 +#define TXx9_TMTCR_CRE 0x00000020 +#define TXx9_TMTCR_ECES 0x00000008 +#define TXx9_TMTCR_CCS 0x00000004 +#define TXx9_TMTCR_TMODE_MASK 0x00000003 +#define TXx9_TMTCR_TMODE_ITVL 0x00000000 +#define TXx9_TMTCR_TMODE_PGEN 0x00000001 +#define TXx9_TMTCR_TMODE_WDOG 0x00000002 + +/* TMTISR : Timer Int. Status */ +#define TXx9_TMTISR_TPIBS 0x00000004 +#define TXx9_TMTISR_TPIAS 0x00000002 +#define TXx9_TMTISR_TIIS 0x00000001 + +/* TMITMR : Interval Timer Mode */ +#define TXx9_TMITMR_TIIE 0x00008000 +#define TXx9_TMITMR_TZCE 0x00000001 + +/* TMWTMR : Watchdog Timer Mode */ +#define TXx9_TMWTMR_TWIE 0x00008000 +#define TXx9_TMWTMR_WDIS 0x00000080 +#define TXx9_TMWTMR_TWC 0x00000001 + +void txx9_clocksource_init(unsigned long baseaddr, + unsigned int imbusclk); +void txx9_clockevent_init(unsigned long baseaddr, int irq, + unsigned int imbusclk); +void txx9_tmr_init(unsigned long baseaddr); + +#ifdef CONFIG_CPU_TX39XX +#define TXX9_TIMER_BITS 24 +#else +#define TXX9_TIMER_BITS 32 +#endif + +#endif /* __ASM_TXX9TMR_H */ diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h new file mode 100644 index 0000000..f704c50 --- /dev/null +++ b/include/asm-x86/gart.h @@ -0,0 +1,29 @@ +#ifndef _ASM_X8664_IOMMU_H +#define _ASM_X8664_IOMMU_H 1 + +extern void pci_iommu_shutdown(void); +extern void no_iommu_init(void); +extern int force_iommu, no_iommu; +extern int iommu_detected; +#ifdef CONFIG_GART_IOMMU +extern void gart_iommu_init(void); +extern void gart_iommu_shutdown(void); +extern void __init gart_parse_options(char *); +extern void gart_iommu_hole_init(void); +extern int fallback_aper_order; +extern int fallback_aper_force; +extern int gart_iommu_aperture; +extern int gart_iommu_aperture_allowed; +extern int gart_iommu_aperture_disabled; +extern int fix_aperture; +#else +#define gart_iommu_aperture 0 +#define gart_iommu_aperture_allowed 0 + +static inline void gart_iommu_shutdown(void) +{ +} + +#endif + +#endif diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h index 5af471f..07862fd 100644 --- a/include/asm-x86/iommu.h +++ b/include/asm-x86/iommu.h @@ -1,5 +1,5 @@ -#ifndef _ASM_X8664_IOMMU_H -#define _ASM_X8664_IOMMU_H 1 +#ifndef _ASM_X8664_GART_H +#define _ASM_X8664_GART_H 1 extern void pci_iommu_shutdown(void); extern void no_iommu_init(void); diff --git a/include/asm-x86/pci_64.h b/include/asm-x86/pci_64.h index 9baa46d..ef54226 100644 --- a/include/asm-x86/pci_64.h +++ b/include/asm-x86/pci_64.h @@ -37,7 +37,7 @@ extern int iommu_setup(char *opt); */ #define PCI_DMA_BUS_IS_PHYS (dma_ops->is_phys) -#if defined(CONFIG_IOMMU) || defined(CONFIG_CALGARY_IOMMU) +#if defined(CONFIG_GART_IOMMU) || defined(CONFIG_CALGARY_IOMMU) #define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ dma_addr_t ADDR_NAME; diff --git a/include/linux/Kbuild b/include/linux/Kbuild index 6a65231..bd33c22 100644 --- a/include/linux/Kbuild +++ b/include/linux/Kbuild @@ -149,6 +149,7 @@ header-y += ticable.h header-y += times.h header-y += tiocl.h header-y += tipc.h +header-y += tipc_config.h header-y += toshiba.h header-y += ultrasound.h header-y += un.h diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h index c83534e..0365ec9 100644 --- a/include/linux/bootmem.h +++ b/include/linux/bootmem.h @@ -59,7 +59,6 @@ extern void *__alloc_bootmem_core(struct bootmem_data *bdata, unsigned long align, unsigned long goal, unsigned long limit); -extern void *alloc_bootmem_high_node(pg_data_t *pgdat, unsigned long size); #ifndef CONFIG_HAVE_ARCH_BOOTMEM_NODE extern void reserve_bootmem(unsigned long addr, unsigned long size); diff --git a/include/linux/ipmi_smi.h b/include/linux/ipmi_smi.h index 56ae438..6e8cec5 100644 --- a/include/linux/ipmi_smi.h +++ b/include/linux/ipmi_smi.h @@ -173,7 +173,7 @@ static inline int ipmi_demangle_device_id(const unsigned char *data, id->firmware_revision_2 = data[3]; id->ipmi_version = data[4]; id->additional_device_support = data[5]; - if (data_len >= 6) { + if (data_len >= 11) { id->manufacturer_id = (data[6] | (data[7] << 8) | (data[8] << 16)); id->product_id = data[9] | (data[10] << 8); diff --git a/include/linux/sched.h b/include/linux/sched.h index 3c07d59..155d743 100644 --- a/include/linux/sched.h +++ b/include/linux/sched.h @@ -1009,6 +1009,7 @@ struct task_struct { unsigned int rt_priority; cputime_t utime, stime, utimescaled, stimescaled; cputime_t gtime; + cputime_t prev_utime, prev_stime; unsigned long nvcsw, nivcsw; /* context switch counts */ struct timespec start_time; /* monotonic time */ struct timespec real_start_time; /* boot based time */ |
