diff options
Diffstat (limited to 'include/dt-bindings')
| -rw-r--r-- | include/dt-bindings/clock/r8a7790-clock.h | 7 | ||||
| -rw-r--r-- | include/dt-bindings/clock/r8a7791-clock.h | 6 | ||||
| -rw-r--r-- | include/dt-bindings/gpio/tegra-gpio.h | 1 | ||||
| -rw-r--r-- | include/dt-bindings/pinctrl/pinctrl-tegra.h | 45 |
4 files changed, 59 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h index 420f0b0..859e9be 100644 --- a/include/dt-bindings/clock/r8a7790-clock.h +++ b/include/dt-bindings/clock/r8a7790-clock.h @@ -22,6 +22,9 @@ #define R8A7790_CLK_SD1 8 #define R8A7790_CLK_Z 9 +/* MSTP0 */ +#define R8A7790_CLK_MSIOF0 0 + /* MSTP1 */ #define R8A7790_CLK_TMU1 11 #define R8A7790_CLK_TMU3 21 @@ -37,8 +40,11 @@ #define R8A7790_CLK_SCIFA2 2 #define R8A7790_CLK_SCIFA1 3 #define R8A7790_CLK_SCIFA0 4 +#define R8A7790_CLK_MSIOF2 5 #define R8A7790_CLK_SCIFB0 6 #define R8A7790_CLK_SCIFB1 7 +#define R8A7790_CLK_MSIOF1 8 +#define R8A7790_CLK_MSIOF3 15 #define R8A7790_CLK_SCIFB2 16 #define R8A7790_CLK_SYS_DMAC0 18 #define R8A7790_CLK_SYS_DMAC1 19 @@ -91,6 +97,7 @@ #define R8A7790_CLK_GPIO0 12 #define R8A7790_CLK_RCAN1 15 #define R8A7790_CLK_RCAN0 16 +#define R8A7790_CLK_QSPI_MOD 17 #define R8A7790_CLK_IICDVFS 26 #define R8A7790_CLK_I2C3 28 #define R8A7790_CLK_I2C2 29 diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h index df1715b..30f82f2 100644 --- a/include/dt-bindings/clock/r8a7791-clock.h +++ b/include/dt-bindings/clock/r8a7791-clock.h @@ -21,6 +21,9 @@ #define R8A7791_CLK_SD0 7 #define R8A7791_CLK_Z 8 +/* MSTP0 */ +#define R8A7791_CLK_MSIOF0 0 + /* MSTP1 */ #define R8A7791_CLK_TMU1 11 #define R8A7791_CLK_TMU3 21 @@ -35,8 +38,10 @@ #define R8A7791_CLK_SCIFA2 2 #define R8A7791_CLK_SCIFA1 3 #define R8A7791_CLK_SCIFA0 4 +#define R8A7791_CLK_MSIOF2 5 #define R8A7791_CLK_SCIFB0 6 #define R8A7791_CLK_SCIFB1 7 +#define R8A7791_CLK_MSIOF1 8 #define R8A7791_CLK_SCIFB2 16 #define R8A7791_CLK_DMAC 18 @@ -89,6 +94,7 @@ #define R8A7791_CLK_GPIO0 12 #define R8A7791_CLK_RCAN1 15 #define R8A7791_CLK_RCAN0 16 +#define R8A7791_CLK_QSPI_MOD 17 #define R8A7791_CLK_I2C5 25 #define R8A7791_CLK_IICDVFS 26 #define R8A7791_CLK_I2C4 27 diff --git a/include/dt-bindings/gpio/tegra-gpio.h b/include/dt-bindings/gpio/tegra-gpio.h index 4d179c0..197dc28 100644 --- a/include/dt-bindings/gpio/tegra-gpio.h +++ b/include/dt-bindings/gpio/tegra-gpio.h @@ -43,6 +43,7 @@ #define TEGRA_GPIO_BANK_ID_CC 28 #define TEGRA_GPIO_BANK_ID_DD 29 #define TEGRA_GPIO_BANK_ID_EE 30 +#define TEGRA_GPIO_BANK_ID_FF 31 #define TEGRA_GPIO(bank, offset) \ ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset) diff --git a/include/dt-bindings/pinctrl/pinctrl-tegra.h b/include/dt-bindings/pinctrl/pinctrl-tegra.h new file mode 100644 index 0000000..ebafa49 --- /dev/null +++ b/include/dt-bindings/pinctrl/pinctrl-tegra.h @@ -0,0 +1,45 @@ +/* + * This header provides constants for Tegra pinctrl bindings. + * + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * Author: Laxman Dewangan <ldewangan@nvidia.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _DT_BINDINGS_PINCTRL_TEGRA_H +#define _DT_BINDINGS_PINCTRL_TEGRA_H + +/* + * Enable/disable for diffeent dt properties. This is applicable for + * properties nvidia,enable-input, nvidia,tristate, nvidia,open-drain, + * nvidia,lock, nvidia,rcv-sel, nvidia,high-speed-mode, nvidia,schmitt. + */ +#define TEGRA_PIN_DISABLE 0 +#define TEGRA_PIN_ENABLE 1 + +#define TEGRA_PIN_PULL_NONE 0 +#define TEGRA_PIN_PULL_DOWN 1 +#define TEGRA_PIN_PULL_UP 2 + +/* Low power mode driver */ +#define TEGRA_PIN_LP_DRIVE_DIV_8 0 +#define TEGRA_PIN_LP_DRIVE_DIV_4 1 +#define TEGRA_PIN_LP_DRIVE_DIV_2 2 +#define TEGRA_PIN_LP_DRIVE_DIV_1 3 + +/* Rising/Falling slew rate */ +#define TEGRA_PIN_SLEW_RATE_FASTEST 0 +#define TEGRA_PIN_SLEW_RATE_FAST 1 +#define TEGRA_PIN_SLEW_RATE_SLOW 2 +#define TEGRA_PIN_SLEW_RATE_SLOWEST 3 + +#endif |
