summaryrefslogtreecommitdiffstats
path: root/include/dt-bindings/reset
diff options
context:
space:
mode:
Diffstat (limited to 'include/dt-bindings/reset')
-rw-r--r--include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h27
-rw-r--r--include/dt-bindings/reset/snps,hsdk-v1-reset.h17
2 files changed, 44 insertions, 0 deletions
diff --git a/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
new file mode 100644
index 0000000..1f1b56e
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson8b-clkc-reset.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ *
+ * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+#define _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H
+
+#define CLKC_RESET_L2_CACHE_SOFT_RESET 0
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_A5_SOFT_RESET 1
+#define CLKC_RESET_SCU_SOFT_RESET 2
+#define CLKC_RESET_CPU0_SOFT_RESET 3
+#define CLKC_RESET_CPU1_SOFT_RESET 4
+#define CLKC_RESET_CPU2_SOFT_RESET 5
+#define CLKC_RESET_CPU3_SOFT_RESET 6
+#define CLKC_RESET_A5_GLOBAL_RESET 7
+#define CLKC_RESET_A5_AXI_SOFT_RESET 8
+#define CLKC_RESET_A5_ABP_SOFT_RESET 9
+#define CLKC_RESET_AXI_64_TO_128_BRIDGE_MMC_SOFT_RESET 10
+#define CLKC_RESET_VID_CLK_CNTL_SOFT_RESET 11
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_POST 12
+#define CLKC_RESET_VID_DIVIDER_CNTL_SOFT_RESET_PRE 13
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST 14
+#define CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE 15
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON8B_CLKC_RESET_H */
diff --git a/include/dt-bindings/reset/snps,hsdk-v1-reset.h b/include/dt-bindings/reset/snps,hsdk-v1-reset.h
new file mode 100644
index 0000000..d898c89
--- /dev/null
+++ b/include/dt-bindings/reset/snps,hsdk-v1-reset.h
@@ -0,0 +1,17 @@
+/**
+ * This header provides index for the HSDK v1 reset controller.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
+#define _DT_BINDINGS_RESET_CONTROLLER_HSDK_V1
+
+#define HSDK_V1_APB_RESET 0
+#define HSDK_V1_AXI_RESET 1
+#define HSDK_V1_ETH_RESET 2
+#define HSDK_V1_USB_RESET 3
+#define HSDK_V1_SDIO_RESET 4
+#define HSDK_V1_HDMI_RESET 5
+#define HSDK_V1_GFX_RESET 6
+#define HSDK_V1_DMAC_RESET 7
+#define HSDK_V1_EBI_RESET 8
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HSDK_V1*/
OpenPOWER on IntegriCloud