diff options
Diffstat (limited to 'include/asm-sh')
203 files changed, 14187 insertions, 0 deletions
diff --git a/include/asm-sh/a.out.h b/include/asm-sh/a.out.h new file mode 100644 index 0000000..6e9fca9 --- /dev/null +++ b/include/asm-sh/a.out.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SH_A_OUT_H +#define __ASM_SH_A_OUT_H + +struct exec +{ + unsigned long a_info; /* Use macros N_MAGIC, etc for access */ + unsigned a_text; /* length of text, in bytes */ + unsigned a_data; /* length of data, in bytes */ + unsigned a_bss; /* length of uninitialized data area for file, in bytes */ + unsigned a_syms; /* length of symbol table data in file, in bytes */ + unsigned a_entry; /* start address */ + unsigned a_trsize; /* length of relocation info for text, in bytes */ + unsigned a_drsize; /* length of relocation info for data, in bytes */ +}; + +#define N_TRSIZE(a) ((a).a_trsize) +#define N_DRSIZE(a) ((a).a_drsize) +#define N_SYMSIZE(a) ((a).a_syms) + +#ifdef __KERNEL__ + +#define STACK_TOP TASK_SIZE + +#endif + +#endif /* __ASM_SH_A_OUT_H */ diff --git a/include/asm-sh/adc.h b/include/asm-sh/adc.h new file mode 100644 index 0000000..5f85cf7 --- /dev/null +++ b/include/asm-sh/adc.h @@ -0,0 +1,13 @@ +#ifndef __ASM_ADC_H +#define __ASM_ADC_H +#ifdef __KERNEL__ +/* + * Copyright (C) 2004 Andriy Skulysh + */ + +#include <asm/cpu/adc.h> + +int adc_single(unsigned int channel); + +#endif /* __KERNEL__ */ +#endif /* __ASM_ADC_H */ diff --git a/include/asm-sh/addrspace.h b/include/asm-sh/addrspace.h new file mode 100644 index 0000000..dbb05d1 --- /dev/null +++ b/include/asm-sh/addrspace.h @@ -0,0 +1,38 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima + * + * Defitions for the address spaces of the SH CPUs. + */ +#ifndef __ASM_SH_ADDRSPACE_H +#define __ASM_SH_ADDRSPACE_H +#ifdef __KERNEL__ + +#include <asm/cpu/addrspace.h> + +/* Memory segments (32bit Priviledged mode addresses) */ +#define P0SEG 0x00000000 +#define P1SEG 0x80000000 +#define P2SEG 0xa0000000 +#define P3SEG 0xc0000000 +#define P4SEG 0xe0000000 + +/* Returns the privileged segment base of a given address */ +#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000) + +/* Returns the physical address of a PnSEG (n=1,2) address */ +#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff) + +/* + * Map an address to a certain privileged segment + */ +#define P1SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG)) +#define P2SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG)) +#define P3SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG)) +#define P4SEGADDR(a) ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG)) + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_ADDRSPACE_H */ diff --git a/include/asm-sh/adx/io.h b/include/asm-sh/adx/io.h new file mode 100644 index 0000000..ab1225f --- /dev/null +++ b/include/asm-sh/adx/io.h @@ -0,0 +1,86 @@ +/* + * include/asm-sh/io_adx.h + * + * Copyright (C) 2001 A&D Co., Ltd. + * + * This file may be copied or modified under the terms of the GNU + * General Public License. See linux/COPYING for more information. + * + * IO functions for an A&D ADX Board + */ + +#ifndef _ASM_SH_IO_ADX_H +#define _ASM_SH_IO_ADX_H + +#include <asm/io_generic.h> + +extern unsigned char adx_inb(unsigned long port); +extern unsigned short adx_inw(unsigned long port); +extern unsigned int adx_inl(unsigned long port); + +extern void adx_outb(unsigned char value, unsigned long port); +extern void adx_outw(unsigned short value, unsigned long port); +extern void adx_outl(unsigned int value, unsigned long port); + +extern unsigned char adx_inb_p(unsigned long port); +extern void adx_outb_p(unsigned char value, unsigned long port); + +extern void adx_insb(unsigned long port, void *addr, unsigned long count); +extern void adx_insw(unsigned long port, void *addr, unsigned long count); +extern void adx_insl(unsigned long port, void *addr, unsigned long count); +extern void adx_outsb(unsigned long port, const void *addr, unsigned long count); +extern void adx_outsw(unsigned long port, const void *addr, unsigned long count); +extern void adx_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned char adx_readb(unsigned long addr); +extern unsigned short adx_readw(unsigned long addr); +extern unsigned int adx_readl(unsigned long addr); +extern void adx_writeb(unsigned char b, unsigned long addr); +extern void adx_writew(unsigned short b, unsigned long addr); +extern void adx_writel(unsigned int b, unsigned long addr); + +extern void * adx_ioremap(unsigned long offset, unsigned long size); +extern void adx_iounmap(void *addr); + +extern unsigned long adx_isa_port2addr(unsigned long offset); + +extern void setup_adx(void); +extern void init_adx_IRQ(void); + +#ifdef __WANT_IO_DEF + +#define __inb adx_inb +#define __inw adx_inw +#define __inl adx_inl +#define __outb adx_outb +#define __outw adx_outw +#define __outl adx_outl + +#define __inb_p adx_inb_p +#define __inw_p adx_inw +#define __inl_p adx_inl +#define __outb_p adx_outb_p +#define __outw_p adx_outw +#define __outl_p adx_outl + +#define __insb adx_insb +#define __insw adx_insw +#define __insl adx_insl +#define __outsb adx_outsb +#define __outsw adx_outsw +#define __outsl adx_outsl + +#define __readb adx_readb +#define __readw adx_readw +#define __readl adx_readl +#define __writeb adx_writeb +#define __writew adx_writew +#define __writel adx_writel + +#define __isa_port2addr adx_isa_port2addr +#define __ioremap adx_ioremap +#define __iounmap adx_iounmap + +#endif + +#endif /* _ASM_SH_IO_AANDD_H */ diff --git a/include/asm-sh/atomic.h b/include/asm-sh/atomic.h new file mode 100644 index 0000000..3c4f805d --- /dev/null +++ b/include/asm-sh/atomic.h @@ -0,0 +1,114 @@ +#ifndef __ASM_SH_ATOMIC_H +#define __ASM_SH_ATOMIC_H + +/* + * Atomic operations that C can't guarantee us. Useful for + * resource counting etc.. + * + */ + +typedef struct { volatile int counter; } atomic_t; + +#define ATOMIC_INIT(i) ( (atomic_t) { (i) } ) + +#define atomic_read(v) ((v)->counter) +#define atomic_set(v,i) ((v)->counter = (i)) + +#include <asm/system.h> + +/* + * To get proper branch prediction for the main line, we must branch + * forward to code at the end of this object's .text section, then + * branch back to restart the operation. + */ + +static __inline__ void atomic_add(int i, atomic_t * v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v += i; + local_irq_restore(flags); +} + +static __inline__ void atomic_sub(int i, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v -= i; + local_irq_restore(flags); +} + +static __inline__ int atomic_add_return(int i, atomic_t * v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp += i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0) + +static __inline__ int atomic_sub_return(int i, atomic_t * v) +{ + unsigned long temp, flags; + + local_irq_save(flags); + temp = *(long *)v; + temp -= i; + *(long *)v = temp; + local_irq_restore(flags); + + return temp; +} + +#define atomic_dec_return(v) atomic_sub_return(1,(v)) +#define atomic_inc_return(v) atomic_add_return(1,(v)) + +/* + * atomic_inc_and_test - increment and test + * @v: pointer of type atomic_t + * + * Atomically increments @v by 1 + * and returns true if the result is zero, or false for all + * other cases. + */ +#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0) + +#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0) +#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0) + +#define atomic_inc(v) atomic_add(1,(v)) +#define atomic_dec(v) atomic_sub(1,(v)) + +static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v &= ~mask; + local_irq_restore(flags); +} + +static __inline__ void atomic_set_mask(unsigned int mask, atomic_t *v) +{ + unsigned long flags; + + local_irq_save(flags); + *(long *)v |= mask; + local_irq_restore(flags); +} + +/* Atomic operations are already serializing on SH */ +#define smp_mb__before_atomic_dec() barrier() +#define smp_mb__after_atomic_dec() barrier() +#define smp_mb__before_atomic_inc() barrier() +#define smp_mb__after_atomic_inc() barrier() + +#endif /* __ASM_SH_ATOMIC_H */ diff --git a/include/asm-sh/bigsur/bigsur.h b/include/asm-sh/bigsur/bigsur.h new file mode 100644 index 0000000..427245f --- /dev/null +++ b/include/asm-sh/bigsur/bigsur.h @@ -0,0 +1,80 @@ +/* + * + * Hitachi Big Sur Eval Board support + * + * Dustin McIntire (dustin@sensoria.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Derived from Hitachi SH7751 reference manual + * + */ + +#ifndef _ASM_BIGSUR_H_ +#define _ASM_BIGSUR_H_ + +#include <asm/irq.h> +#include <asm/hd64465/hd64465.h> + +/* 7751 Internal IRQ's used by external CPLD controller */ +#define BIGSUR_IRQ_LOW 0 +#define BIGSUR_IRQ_NUM 14 /* External CPLD level 1 IRQs */ +#define BIGSUR_IRQ_HIGH (BIGSUR_IRQ_LOW + BIGSUR_IRQ_NUM) +#define BIGSUR_2NDLVL_IRQ_LOW (HD64465_IRQ_BASE+HD64465_IRQ_NUM) +#define BIGSUR_2NDLVL_IRQ_NUM 32 /* Level 2 IRQs = 4 regs * 8 bits */ +#define BIGSUR_2NDLVL_IRQ_HIGH (BIGSUR_2NDLVL_IRQ_LOW + \ + BIGSUR_2NDLVL_IRQ_NUM) + +/* PCI interrupt base number (A_INTA-A_INTD) */ +#define BIGSUR_SH7751_PCI_IRQ_BASE (BIGSUR_2NDLVL_IRQ_LOW+10) + +/* CPLD registers and external chip addresses */ +#define BIGSUR_HD64464_ADDR 0xB2000000 +#define BIGSUR_DGDR 0xB1FFFE00 +#define BIGSUR_BIDR 0xB1FFFD00 +#define BIGSUR_CSLR 0xB1FFFC00 +#define BIGSUR_SW1R 0xB1FFFB00 +#define BIGSUR_DBGR 0xB1FFFA00 +#define BIGSUR_BDTR 0xB1FFF900 +#define BIGSUR_BDRR 0xB1FFF800 +#define BIGSUR_PPR1 0xB1FFF700 +#define BIGSUR_PPR2 0xB1FFF600 +#define BIGSUR_IDE2 0xB1FFF500 +#define BIGSUR_IDE3 0xB1FFF400 +#define BIGSUR_SPCR 0xB1FFF300 +#define BIGSUR_ETHR 0xB1FE0000 +#define BIGSUR_PPDR 0xB1FDFF00 +#define BIGSUR_ICTL 0xB1FDFE00 +#define BIGSUR_ICMD 0xB1FDFD00 +#define BIGSUR_DMA0 0xB1FDFC00 +#define BIGSUR_DMA1 0xB1FDFB00 +#define BIGSUR_IRQ0 0xB1FDFA00 +#define BIGSUR_IRQ1 0xB1FDF900 +#define BIGSUR_IRQ2 0xB1FDF800 +#define BIGSUR_IRQ3 0xB1FDF700 +#define BIGSUR_IMR0 0xB1FDF600 +#define BIGSUR_IMR1 0xB1FDF500 +#define BIGSUR_IMR2 0xB1FDF400 +#define BIGSUR_IMR3 0xB1FDF300 +#define BIGSUR_IRLMR0 0xB1FDF200 +#define BIGSUR_IRLMR1 0xB1FDF100 +#define BIGSUR_V320USC_ADDR 0xB1000000 +#define BIGSUR_HD64465_ADDR 0xB0000000 +#define BIGSUR_INTERNAL_BASE 0xB0000000 + +/* SMC ethernet card parameters */ +#define BIGSUR_ETHER_IOPORT 0x220 + +/* IDE register paramters */ +#define BIGSUR_IDECMD_IOPORT 0x1f0 +#define BIGSUR_IDECTL_IOPORT 0x1f8 + +/* LED bit position in BIGSUR_CSLR */ +#define BIGSUR_LED (1<<4) + +/* PCI: default LOCAL memory window sizes (seen from PCI bus) */ +#define BIGSUR_LSR0_SIZE (64*(1<<20)) //64MB +#define BIGSUR_LSR1_SIZE (64*(1<<20)) //64MB + +#endif /* _ASM_BIGSUR_H_ */ diff --git a/include/asm-sh/bigsur/io.h b/include/asm-sh/bigsur/io.h new file mode 100644 index 0000000..939735e --- /dev/null +++ b/include/asm-sh/bigsur/io.h @@ -0,0 +1,35 @@ +/* + * include/asm-sh/io_bigsur.h + * + * By Dustin McIntire (dustin@sensoria.com) (c)2001 + * Derived from io_hd64465.h, which bore the message: + * By Greg Banks <gbanks@pocketpenguins.com> + * (c) 2000 PocketPenguins Inc. + * and from io_hd64461.h, which bore the message: + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for a Hitachi Big Sur Evaluation Board. + */ + +#ifndef _ASM_SH_IO_BIGSUR_H +#define _ASM_SH_IO_BIGSUR_H + +#include <linux/types.h> + +extern unsigned long bigsur_isa_port2addr(unsigned long offset); +extern int bigsur_irq_demux(int irq); +/* Provision for generic secondary demux step -- used by PCMCIA code */ +extern void bigsur_register_irq_demux(int irq, + int (*demux)(int irq, void *dev), void *dev); +extern void bigsur_unregister_irq_demux(int irq); +/* Set this variable to 1 to see port traffic */ +extern int bigsur_io_debug; +/* Map a range of ports to a range of kernel virtual memory. */ +extern void bigsur_port_map(u32 baseport, u32 nports, u32 addr, u8 shift); +extern void bigsur_port_unmap(u32 baseport, u32 nports); + +#endif /* _ASM_SH_IO_BIGSUR_H */ + diff --git a/include/asm-sh/bigsur/serial.h b/include/asm-sh/bigsur/serial.h new file mode 100644 index 0000000..540f122 --- /dev/null +++ b/include/asm-sh/bigsur/serial.h @@ -0,0 +1,27 @@ +/* + * include/asm-sh/serial-bigsur.h + * + * Configuration details for Big Sur 16550 based serial ports + * i.e. HD64465, PCMCIA, etc. + */ + +#ifndef _ASM_SERIAL_BIGSUR_H +#define _ASM_SERIAL_BIGSUR_H +#include <asm/hd64465.h> + +#define BASE_BAUD (3379200 / 16) + +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ + + +#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS + +/* XXX: This should be moved ino irq.h */ +#define irq_cannonicalize(x) (x) + +#endif /* _ASM_SERIAL_BIGSUR_H */ diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h new file mode 100644 index 0000000..5163d1f --- /dev/null +++ b/include/asm-sh/bitops.h @@ -0,0 +1,476 @@ +#ifndef __ASM_SH_BITOPS_H +#define __ASM_SH_BITOPS_H + +#ifdef __KERNEL__ +#include <asm/system.h> +/* For __swab32 */ +#include <asm/byteorder.h> + +static __inline__ void set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a |= mask; + local_irq_restore(flags); +} + +static __inline__ void __set_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a |= mask; +} + +/* + * clear_bit() doesn't provide any barrier for the compiler. + */ +#define smp_mb__before_clear_bit() barrier() +#define smp_mb__after_clear_bit() barrier() +static __inline__ void clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a &= ~mask; + local_irq_restore(flags); +} + +static __inline__ void __clear_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a &= ~mask; +} + +static __inline__ void change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + *a ^= mask; + local_irq_restore(flags); +} + +static __inline__ void __change_bit(int nr, volatile void * addr) +{ + int mask; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + *a ^= mask; +} + +static __inline__ int test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a |= mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a |= mask; + + return retval; +} + +static __inline__ int test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a &= ~mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a &= ~mask; + + return retval; +} + +static __inline__ int test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + unsigned long flags; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + local_irq_save(flags); + retval = (mask & *a) != 0; + *a ^= mask; + local_irq_restore(flags); + + return retval; +} + +static __inline__ int __test_and_change_bit(int nr, volatile void * addr) +{ + int mask, retval; + volatile unsigned int *a = addr; + + a += nr >> 5; + mask = 1 << (nr & 0x1f); + retval = (mask & *a) != 0; + *a ^= mask; + + return retval; +} + +static __inline__ int test_bit(int nr, const volatile void *addr) +{ + return 1UL & (((const volatile unsigned int *) addr)[nr >> 5] >> (nr & 31)); +} + +static __inline__ unsigned long ffz(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bt/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * __ffs - find first bit in word. + * @word: The word to search + * + * Undefined if no bit exists, so code should check against 0 first. + */ +static __inline__ unsigned long __ffs(unsigned long word) +{ + unsigned long result; + + __asm__("1:\n\t" + "shlr %1\n\t" + "bf/s 1b\n\t" + " add #1, %0" + : "=r" (result), "=r" (word) + : "0" (~0L), "1" (word) + : "t"); + return result; +} + +/** + * find_next_bit - find the next set bit in a memory region + * @addr: The address to base the search on + * @offset: The bitnumber to start searching at + * @size: The maximum size to search + */ +static __inline__ unsigned long find_next_bit(const unsigned long *addr, + unsigned long size, unsigned long offset) +{ + unsigned int *p = ((unsigned int *) addr) + (offset >> 5); + unsigned int result = offset & ~31UL; + unsigned int tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *p++; + tmp &= ~0UL << offset; + if (size < 32) + goto found_first; + if (tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size >= 32) { + if ((tmp = *p++) != 0) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp &= ~0UL >> (32 - size); + if (tmp == 0UL) /* Are any bits set? */ + return result + size; /* Nope. */ +found_middle: + return result + __ffs(tmp); +} + +/** + * find_first_bit - find the first set bit in a memory region + * @addr: The address to start the search at + * @size: The maximum size to search + * + * Returns the bit-number of the first set bit, not the number of the byte + * containing a bit. + */ +#define find_first_bit(addr, size) \ + find_next_bit((addr), (size), 0) + +static __inline__ int find_next_zero_bit(const unsigned long *addr, int size, int offset) +{ + const unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if (offset) { + tmp = *(p++); + tmp |= ~0UL >> (32-offset); + if (size < 32) + goto found_first; + if (~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while (size & ~31UL) { + if (~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if (!size) + return result; + tmp = *p; + +found_first: + tmp |= ~0UL << size; +found_middle: + return result + ffz(tmp); +} + +#define find_first_zero_bit(addr, size) \ + find_next_zero_bit((addr), (size), 0) + +/* + * ffs: find first bit set. This is defined the same way as + * the libc and compiler builtin ffs routines, therefore + * differs in spirit from the above ffz (man ffs). + */ + +#define ffs(x) generic_ffs(x) + +/* + * hweightN: returns the hamming weight (i.e. the number + * of bits set) of a N-bit word + */ + +#define hweight32(x) generic_hweight32(x) +#define hweight16(x) generic_hweight16(x) +#define hweight8(x) generic_hweight8(x) + +/* + * Every architecture must define this function. It's the fastest + * way of searching a 140-bit bitmap where the first 100 bits are + * unlikely to be set. It's guaranteed that at least one of the 140 + * bits is cleared. + */ + +static inline int sched_find_first_bit(const unsigned long *b) +{ + if (unlikely(b[0])) + return __ffs(b[0]); + if (unlikely(b[1])) + return __ffs(b[1]) + 32; + if (unlikely(b[2])) + return __ffs(b[2]) + 64; + if (b[3]) + return __ffs(b[3]) + 96; + return __ffs(b[4]) + 128; +} + +#ifdef __LITTLE_ENDIAN__ +#define ext2_set_bit(nr, addr) test_and_set_bit((nr), (addr)) +#define ext2_clear_bit(nr, addr) test_and_clear_bit((nr), (addr)) +#define ext2_test_bit(nr, addr) test_bit((nr), (addr)) +#define ext2_find_first_zero_bit(addr, size) find_first_zero_bit((addr), (size)) +#define ext2_find_next_zero_bit(addr, size, offset) \ + find_next_zero_bit((unsigned long *)(addr), (size), (offset)) +#else +static __inline__ int ext2_set_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + local_irq_save(flags); + retval = (mask & *ADDR) != 0; + *ADDR |= mask; + local_irq_restore(flags); + return retval; +} + +static __inline__ int ext2_clear_bit(int nr, volatile void * addr) +{ + int mask, retval; + unsigned long flags; + volatile unsigned char *ADDR = (unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + local_irq_save(flags); + retval = (mask & *ADDR) != 0; + *ADDR &= ~mask; + local_irq_restore(flags); + return retval; +} + +static __inline__ int ext2_test_bit(int nr, const volatile void * addr) +{ + int mask; + const volatile unsigned char *ADDR = (const unsigned char *) addr; + + ADDR += nr >> 3; + mask = 1 << (nr & 0x07); + return ((mask & *ADDR) != 0); +} + +#define ext2_find_first_zero_bit(addr, size) \ + ext2_find_next_zero_bit((addr), (size), 0) + +static __inline__ unsigned long ext2_find_next_zero_bit(void *addr, unsigned long size, unsigned long offset) +{ + unsigned long *p = ((unsigned long *) addr) + (offset >> 5); + unsigned long result = offset & ~31UL; + unsigned long tmp; + + if (offset >= size) + return size; + size -= result; + offset &= 31UL; + if(offset) { + /* We hold the little endian value in tmp, but then the + * shift is illegal. So we could keep a big endian value + * in tmp, like this: + * + * tmp = __swab32(*(p++)); + * tmp |= ~0UL >> (32-offset); + * + * but this would decrease preformance, so we change the + * shift: + */ + tmp = *(p++); + tmp |= __swab32(~0UL >> (32-offset)); + if(size < 32) + goto found_first; + if(~tmp) + goto found_middle; + size -= 32; + result += 32; + } + while(size & ~31UL) { + if(~(tmp = *(p++))) + goto found_middle; + result += 32; + size -= 32; + } + if(!size) + return result; + tmp = *p; + +found_first: + /* tmp is little endian, so we would have to swab the shift, + * see above. But then we have to swab tmp below for ffz, so + * we might as well do this here. + */ + return result + ffz(__swab32(tmp) | (~0UL << size)); +found_middle: + return result + ffz(__swab32(tmp)); +} +#endif + +#define ext2_set_bit_atomic(lock, nr, addr) \ + ({ \ + int ret; \ + spin_lock(lock); \ + ret = ext2_set_bit((nr), (addr)); \ + spin_unlock(lock); \ + ret; \ + }) + +#define ext2_clear_bit_atomic(lock, nr, addr) \ + ({ \ + int ret; \ + spin_lock(lock); \ + ret = ext2_clear_bit((nr), (addr)); \ + spin_unlock(lock); \ + ret; \ + }) + +/* Bitmap functions for the minix filesystem. */ +#define minix_test_and_set_bit(nr,addr) test_and_set_bit(nr,addr) +#define minix_set_bit(nr,addr) set_bit(nr,addr) +#define minix_test_and_clear_bit(nr,addr) test_and_clear_bit(nr,addr) +#define minix_test_bit(nr,addr) test_bit(nr,addr) +#define minix_find_first_zero_bit(addr,size) find_first_zero_bit(addr,size) + +/* + * fls: find last bit set. + */ + +#define fls(x) generic_fls(x) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h new file mode 100644 index 0000000..7017221 --- /dev/null +++ b/include/asm-sh/bug.h @@ -0,0 +1,17 @@ +#ifndef __ASM_SH_BUG_H +#define __ASM_SH_BUG_H + +#include <linux/config.h> + +/* + * Tell the user there is some problem. + */ +#define BUG() do { \ + printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \ + *(volatile int *)0 = 0; \ +} while (0) + +#define HAVE_ARCH_BUG +#include <asm-generic/bug.h> + +#endif diff --git a/include/asm-sh/bugs.h b/include/asm-sh/bugs.h new file mode 100644 index 0000000..a6de3d0 --- /dev/null +++ b/include/asm-sh/bugs.h @@ -0,0 +1,50 @@ +#ifndef __ASM_SH_BUGS_H +#define __ASM_SH_BUGS_H + +/* + * This is included by init/main.c to check for architecture-dependent bugs. + * + * Needs: + * void check_bugs(void); + */ + +/* + * I don't know of any Super-H bugs yet. + */ + +#include <asm/processor.h> + +static void __init check_bugs(void) +{ + extern char *get_cpu_subtype(void); + extern unsigned long loops_per_jiffy; + char *p= &system_utsname.machine[2]; /* "sh" */ + + cpu_data->loops_per_jiffy = loops_per_jiffy; + + switch (cpu_data->type) { + case CPU_SH7604: + *p++ = '2'; + break; + case CPU_SH7705 ... CPU_SH7300: + *p++ = '3'; + break; + case CPU_SH7750 ... CPU_SH4_501: + *p++ = '4'; + break; + default: + *p++ = '?'; + *p++ = '!'; + break; + } + + printk("CPU: %s\n", get_cpu_subtype()); + +#ifndef __LITTLE_ENDIAN__ + /* 'eb' means 'Endian Big' */ + *p++ = 'e'; + *p++ = 'b'; +#endif + *p = '\0'; +} +#endif /* __ASM_SH_BUGS_H */ diff --git a/include/asm-sh/bus-sh.h b/include/asm-sh/bus-sh.h new file mode 100644 index 0000000..f782a33 --- /dev/null +++ b/include/asm-sh/bus-sh.h @@ -0,0 +1,65 @@ +/* + * include/asm-sh/bus-sh.h + * + * Copyright (C) 2004 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_BUS_SH_H +#define __ASM_SH_BUS_SH_H + +extern struct bus_type sh_bus_types[]; + +struct sh_dev { + struct device dev; + char *name; + unsigned int dev_id; + unsigned int bus_id; + struct resource res; + void *mapbase; + unsigned int irq[6]; + u64 *dma_mask; +}; + +#define to_sh_dev(d) container_of((d), struct sh_dev, dev) + +#define sh_get_drvdata(d) dev_get_drvdata(&(d)->dev) +#define sh_set_drvdata(d,p) dev_set_drvdata(&(d)->dev, (p)) + +struct sh_driver { + struct device_driver drv; + unsigned int dev_id; + unsigned int bus_id; + int (*probe)(struct sh_dev *); + int (*remove)(struct sh_dev *); + int (*suspend)(struct sh_dev *, u32); + int (*resume)(struct sh_dev *); +}; + +#define to_sh_driver(d) container_of((d), struct sh_driver, drv) +#define sh_name(d) ((d)->dev.driver->name) + +/* + * Device ID numbers for bus types + */ +enum { + SH_DEV_ID_USB_OHCI, +}; + +#define SH_NR_BUSES 1 +#define SH_BUS_NAME_VIRT "shbus" + +enum { + SH_BUS_VIRT, +}; + +/* arch/sh/kernel/cpu/bus.c */ +extern int sh_device_register(struct sh_dev *dev); +extern void sh_device_unregister(struct sh_dev *dev); +extern int sh_driver_register(struct sh_driver *drv); +extern void sh_driver_unregister(struct sh_driver *drv); + +#endif /* __ASM_SH_BUS_SH_H */ + diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h new file mode 100644 index 0000000..bff2b13 --- /dev/null +++ b/include/asm-sh/byteorder.h @@ -0,0 +1,56 @@ +#ifndef __ASM_SH_BYTEORDER_H +#define __ASM_SH_BYTEORDER_H + +/* + * Copyright (C) 1999 Niibe Yutaka + */ + +#include <asm/types.h> +#include <linux/compiler.h> + +static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x) +{ + __asm__("swap.b %0, %0\n\t" + "swap.w %0, %0\n\t" + "swap.b %0, %0" + : "=r" (x) + : "0" (x)); + return x; +} + +static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x) +{ + __asm__("swap.b %0, %0" + : "=r" (x) + : "0" (x)); + return x; +} + +static inline __u64 ___arch__swab64(__u64 val) +{ + union { + struct { __u32 a,b; } s; + __u64 u; + } v, w; + v.u = val; + w.s.b = ___arch__swab32(v.s.a); + w.s.a = ___arch__swab32(v.s.b); + return w.u; +} + +#define __arch__swab64(x) ___arch__swab64(x) +#define __arch__swab32(x) ___arch__swab32(x) +#define __arch__swab16(x) ___arch__swab16(x) + +#if !defined(__STRICT_ANSI__) || defined(__KERNEL__) +# define __BYTEORDER_HAS_U64__ +# define __SWAB_64_THRU_32__ +#endif + +#ifdef __LITTLE_ENDIAN__ +#include <linux/byteorder/little_endian.h> +#else +#include <linux/byteorder/big_endian.h> +#endif + +#endif /* __ASM_SH_BYTEORDER_H */ diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h new file mode 100644 index 0000000..9b4dd6d --- /dev/null +++ b/include/asm-sh/cache.h @@ -0,0 +1,48 @@ +/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $ + * + * include/asm-sh/cache.h + * + * Copyright 1999 (C) Niibe Yutaka + * Copyright 2002, 2003 (C) Paul Mundt + */ +#ifndef __ASM_SH_CACHE_H +#define __ASM_SH_CACHE_H +#ifdef __KERNEL__ + +#include <asm/cpu/cache.h> +#include <asm/cpu/cacheflush.h> + +#define SH_CACHE_VALID 1 +#define SH_CACHE_UPDATED 2 +#define SH_CACHE_COMBINED 4 +#define SH_CACHE_ASSOC 8 + +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) +#define SMP_CACHE_BYTES L1_CACHE_BYTES + +#define L1_CACHE_ALIGN(x) (((x)+(L1_CACHE_BYTES-1))&~(L1_CACHE_BYTES-1)) + +#define L1_CACHE_SHIFT_MAX 5 /* largest L1 which this arch supports */ + +struct cache_info { + unsigned int ways; + unsigned int sets; + unsigned int linesz; + + unsigned int way_incr; + + unsigned int entry_shift; + unsigned int entry_mask; + + unsigned long flags; +}; + +/* Flush (write-back only) a region (smaller than a page) */ +extern void __flush_wback_region(void *start, int size); +/* Flush (write-back & invalidate) a region (smaller than a page) */ +extern void __flush_purge_region(void *start, int size); +/* Flush (invalidate only) a region (smaller than a page) */ +extern void __flush_invalidate_region(void *start, int size); + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_CACHE_H */ diff --git a/include/asm-sh/cacheflush.h b/include/asm-sh/cacheflush.h new file mode 100644 index 0000000..9dfb33e --- /dev/null +++ b/include/asm-sh/cacheflush.h @@ -0,0 +1,31 @@ +#ifndef __ASM_SH_CACHEFLUSH_H +#define __ASM_SH_CACHEFLUSH_H +#ifdef __KERNEL__ + +#include <asm/cpu/cacheflush.h> + +/* Flush (write-back only) a region (smaller than a page) */ +extern void __flush_wback_region(void *start, int size); +/* Flush (write-back & invalidate) a region (smaller than a page) */ +extern void __flush_purge_region(void *start, int size); +/* Flush (invalidate only) a region (smaller than a page) */ +extern void __flush_invalidate_region(void *start, int size); + +#define flush_cache_vmap(start, end) flush_cache_all() +#define flush_cache_vunmap(start, end) flush_cache_all() + +#define copy_to_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + flush_cache_page(vma, vaddr, page_to_pfn(page));\ + memcpy(dst, src, len); \ + flush_icache_user_range(vma, page, vaddr, len); \ + } while (0) + +#define copy_from_user_page(vma, page, vaddr, dst, src, len) \ + do { \ + flush_cache_page(vma, vaddr, page_to_pfn(page));\ + memcpy(dst, src, len); \ + } while (0) + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_CACHEFLUSH_H */ diff --git a/include/asm-sh/cat68701/io.h b/include/asm-sh/cat68701/io.h new file mode 100644 index 0000000..753b846 --- /dev/null +++ b/include/asm-sh/cat68701/io.h @@ -0,0 +1,22 @@ +/* + * include/asm-sh/io_cat68701.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * 2001 Yutarou Ebihar (ebihara@si-linux.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an AONE Corp. CAT-68701 SH7708 Borad + */ + +#ifndef _ASM_SH_IO_CAT68701_H +#define _ASM_SH_IO_CAT68701_H + +extern unsigned long cat68701_isa_port2addr(unsigned long offset); +extern int cat68701_irq_demux(int irq); + +extern void init_cat68701_IRQ(void); +extern void heartbeat_cat68701(void); + +#endif /* _ASM_SH_IO_CAT68701_H */ diff --git a/include/asm-sh/checksum.h b/include/asm-sh/checksum.h new file mode 100644 index 0000000..5113c7f --- /dev/null +++ b/include/asm-sh/checksum.h @@ -0,0 +1,216 @@ +#ifndef __ASM_SH_CHECKSUM_H +#define __ASM_SH_CHECKSUM_H + +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka + */ + +#include <linux/config.h> +#include <linux/in6.h> + +/* + * computes the checksum of a memory block at buff, length len, + * and adds in "sum" (32-bit) + * + * returns a 32-bit number suitable for feeding into itself + * or csum_tcpudp_magic + * + * this function must be called with even lengths, except + * for the last fragment, which may be odd + * + * it's best to have buff aligned on a 32-bit boundary + */ +asmlinkage unsigned int csum_partial(const unsigned char * buff, int len, unsigned int sum); + +/* + * the same as csum_partial, but copies from src while it + * checksums, and handles user-space pointer exceptions correctly, when needed. + * + * here even more important to align src and dst on a 32-bit (or even + * better 64-bit) boundary + */ + +asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsigned char *dst, + int len, int sum, int *src_err_ptr, int *dst_err_ptr); + +/* + * Note: when you get a NULL pointer exception here this means someone + * passed in an incorrect kernel address to one of these functions. + * + * If you use these functions directly please don't forget the + * verify_area(). + */ +static __inline__ +unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst, + int len, int sum) +{ + return csum_partial_copy_generic ( src, dst, len, sum, NULL, NULL); +} + +static __inline__ +unsigned int csum_partial_copy_from_user (const unsigned char *src, unsigned char *dst, + int len, int sum, int *err_ptr) +{ + return csum_partial_copy_generic ( src, dst, len, sum, err_ptr, NULL); +} + +/* + * Fold a partial checksum + */ + +static __inline__ unsigned int csum_fold(unsigned int sum) +{ + unsigned int __dummy; + __asm__("swap.w %0, %1\n\t" + "extu.w %0, %0\n\t" + "extu.w %1, %1\n\t" + "add %1, %0\n\t" + "swap.w %0, %1\n\t" + "add %1, %0\n\t" + "not %0, %0\n\t" + : "=r" (sum), "=&r" (__dummy) + : "0" (sum) + : "t"); + return sum; +} + +/* + * This is a version of ip_compute_csum() optimized for IP headers, + * which always checksum on 4 octet boundaries. + * + * i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted + * for linux by * Arnt Gulbrandsen. + */ +static __inline__ unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl) +{ + unsigned int sum, __dummy0, __dummy1; + + __asm__ __volatile__( + "mov.l @%1+, %0\n\t" + "mov.l @%1+, %3\n\t" + "add #-2, %2\n\t" + "clrt\n\t" + "1:\t" + "addc %3, %0\n\t" + "movt %4\n\t" + "mov.l @%1+, %3\n\t" + "dt %2\n\t" + "bf/s 1b\n\t" + " cmp/eq #1, %4\n\t" + "addc %3, %0\n\t" + "addc %2, %0" /* Here %2 is 0, add carry-bit */ + /* Since the input registers which are loaded with iph and ihl + are modified, we must also specify them as outputs, or gcc + will assume they contain their original values. */ + : "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1) + : "1" (iph), "2" (ihl) + : "t"); + + return csum_fold(sum); +} + +static __inline__ unsigned long csum_tcpudp_nofold(unsigned long saddr, + unsigned long daddr, + unsigned short len, + unsigned short proto, + unsigned int sum) +{ +#ifdef __LITTLE_ENDIAN__ + unsigned long len_proto = (ntohs(len)<<16)+proto*256; +#else + unsigned long len_proto = (proto<<16)+len; +#endif + __asm__("clrt\n\t" + "addc %0, %1\n\t" + "addc %2, %1\n\t" + "addc %3, %1\n\t" + "movt %0\n\t" + "add %1, %0" + : "=r" (sum), "=r" (len_proto) + : "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum) + : "t"); + return sum; +} + +/* + * computes the checksum of the TCP/UDP pseudo-header + * returns a 16-bit checksum, already complemented + */ +static __inline__ unsigned short int csum_tcpudp_magic(unsigned long saddr, + unsigned long daddr, + unsigned short len, + unsigned short proto, + unsigned int sum) +{ + return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum)); +} + +/* + * this routine is used for miscellaneous IP-like checksums, mainly + * in icmp.c + */ + +static __inline__ unsigned short ip_compute_csum(unsigned char * buff, int len) +{ + return csum_fold (csum_partial(buff, len, 0)); +} + +#define _HAVE_ARCH_IPV6_CSUM +static __inline__ unsigned short int csum_ipv6_magic(struct in6_addr *saddr, + struct in6_addr *daddr, + __u32 len, + unsigned short proto, + unsigned int sum) +{ + unsigned int __dummy; + __asm__("clrt\n\t" + "mov.l @(0,%2), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(4,%2), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(8,%2), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(12,%2), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(0,%3), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(4,%3), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(8,%3), %1\n\t" + "addc %1, %0\n\t" + "mov.l @(12,%3), %1\n\t" + "addc %1, %0\n\t" + "addc %4, %0\n\t" + "addc %5, %0\n\t" + "movt %1\n\t" + "add %1, %0\n" + : "=r" (sum), "=&r" (__dummy) + : "r" (saddr), "r" (daddr), + "r" (htonl(len)), "r" (htonl(proto)), "0" (sum) + : "t"); + + return csum_fold(sum); +} + +/* + * Copy and checksum to user + */ +#define HAVE_CSUM_COPY_USER +static __inline__ unsigned int csum_and_copy_to_user (const unsigned char *src, + unsigned char __user *dst, + int len, int sum, + int *err_ptr) +{ + if (access_ok(VERIFY_WRITE, dst, len)) + return csum_partial_copy_generic(src, dst, len, sum, NULL, err_ptr); + + if (len) + *err_ptr = -EFAULT; + + return -1; /* invalid checksum */ +} +#endif /* __ASM_SH_CHECKSUM_H */ diff --git a/include/asm-sh/cpu-sh2/addrspace.h b/include/asm-sh/cpu-sh2/addrspace.h new file mode 100644 index 0000000..8706c90 --- /dev/null +++ b/include/asm-sh/cpu-sh2/addrspace.h @@ -0,0 +1,16 @@ +/* + * Definitions for the address spaces of the SH-2 CPUs. + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_ADDRSPACE_H +#define __ASM_CPU_SH2_ADDRSPACE_H + +/* Should fill here */ + +#endif /* __ASM_CPU_SH2_ADDRSPACE_H */ + diff --git a/include/asm-sh/cpu-sh2/cache.h b/include/asm-sh/cpu-sh2/cache.h new file mode 100644 index 0000000..cd96402 --- /dev/null +++ b/include/asm-sh/cpu-sh2/cache.h @@ -0,0 +1,31 @@ +/* + * include/asm-sh/cpu-sh2/cache.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_CACHE_H +#define __ASM_CPU_SH2_CACHE_H + +#define L1_CACHE_SHIFT 4 + +#define CCR 0xfffffe92 /* Address of Cache Control Register */ + +#define CCR_CACHE_CE 0x01 /* Cache enable */ +#define CCR_CACHE_ID 0x02 /* Instruction Replacement disable */ +#define CCR_CACHE_OD 0x04 /* Data Replacement disable */ +#define CCR_CACHE_TW 0x08 /* Two-way mode */ +#define CCR_CACHE_CP 0x10 /* Cache purge */ + +#define CACHE_OC_ADDRESS_ARRAY 0x60000000 + +#define CCR_CACHE_ENABLE CCR_CACHE_CE +#define CCR_CACHE_INVALIDATE CCR_CACHE_CP +#define CCR_CACHE_ORA CCR_CACHE_TW +#define CCR_CACHE_WT 0x00 /* SH-2 is _always_ write-through */ + +#endif /* __ASM_CPU_SH2_CACHE_H */ + diff --git a/include/asm-sh/cpu-sh2/cacheflush.h b/include/asm-sh/cpu-sh2/cacheflush.h new file mode 100644 index 0000000..f556fa8 --- /dev/null +++ b/include/asm-sh/cpu-sh2/cacheflush.h @@ -0,0 +1,42 @@ +/* + * include/asm-sh/cpu-sh2/cacheflush.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_CACHEFLUSH_H +#define __ASM_CPU_SH2_CACHEFLUSH_H + +/* + * Cache flushing: + * + * - flush_cache_all() flushes entire cache + * - flush_cache_mm(mm) flushes the specified mm context's cache lines + * - flush_cache_page(mm, vmaddr, pfn) flushes a single page + * - flush_cache_range(vma, start, end) flushes a range of pages + * + * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache + * - flush_icache_range(start, end) flushes(invalidates) a range for icache + * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache + * + * Caches are indexed (effectively) by physical address on SH-2, so + * we don't need them. + */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_sigtramp(vaddr) do { } while (0) + +#define p3_cache_init() do { } while (0) +#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */ + diff --git a/include/asm-sh/cpu-sh2/dma.h b/include/asm-sh/cpu-sh2/dma.h new file mode 100644 index 0000000..d66b43c --- /dev/null +++ b/include/asm-sh/cpu-sh2/dma.h @@ -0,0 +1,23 @@ +/* + * Definitions for the SH-2 DMAC. + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_DMA_H +#define __ASM_CPU_SH2_DMA_H + +#define SH_MAX_DMA_CHANNELS 2 + +#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 }) +#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 }) +#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 }) +#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c }) + +#define DMAOR 0xffffffb0 + +#endif /* __ASM_CPU_SH2_DMA_H */ + diff --git a/include/asm-sh/cpu-sh2/shmparam.h b/include/asm-sh/cpu-sh2/shmparam.h new file mode 100644 index 0000000..817c182 --- /dev/null +++ b/include/asm-sh/cpu-sh2/shmparam.h @@ -0,0 +1,16 @@ +/* + * include/asm-sh/cpu-sh2/shmparam.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_SHMPARAM_H +#define __ASM_CPU_SH2_SHMPARAM_H + +#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ + +#endif /* __ASM_CPU_SH2_SHMPARAM_H */ + diff --git a/include/asm-sh/cpu-sh2/sigcontext.h b/include/asm-sh/cpu-sh2/sigcontext.h new file mode 100644 index 0000000..fe5c15d --- /dev/null +++ b/include/asm-sh/cpu-sh2/sigcontext.h @@ -0,0 +1,17 @@ +#ifndef __ASM_CPU_SH2_SIGCONTEXT_H +#define __ASM_CPU_SH2_SIGCONTEXT_H + +struct sigcontext { + unsigned long oldmask; + + /* CPU registers */ + unsigned long sc_regs[16]; + unsigned long sc_pc; + unsigned long sc_pr; + unsigned long sc_sr; + unsigned long sc_gbr; + unsigned long sc_mach; + unsigned long sc_macl; +}; + +#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */ diff --git a/include/asm-sh/cpu-sh2/ubc.h b/include/asm-sh/cpu-sh2/ubc.h new file mode 100644 index 0000000..ba0e87f --- /dev/null +++ b/include/asm-sh/cpu-sh2/ubc.h @@ -0,0 +1,32 @@ +/* + * include/asm-sh/cpu-sh2/ubc.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_UBC_H +#define __ASM_CPU_SH2_UBC_H + +#define UBC_BARA 0xffffff40 +#define UBC_BAMRA 0xffffff44 +#define UBC_BBRA 0xffffff48 +#define UBC_BARB 0xffffff60 +#define UBC_BAMRB 0xffffff64 +#define UBC_BBRB 0xffffff68 +#define UBC_BDRB 0xffffff70 +#define UBC_BDMRB 0xffffff74 +#define UBC_BRCR 0xffffff78 + +/* + * We don't have any ASID changes to make in the UBC on the SH-2. + * + * Make these purposely invalid to track misuse. + */ +#define UBC_BASRA 0x00000000 +#define UBC_BASRB 0x00000000 + +#endif /* __ASM_CPU_SH2_UBC_H */ + diff --git a/include/asm-sh/cpu-sh2/watchdog.h b/include/asm-sh/cpu-sh2/watchdog.h new file mode 100644 index 0000000..393161c --- /dev/null +++ b/include/asm-sh/cpu-sh2/watchdog.h @@ -0,0 +1,69 @@ +/* + * include/asm-sh/cpu-sh2/watchdog.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH2_WATCHDOG_H +#define __ASM_CPU_SH2_WATCHDOG_H + +/* + * More SH-2 brilliance .. its not good enough that we can't read + * and write the same sizes to WTCNT, now we have to read and write + * with different sizes at different addresses for WTCNT _and_ RSTCSR. + * + * At least on the bright side no one has managed to screw over WTCSR + * in this fashion .. yet. + */ +/* Register definitions */ +#define WTCNT 0xfffffe80 +#define WTCSR 0xfffffe80 +#define RSTCSR 0xfffffe82 + +#define WTCNT_R (WTCNT + 1) +#define RSTCSR_R (RSTCSR + 1) + +/* Bit definitions */ +#define WTCSR_IOVF 0x80 +#define WTCSR_WT 0x40 +#define WTCSR_TME 0x20 +#define WTCSR_RSTS 0x00 + +#define RSTCSR_RSTS 0x20 + +/** + * sh_wdt_read_rstcsr - Read from Reset Control/Status Register + * + * Reads back the RSTCSR value. + */ +static inline __u8 sh_wdt_read_rstcsr(void) +{ + /* + * Same read/write brain-damage as for WTCNT here.. + */ + return ctrl_inb(RSTCSR_R); +} + +/** + * sh_wdt_write_csr - Write to Reset Control/Status Register + * + * @val: Value to write + * + * Writes the given value @val to the lower byte of the control/status + * register. The upper byte is set manually on each write. + */ +static inline void sh_wdt_write_rstcsr(__u8 val) +{ + /* + * Note: Due to the brain-damaged nature of this register, + * we can't presently touch the WOVF bit, since the upper byte + * has to be swapped for this. So just leave it alone.. + */ + ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); +} + +#endif /* __ASM_CPU_SH2_WATCHDOG_H */ + diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h new file mode 100644 index 0000000..b289e3c --- /dev/null +++ b/include/asm-sh/cpu-sh3/adc.h @@ -0,0 +1,28 @@ +#ifndef __ASM_CPU_SH3_ADC_H +#define __ASM_CPU_SH3_ADC_H + +/* + * Copyright (C) 2004 Andriy Skulysh + */ + + +#define ADDRAH 0xa4000080 +#define ADDRAL 0xa4000082 +#define ADDRBH 0xa4000084 +#define ADDRBL 0xa4000086 +#define ADDRCH 0xa4000088 +#define ADDRCL 0xa400008a +#define ADDRDH 0xa400008c +#define ADDRDL 0xa400008e +#define ADCSR 0xa4000090 + +#define ADCSR_ADF 0x80 +#define ADCSR_ADIE 0x40 +#define ADCSR_ADST 0x20 +#define ADCSR_MULTI 0x10 +#define ADCSR_CKS 0x08 +#define ADCSR_CH_MASK 0x07 + +#define ADCR 0xa4000092 + +#endif /* __ASM_CPU_SH3_ADC_H */ diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h new file mode 100644 index 0000000..872e9e1 --- /dev/null +++ b/include/asm-sh/cpu-sh3/addrspace.h @@ -0,0 +1,16 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima + * + * Defitions for the address spaces of the SH-3 CPUs. + */ +#ifndef __ASM_CPU_SH3_ADDRSPACE_H +#define __ASM_CPU_SH3_ADDRSPACE_H + +/* Should fill here */ + +#endif /* __ASM_CPU_SH3_ADDRSPACE_H */ + diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h new file mode 100644 index 0000000..406aa8d --- /dev/null +++ b/include/asm-sh/cpu-sh3/cache.h @@ -0,0 +1,37 @@ +/* + * include/asm-sh/cpu-sh3/cache.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_CACHE_H +#define __ASM_CPU_SH3_CACHE_H + +#define L1_CACHE_SHIFT 4 + +#define CCR 0xffffffec /* Address of Cache Control Register */ + +#define CCR_CACHE_CE 0x01 /* Cache Enable */ +#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */ +#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */ +#define CCR_CACHE_CF 0x08 /* Cache Flush */ +#define CCR_CACHE_ORA 0x20 /* RAM mode */ + +#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_PHYSADDR_MASK 0x1ffffc00 + +#define CCR_CACHE_ENABLE CCR_CACHE_CE +#define CCR_CACHE_INVALIDATE CCR_CACHE_CF + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define CCR3 0xa40000b4 +#define CCR_CACHE_16KB 0x00010000 +#define CCR_CACHE_32KB 0x00020000 +#endif + + +#endif /* __ASM_CPU_SH3_CACHE_H */ + diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h new file mode 100644 index 0000000..f51aed0 --- /dev/null +++ b/include/asm-sh/cpu-sh3/cacheflush.h @@ -0,0 +1,87 @@ +/* + * include/asm-sh/cpu-sh3/cacheflush.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_CACHEFLUSH_H +#define __ASM_CPU_SH3_CACHEFLUSH_H + +/* + * Cache flushing: + * + * - flush_cache_all() flushes entire cache + * - flush_cache_mm(mm) flushes the specified mm context's cache lines + * - flush_cache_page(mm, vmaddr, pfn) flushes a single page + * - flush_cache_range(vma, start, end) flushes a range of pages + * + * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache + * - flush_icache_range(start, end) flushes(invalidates) a range for icache + * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache + * + * Caches are indexed (effectively) by physical address on SH-3, so + * we don't need them. + */ + +#if defined(CONFIG_SH7705_CACHE_32KB) + +/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the + * SH4. Unlike the SH4 this is a unified cache so we need to do some work + * in mmap when 'exec'ing a new binary + */ + /* 32KB cache, 4kb PAGE sizes need to check bit 12 */ +#define CACHE_ALIAS 0x00001000 + +struct page; +struct mm_struct; +struct vm_area_struct; + +extern void flush_cache_all(void); +extern void flush_cache_mm(struct mm_struct *mm); +extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn); +extern void flush_dcache_page(struct page *pg); +extern void flush_icache_range(unsigned long start, unsigned long end); +extern void flush_icache_page(struct vm_area_struct *vma, struct page *page); + +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) + +/* SH3 has unified cache so no special action needed here */ +#define flush_cache_sigtramp(vaddr) do { } while (0) +#define flush_page_to_ram(page) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) + +#define p3_cache_init() do { } while (0) + +#define PG_mapped PG_arch_1 + +/* We provide our own get_unmapped_area to avoid cache alias issue */ +#define HAVE_ARCH_UNMAPPED_AREA + +#else + +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +#define flush_icache_range(start, end) do { } while (0) +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_sigtramp(vaddr) do { } while (0) + +#define p3_cache_init() do { } while (0) + +#define HAVE_ARCH_UNMAPPED_AREA + +#endif + +#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */ + diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h new file mode 100644 index 0000000..05fda83 --- /dev/null +++ b/include/asm-sh/cpu-sh3/dac.h @@ -0,0 +1,41 @@ +#ifndef __ASM_CPU_SH3_DAC_H +#define __ASM_CPU_SH3_DAC_H + +/* + * Copyright (C) 2003 Andriy Skulysh + */ + + +#define DADR0 0xa40000a0 +#define DADR1 0xa40000a2 +#define DACR 0xa40000a4 +#define DACR_DAOE1 0x80 +#define DACR_DAOE0 0x40 +#define DACR_DAE 0x20 + + +static __inline__ void sh_dac_enable(int channel) +{ + unsigned char v; + v = ctrl_inb(DACR); + if(channel) v |= DACR_DAOE1; + else v |= DACR_DAOE0; + ctrl_outb(v,DACR); +} + +static __inline__ void sh_dac_disable(int channel) +{ + unsigned char v; + v = ctrl_inb(DACR); + if(channel) v &= ~DACR_DAOE1; + else v &= ~DACR_DAOE0; + ctrl_outb(v,DACR); +} + +static __inline__ void sh_dac_output(u8 value, int channel) +{ + if(channel) ctrl_outb(value,DADR1); + else ctrl_outb(value,DADR0); +} + +#endif /* __ASM_CPU_SH3_DAC_H */ diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h new file mode 100644 index 0000000..b972e71 --- /dev/null +++ b/include/asm-sh/cpu-sh3/dma.h @@ -0,0 +1,7 @@ +#ifndef __ASM_CPU_SH3_DMA_H +#define __ASM_CPU_SH3_DMA_H + +#define SH_DMAC_BASE 0xa4000020 + +#endif /* __ASM_CPU_SH3_DMA_H */ + diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h new file mode 100644 index 0000000..b61b6e3 --- /dev/null +++ b/include/asm-sh/cpu-sh3/freq.h @@ -0,0 +1,22 @@ +/* + * include/asm-sh/cpu-sh3/freq.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_FREQ_H +#define __ASM_CPU_SH3_FREQ_H + +#if defined(CONFIG_CPU_SUBTYPE_SH7300) +#define FRQCR 0xa415ff80 +#else +#define FRQCR 0xffffff80 +#endif +#define MIN_DIVISOR_NR 0 +#define MAX_DIVISOR_NR 4 + +#endif /* __ASM_CPU_SH3_FREQ_H */ + diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h new file mode 100644 index 0000000..5cfaa6b --- /dev/null +++ b/include/asm-sh/cpu-sh3/mmu_context.h @@ -0,0 +1,28 @@ +/* + * include/asm-sh/cpu-sh3/mmu_context.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H +#define __ASM_CPU_SH3_MMU_CONTEXT_H + +#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */ +#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */ +#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */ +#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ + +#define MMUCR 0xFFFFFFE0 /* MMU Control Register */ + +#define MMU_TLB_ADDRESS_ARRAY 0xF2000000 +#define MMU_PAGE_ASSOC_BIT 0x80 + +#define MMU_NTLB_ENTRIES 128 /* for 7708 */ +#define MMU_NTLB_WAYS 4 +#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ + +#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ + diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h new file mode 100644 index 0000000..2d92667 --- /dev/null +++ b/include/asm-sh/cpu-sh3/rtc.h @@ -0,0 +1,25 @@ +#ifndef __ASM_CPU_SH3_RTC_H +#define __ASM_CPU_SH3_RTC_H + +/* SH-3 RTC */ +#define R64CNT 0xfffffec0 +#define RSECCNT 0xfffffec2 +#define RMINCNT 0xfffffec4 +#define RHRCNT 0xfffffec6 +#define RWKCNT 0xfffffec8 +#define RDAYCNT 0xfffffeca +#define RMONCNT 0xfffffecc +#define RYRCNT 0xfffffece +#define RSECAR 0xfffffed0 +#define RMINAR 0xfffffed2 +#define RHRAR 0xfffffed4 +#define RWKAR 0xfffffed6 +#define RDAYAR 0xfffffed8 +#define RMONAR 0xfffffeda +#define RCR1 0xfffffedc +#define RCR2 0xfffffede + +#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */ + +#endif /* __ASM_CPU_SH3_RTC_H */ + diff --git a/include/asm-sh/cpu-sh3/shmparam.h b/include/asm-sh/cpu-sh3/shmparam.h new file mode 100644 index 0000000..da5b5ee --- /dev/null +++ b/include/asm-sh/cpu-sh3/shmparam.h @@ -0,0 +1,16 @@ +/* + * include/asm-sh/cpu-sh3/shmparam.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_SHMPARAM_H +#define __ASM_CPU_SH3_SHMPARAM_H + +#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */ + +#endif /* __ASM_CPU_SH3_SHMPARAM_H */ + diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h new file mode 100644 index 0000000..17310dc --- /dev/null +++ b/include/asm-sh/cpu-sh3/sigcontext.h @@ -0,0 +1,17 @@ +#ifndef __ASM_CPU_SH3_SIGCONTEXT_H +#define __ASM_CPU_SH3_SIGCONTEXT_H + +struct sigcontext { + unsigned long oldmask; + + /* CPU registers */ + unsigned long sc_regs[16]; + unsigned long sc_pc; + unsigned long sc_pr; + unsigned long sc_sr; + unsigned long sc_gbr; + unsigned long sc_mach; + unsigned long sc_macl; +}; + +#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */ diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h new file mode 100644 index 0000000..3d8e95e --- /dev/null +++ b/include/asm-sh/cpu-sh3/timer.h @@ -0,0 +1,64 @@ +/* + * include/asm-sh/cpu-sh3/timer.h + * + * Copyright (C) 2004 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_TIMER_H +#define __ASM_CPU_SH3_TIMER_H + +/* + * --------------------------------------------------------------------------- + * TMU Common definitions for SH3 processors + * SH7706 + * SH7709S + * SH7727 + * SH7729R + * SH7710 + * SH7720 + * SH7300 + * --------------------------------------------------------------------------- + */ + +#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) +#define TMU_TSTR 0xa412fe92 /* Byte access */ + +#define TMU0_TCOR 0xa412fe94 /* Long access */ +#define TMU0_TCNT 0xa412fe98 /* Long access */ +#define TMU0_TCR 0xa412fe9c /* Word access */ + +#define TMU1_TCOR 0xa412fea0 /* Long access */ +#define TMU1_TCNT 0xa412fea4 /* Long access */ +#define TMU1_TCR 0xa412fea8 /* Word access */ + +#define TMU2_TCOR 0xa412feac /* Long access */ +#define TMU2_TCNT 0xa412feb0 /* Long access */ +#define TMU2_TCR 0xa412feb4 /* Word access */ + +#else +#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#define TMU_TOCR 0xfffffe90 /* Byte access */ +#endif +#define TMU_TSTR 0xfffffe92 /* Byte access */ + +#define TMU0_TCOR 0xfffffe94 /* Long access */ +#define TMU0_TCNT 0xfffffe98 /* Long access */ +#define TMU0_TCR 0xfffffe9c /* Word access */ + +#define TMU1_TCOR 0xfffffea0 /* Long access */ +#define TMU1_TCNT 0xfffffea4 /* Long access */ +#define TMU1_TCR 0xfffffea8 /* Word access */ + +#define TMU2_TCOR 0xfffffeac /* Long access */ +#define TMU2_TCNT 0xfffffeb0 /* Long access */ +#define TMU2_TCR 0xfffffeb4 /* Word access */ +#if !defined(CONFIG_CPU_SUBTYPE_SH7727) +#define TMU2_TCPR2 0xfffffeb8 /* Long access */ +#endif +#endif + +#endif /* __ASM_CPU_SH3_TIMER_H */ + diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h new file mode 100644 index 0000000..0f809de --- /dev/null +++ b/include/asm-sh/cpu-sh3/ubc.h @@ -0,0 +1,27 @@ +/* + * include/asm-sh/cpu-sh3/ubc.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_UBC_H +#define __ASM_CPU_SH3_UBC_H + +#define UBC_BARA 0xffffffb0 +#define UBC_BAMRA 0xffffffb4 +#define UBC_BBRA 0xffffffb8 +#define UBC_BASRA 0xffffffe4 +#define UBC_BARB 0xffffffa0 +#define UBC_BAMRB 0xffffffa4 +#define UBC_BBRB 0xffffffa8 +#define UBC_BASRB 0xffffffe8 +#define UBC_BDRB 0xffffff90 +#define UBC_BDMRB 0xffffff94 +#define UBC_BRCR 0xffffff98 + +#endif /* __ASM_CPU_SH3_UBC_H */ + diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h new file mode 100644 index 0000000..4ee0347 --- /dev/null +++ b/include/asm-sh/cpu-sh3/watchdog.h @@ -0,0 +1,25 @@ +/* + * include/asm-sh/cpu-sh3/watchdog.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH3_WATCHDOG_H +#define __ASM_CPU_SH3_WATCHDOG_H + +/* Register definitions */ +#define WTCNT 0xffffff84 +#define WTCSR 0xffffff86 + +/* Bit definitions */ +#define WTCSR_TME 0x80 +#define WTCSR_WT 0x40 +#define WTCSR_RSTS 0x20 +#define WTCSR_WOVF 0x10 +#define WTCSR_IOVF 0x08 + +#endif /* __ASM_CPU_SH3_WATCHDOG_H */ + diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h new file mode 100644 index 0000000..727634d --- /dev/null +++ b/include/asm-sh/cpu-sh4/addrspace.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1999 by Kaz Kojima + * + * Defitions for the address spaces of the SH-4 CPUs. + */ +#ifndef __ASM_CPU_SH4_ADDRSPACE_H +#define __ASM_CPU_SH4_ADDRSPACE_H + +/* Detailed P4SEG */ +#define P4SEG_STORE_QUE (P4SEG) +#define P4SEG_IC_ADDR 0xf0000000 +#define P4SEG_IC_DATA 0xf1000000 +#define P4SEG_ITLB_ADDR 0xf2000000 +#define P4SEG_ITLB_DATA 0xf3000000 +#define P4SEG_OC_ADDR 0xf4000000 +#define P4SEG_OC_DATA 0xf5000000 +#define P4SEG_TLB_ADDR 0xf6000000 +#define P4SEG_TLB_DATA 0xf7000000 +#define P4SEG_REG_BASE 0xff000000 + +#endif /* __ASM_CPU_SH4_ADDRSPACE_H */ + diff --git a/include/asm-sh/cpu-sh4/cache.h b/include/asm-sh/cpu-sh4/cache.h new file mode 100644 index 0000000..1fe2035 --- /dev/null +++ b/include/asm-sh/cpu-sh4/cache.h @@ -0,0 +1,35 @@ +/* + * include/asm-sh/cpu-sh4/cache.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_CACHE_H +#define __ASM_CPU_SH4_CACHE_H + +#define L1_CACHE_SHIFT 5 + +#define CCR 0xff00001c /* Address of Cache Control Register */ +#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */ +#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/ +#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */ +#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */ +#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */ +#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */ +#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */ +#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */ +#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */ +#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */ + +/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */ +#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE) +#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI) + +#define CACHE_IC_ADDRESS_ARRAY 0xf0000000 +#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 + +#endif /* __ASM_CPU_SH4_CACHE_H */ + diff --git a/include/asm-sh/cpu-sh4/cacheflush.h b/include/asm-sh/cpu-sh4/cacheflush.h new file mode 100644 index 0000000..f323567 --- /dev/null +++ b/include/asm-sh/cpu-sh4/cacheflush.h @@ -0,0 +1,64 @@ +/* + * include/asm-sh/cpu-sh4/cacheflush.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_CACHEFLUSH_H +#define __ASM_CPU_SH4_CACHEFLUSH_H + +/* + * Caches are broken on SH-4 (unless we use write-through + * caching; in which case they're only semi-broken), + * so we need them. + */ + +/* Page is 4K, OC size is 16K, there are four lines. */ +#define CACHE_ALIAS 0x00003000 + +struct page; +struct mm_struct; +struct vm_area_struct; + +extern void flush_cache_all(void); +extern void flush_cache_mm(struct mm_struct *mm); +extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn); +extern void flush_dcache_page(struct page *pg); + +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) + +extern void flush_icache_range(unsigned long start, unsigned long end); +extern void flush_cache_sigtramp(unsigned long addr); +extern void flush_icache_user_range(struct vm_area_struct *vma, + struct page *page, unsigned long addr, + int len); + +#define flush_icache_page(vma,pg) do { } while (0) + +/* Initialization of P3 area for copy_user_page */ +extern void p3_cache_init(void); + +#define PG_mapped PG_arch_1 + +/* We provide our own get_unmapped_area to avoid cache alias issue */ +#define HAVE_ARCH_UNMAPPED_AREA + +#ifdef CONFIG_MMU +extern int remap_area_pages(unsigned long addr, unsigned long phys_addr, + unsigned long size, unsigned long flags); +#else /* CONFIG_MMU */ +static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr, + unsigned long size, unsigned long flags) +{ + return 0; +} +#endif /* CONFIG_MMU */ +#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */ + diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h new file mode 100644 index 0000000..e2b91ad --- /dev/null +++ b/include/asm-sh/cpu-sh4/dma.h @@ -0,0 +1,17 @@ +#ifndef __ASM_CPU_SH4_DMA_H +#define __ASM_CPU_SH4_DMA_H + +#define SH_DMAC_BASE 0xffa00000 + +#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \ + SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30}) +#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \ + SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34}) +#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \ + SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38}) +#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \ + SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c}) +#define DMAOR (SH_DMAC_BASE + 0x40) + +#endif /* __ASM_CPU_SH4_DMA_H */ + diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h new file mode 100644 index 0000000..201d94f --- /dev/null +++ b/include/asm-sh/cpu-sh4/freq.h @@ -0,0 +1,22 @@ +/* + * include/asm-sh/cpu-sh4/freq.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_FREQ_H +#define __ASM_CPU_SH4_FREQ_H + +#if defined(CONFIG_CPU_SUBTYPE_SH73180) +#define FRQCR 0xa4150000 +#else +#define FRQCR 0xffc00000 +#endif +#define MIN_DIVISOR_NR 0 +#define MAX_DIVISOR_NR 3 + +#endif /* __ASM_CPU_SH4_FREQ_H */ + diff --git a/include/asm-sh/cpu-sh4/mmu_context.h b/include/asm-sh/cpu-sh4/mmu_context.h new file mode 100644 index 0000000..5b64d04 --- /dev/null +++ b/include/asm-sh/cpu-sh4/mmu_context.h @@ -0,0 +1,39 @@ +/* + * include/asm-sh/cpu-sh4/mmu_context.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H +#define __ASM_CPU_SH4_MMU_CONTEXT_H + +#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ +#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ +#define MMU_TTB 0xFF000008 /* Translation table base register */ +#define MMU_TEA 0xFF00000C /* TLB Exception Address */ +#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */ + +#define MMUCR 0xFF000010 /* MMU Control Register */ + +#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 +#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 +#define MMU_PAGE_ASSOC_BIT 0x80 + +#define MMU_NTLB_ENTRIES 64 /* for 7750 */ +#define MMU_CONTROL_INIT 0x205 /* SQMD=1, SV=0, TI=1, AT=1 */ + +#define MMU_ITLB_DATA_ARRAY 0xF3000000 +#define MMU_UTLB_DATA_ARRAY 0xF7000000 + +#define MMU_UTLB_ENTRIES 64 +#define MMU_U_ENTRY_SHIFT 8 +#define MMU_UTLB_VALID 0x100 +#define MMU_ITLB_ENTRIES 4 +#define MMU_I_ENTRY_SHIFT 8 +#define MMU_ITLB_VALID 0x100 + +#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ + diff --git a/include/asm-sh/cpu-sh4/rtc.h b/include/asm-sh/cpu-sh4/rtc.h new file mode 100644 index 0000000..e091e32 --- /dev/null +++ b/include/asm-sh/cpu-sh4/rtc.h @@ -0,0 +1,25 @@ +#ifndef __ASM_CPU_SH4_RTC_H +#define __ASM_CPU_SH4_RTC_H + +/* SH-4 RTC */ +#define R64CNT 0xffc80000 +#define RSECCNT 0xffc80004 +#define RMINCNT 0xffc80008 +#define RHRCNT 0xffc8000c +#define RWKCNT 0xffc80010 +#define RDAYCNT 0xffc80014 +#define RMONCNT 0xffc80018 +#define RYRCNT 0xffc8001c /* 16bit */ +#define RSECAR 0xffc80020 +#define RMINAR 0xffc80024 +#define RHRAR 0xffc80028 +#define RWKAR 0xffc8002c +#define RDAYAR 0xffc80030 +#define RMONAR 0xffc80034 +#define RCR1 0xffc80038 +#define RCR2 0xffc8003c + +#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */ + +#endif /* __ASM_CPU_SH4_RTC_H */ + diff --git a/include/asm-sh/cpu-sh4/shmparam.h b/include/asm-sh/cpu-sh4/shmparam.h new file mode 100644 index 0000000..a5a0aa9 --- /dev/null +++ b/include/asm-sh/cpu-sh4/shmparam.h @@ -0,0 +1,19 @@ +/* + * include/asm-sh/cpu-sh4/shmparam.h + * + * Copyright (C) 1999 Niibe Yutaka + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_SHMPARAM_H +#define __ASM_CPU_SH4_SHMPARAM_H + +/* + * SH-4 has D-cache alias issue + */ +#define SHMLBA (PAGE_SIZE*4) /* attach addr a multiple of this */ + +#endif /* __ASM_CPU_SH4_SHMPARAM_H */ + diff --git a/include/asm-sh/cpu-sh4/sigcontext.h b/include/asm-sh/cpu-sh4/sigcontext.h new file mode 100644 index 0000000..ab392f1 --- /dev/null +++ b/include/asm-sh/cpu-sh4/sigcontext.h @@ -0,0 +1,24 @@ +#ifndef __ASM_CPU_SH4_SIGCONTEXT_H +#define __ASM_CPU_SH4_SIGCONTEXT_H + +struct sigcontext { + unsigned long oldmask; + + /* CPU registers */ + unsigned long sc_regs[16]; + unsigned long sc_pc; + unsigned long sc_pr; + unsigned long sc_sr; + unsigned long sc_gbr; + unsigned long sc_mach; + unsigned long sc_macl; + + /* FPU registers */ + unsigned long sc_fpregs[16]; + unsigned long sc_xfpregs[16]; + unsigned int sc_fpscr; + unsigned int sc_fpul; + unsigned int sc_ownedfp; +}; + +#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */ diff --git a/include/asm-sh/cpu-sh4/sq.h b/include/asm-sh/cpu-sh4/sq.h new file mode 100644 index 0000000..366b091 --- /dev/null +++ b/include/asm-sh/cpu-sh4/sq.h @@ -0,0 +1,48 @@ +/* + * include/asm-sh/cpu-sh4/sq.h + * + * Copyright (C) 2001, 2002, 2003 Paul Mundt + * Copyright (C) 2001, 2002 M. R. Brown + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_SQ_H +#define __ASM_CPU_SH4_SQ_H + +#include <asm/addrspace.h> + +/* + * Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be + * mapped to any physical address space. Since data is written (and aligned) + * to 32-byte boundaries, we need to be sure that all allocations are aligned. + */ +#define SQ_SIZE 32 +#define SQ_ALIGN_MASK (~(SQ_SIZE - 1)) +#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK) + +#define SQ_QACR0 (P4SEG_REG_BASE + 0x38) +#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c) +#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000) + +struct sq_mapping { + const char *name; + + unsigned long sq_addr; + unsigned long addr; + unsigned int size; + + struct list_head list; +}; + +/* arch/sh/kernel/cpu/sh4/sq.c */ +extern struct sq_mapping *sq_remap(unsigned long phys, unsigned int size, const char *name); +extern void sq_unmap(struct sq_mapping *map); + +extern void sq_clear(unsigned long addr, unsigned int len); +extern void sq_flush(void *addr); +extern void sq_flush_range(unsigned long start, unsigned int len); + +#endif /* __ASM_CPU_SH4_SQ_H */ + diff --git a/include/asm-sh/cpu-sh4/timer.h b/include/asm-sh/cpu-sh4/timer.h new file mode 100644 index 0000000..8a4af126c --- /dev/null +++ b/include/asm-sh/cpu-sh4/timer.h @@ -0,0 +1,51 @@ +/* + * include/asm-sh/cpu-sh4/timer.h + * + * Copyright (C) 2004 Lineo Solutions, Inc. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_TIMER_H +#define __ASM_CPU_SH4_TIMER_H + +/* + * --------------------------------------------------------------------------- + * TMU Common definitions for SH4 processors + * SH7750S/SH7750R + * SH7751/SH7751R + * SH7760 + * --------------------------------------------------------------------------- + */ + +#if !defined(CONFIG_CPU_SUBTYPE_SH7760) +#define TMU_TOCR 0xffd80000 /* Byte access */ +#endif +#define TMU_TSTR 0xffd80004 /* Byte access */ + +#define TMU0_TCOR 0xffd80008 /* Long access */ +#define TMU0_TCNT 0xffd8000c /* Long access */ +#define TMU0_TCR 0xffd80010 /* Word access */ + +#define TMU1_TCOR 0xffd80014 /* Long access */ +#define TMU1_TCNT 0xffd80018 /* Long access */ +#define TMU1_TCR 0xffd8001c /* Word access */ + +#define TMU2_TCOR 0xffd80020 /* Long access */ +#define TMU2_TCNT 0xffd80024 /* Long access */ +#define TMU2_TCR 0xffd80028 /* Word access */ +#define TMU2_TCPR 0xffd8002c /* Long access */ + +#if !defined(CONFIG_CPU_SUBTYPE_SH7760) +#define TMU3_TCOR 0xfe100008 /* Long access */ +#define TMU3_TCNT 0xfe10000c /* Long access */ +#define TMU3_TCR 0xfe100010 /* Word access */ + +#define TMU4_TCOR 0xfe100014 /* Long access */ +#define TMU4_TCNT 0xfe100018 /* Long access */ +#define TMU4_TCR 0xfe10001c /* Word access */ +#endif + +#endif /* __ASM_CPU_SH4_TIMER_H */ + diff --git a/include/asm-sh/cpu-sh4/ubc.h b/include/asm-sh/cpu-sh4/ubc.h new file mode 100644 index 0000000..3d09431 --- /dev/null +++ b/include/asm-sh/cpu-sh4/ubc.h @@ -0,0 +1,27 @@ +/* + * include/asm-sh/cpu-sh4/ubc.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_UBC_H +#define __ASM_CPU_SH4_UBC_H + +#define UBC_BARA 0xff200000 +#define UBC_BAMRA 0xff200004 +#define UBC_BBRA 0xff200008 +#define UBC_BASRA 0xff000014 +#define UBC_BARB 0xff20000c +#define UBC_BAMRB 0xff200010 +#define UBC_BBRB 0xff200014 +#define UBC_BASRB 0xff000018 +#define UBC_BDRB 0xff200018 +#define UBC_BDMRB 0xff20001c +#define UBC_BRCR 0xff200020 + +#endif /* __ASM_CPU_SH4_UBC_H */ + diff --git a/include/asm-sh/cpu-sh4/watchdog.h b/include/asm-sh/cpu-sh4/watchdog.h new file mode 100644 index 0000000..259f6a0 --- /dev/null +++ b/include/asm-sh/cpu-sh4/watchdog.h @@ -0,0 +1,25 @@ +/* + * include/asm-sh/cpu-sh4/watchdog.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_CPU_SH4_WATCHDOG_H +#define __ASM_CPU_SH4_WATCHDOG_H + +/* Register definitions */ +#define WTCNT 0xffc00008 +#define WTCSR 0xffc0000c + +/* Bit definitions */ +#define WTCSR_TME 0x80 +#define WTCSR_WT 0x40 +#define WTCSR_RSTS 0x20 +#define WTCSR_WOVF 0x10 +#define WTCSR_IOVF 0x08 + +#endif /* __ASM_CPU_SH4_WATCHDOG_H */ + diff --git a/include/asm-sh/cputime.h b/include/asm-sh/cputime.h new file mode 100644 index 0000000..6ca395d --- /dev/null +++ b/include/asm-sh/cputime.h @@ -0,0 +1,6 @@ +#ifndef __SH_CPUTIME_H +#define __SH_CPUTIME_H + +#include <asm-generic/cputime.h> + +#endif /* __SH_CPUTIME_H */ diff --git a/include/asm-sh/cqreek/cqreek.h b/include/asm-sh/cqreek/cqreek.h new file mode 100644 index 0000000..09aecc0 --- /dev/null +++ b/include/asm-sh/cqreek/cqreek.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SH_CQREEK_CQREEK_H +#define __ASM_SH_CQREEK_CQREEK_H + +#define BRIDGE_FEATURE 0x0002 + +#define BRIDGE_IDE_CTRL 0x0018 +#define BRIDGE_IDE_INTR_LVL 0x001A +#define BRIDGE_IDE_INTR_MASK 0x001C +#define BRIDGE_IDE_INTR_STAT 0x001E + +#define BRIDGE_ISA_CTRL 0x0028 +#define BRIDGE_ISA_INTR_LVL 0x002A +#define BRIDGE_ISA_INTR_MASK 0x002C +#define BRIDGE_ISA_INTR_STAT 0x002E + +/* arch/sh/boards/cqreek/setup.c */ +extern void setup_cqreek(void); + +/* arch/sh/boards/cqreek/irq.c */ +extern int cqreek_has_ide, cqreek_has_isa; +extern void init_cqreek_IRQ(void); + +/* arch/sh/boards/cqreek/io.c */ +extern unsigned long cqreek_port2addr(unsigned long port); + +#endif /* __ASM_SH_CQREEK_CQREEK_H */ + diff --git a/include/asm-sh/current.h b/include/asm-sh/current.h new file mode 100644 index 0000000..62b6388 --- /dev/null +++ b/include/asm-sh/current.h @@ -0,0 +1,20 @@ +#ifndef __ASM_SH_CURRENT_H +#define __ASM_SH_CURRENT_H + +/* + * Copyright (C) 1999 Niibe Yutaka + * + */ + +#include <linux/thread_info.h> + +struct task_struct; + +static __inline__ struct task_struct * get_current(void) +{ + return current_thread_info()->task; +} + +#define current get_current() + +#endif /* __ASM_SH_CURRENT_H */ diff --git a/include/asm-sh/delay.h b/include/asm-sh/delay.h new file mode 100644 index 0000000..db599b2 --- /dev/null +++ b/include/asm-sh/delay.h @@ -0,0 +1,27 @@ +#ifndef __ASM_SH_DELAY_H +#define __ASM_SH_DELAY_H + +/* + * Copyright (C) 1993 Linus Torvalds + * + * Delay routines calling functions in arch/sh/lib/delay.c + */ + +extern void __bad_udelay(void); +extern void __bad_ndelay(void); + +extern void __udelay(unsigned long usecs); +extern void __ndelay(unsigned long nsecs); +extern void __const_udelay(unsigned long usecs); +extern void __delay(unsigned long loops); + +#define udelay(n) (__builtin_constant_p(n) ? \ + ((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \ + __udelay(n)) + + +#define ndelay(n) (__builtin_constant_p(n) ? \ + ((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \ + __ndelay(n)) + +#endif /* __ASM_SH_DELAY_H */ diff --git a/include/asm-sh/div64.h b/include/asm-sh/div64.h new file mode 100644 index 0000000..6cd978c --- /dev/null +++ b/include/asm-sh/div64.h @@ -0,0 +1 @@ +#include <asm-generic/div64.h> diff --git a/include/asm-sh/dma-mapping.h b/include/asm-sh/dma-mapping.h new file mode 100644 index 0000000..80d164c --- /dev/null +++ b/include/asm-sh/dma-mapping.h @@ -0,0 +1,179 @@ +#ifndef __ASM_SH_DMA_MAPPING_H +#define __ASM_SH_DMA_MAPPING_H + +#include <linux/config.h> +#include <linux/mm.h> +#include <asm/scatterlist.h> +#include <asm/io.h> + +extern struct bus_type pci_bus_type; + +/* arch/sh/mm/consistent.c */ +extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); +extern void consistent_free(void *vaddr, size_t size); +extern void consistent_sync(void *vaddr, size_t size, int direction); + +#define dma_supported(dev, mask) (1) + +static inline int dma_set_mask(struct device *dev, u64 mask) +{ + if (!dev->dma_mask || !dma_supported(dev, mask)) + return -EIO; + + *dev->dma_mask = mask; + + return 0; +} + +static inline void *dma_alloc_coherent(struct device *dev, size_t size, + dma_addr_t *dma_handle, int flag) +{ + if (sh_mv.mv_consistent_alloc) { + void *ret; + + ret = sh_mv.mv_consistent_alloc(dev, size, dma_handle, flag); + if (ret != NULL) + return ret; + } + + return consistent_alloc(flag, size, dma_handle); +} + +static inline void dma_free_coherent(struct device *dev, size_t size, + void *vaddr, dma_addr_t dma_handle) +{ + if (sh_mv.mv_consistent_free) { + int ret; + + ret = sh_mv.mv_consistent_free(dev, size, vaddr, dma_handle); + if (ret == 0) + return; + } + + consistent_free(vaddr, size); +} + +static inline void dma_cache_sync(void *vaddr, size_t size, + enum dma_data_direction dir) +{ + consistent_sync(vaddr, size, (int)dir); +} + +static inline dma_addr_t dma_map_single(struct device *dev, + void *ptr, size_t size, + enum dma_data_direction dir) +{ +#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return virt_to_bus(ptr); +#endif + dma_cache_sync(ptr, size, dir); + + return virt_to_bus(ptr); +} + +#define dma_unmap_single(dev, addr, size, dir) do { } while (0) + +static inline int dma_map_sg(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nents; i++) { +#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT) + dma_cache_sync(page_address(sg[i].page) + sg[i].offset, + sg[i].length, dir); +#endif + sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset; + } + + return nents; +} + +#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0) + +static inline dma_addr_t dma_map_page(struct device *dev, struct page *page, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ + return dma_map_single(dev, page_address(page) + offset, size, dir); +} + +static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address, + size_t size, enum dma_data_direction dir) +{ + dma_unmap_single(dev, dma_address, size, dir); +} + +static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle, + size_t size, enum dma_data_direction dir) +{ +#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return; +#endif + dma_cache_sync(bus_to_virt(dma_handle), size, dir); +} + +static inline void dma_sync_single_range(struct device *dev, + dma_addr_t dma_handle, + unsigned long offset, size_t size, + enum dma_data_direction dir) +{ +#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT) + if (dev->bus == &pci_bus_type) + return; +#endif + dma_cache_sync(bus_to_virt(dma_handle) + offset, size, dir); +} + +static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg, + int nelems, enum dma_data_direction dir) +{ + int i; + + for (i = 0; i < nelems; i++) { +#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT) + dma_cache_sync(page_address(sg[i].page) + sg[i].offset, + sg[i].length, dir); +#endif + sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset; + } +} + +static inline void dma_sync_single_for_cpu(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) + __attribute__ ((alias("dma_sync_single"))); + +static inline void dma_sync_single_for_device(struct device *dev, + dma_addr_t dma_handle, size_t size, + enum dma_data_direction dir) + __attribute__ ((alias("dma_sync_single"))); + +static inline void dma_sync_sg_for_cpu(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) + __attribute__ ((alias("dma_sync_sg"))); + +static inline void dma_sync_sg_for_device(struct device *dev, + struct scatterlist *sg, int nelems, + enum dma_data_direction dir) + __attribute__ ((alias("dma_sync_sg"))); + +static inline int dma_get_cache_alignment(void) +{ + /* + * Each processor family will define its own L1_CACHE_SHIFT, + * L1_CACHE_BYTES wraps to this, so this is always safe. + */ + return L1_CACHE_BYTES; +} + +static inline int dma_mapping_error(dma_addr_t dma_addr) +{ + return dma_addr == 0; +} + +#endif /* __ASM_SH_DMA_MAPPING_H */ + diff --git a/include/asm-sh/dma.h b/include/asm-sh/dma.h new file mode 100644 index 0000000..8e94360 --- /dev/null +++ b/include/asm-sh/dma.h @@ -0,0 +1,143 @@ +/* + * include/asm-sh/dma.h + * + * Copyright (C) 2003, 2004 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_DMA_H +#define __ASM_SH_DMA_H +#ifdef __KERNEL__ + +#include <linux/config.h> +#include <linux/spinlock.h> +#include <linux/wait.h> +#include <linux/sysdev.h> +#include <asm/cpu/dma.h> +#include <asm/semaphore.h> + +/* The maximum address that we can perform a DMA transfer to on this platform */ +/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any + occurrence should be flagged as an error. */ +/* But... */ +/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */ +#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) + +#ifdef CONFIG_NR_DMA_CHANNELS +# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS) +#else +# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS) +#endif + +/* + * Read and write modes can mean drastically different things depending on the + * channel configuration. Consult your DMAC documentation and module + * implementation for further clues. + */ +#define DMA_MODE_READ 0x00 +#define DMA_MODE_WRITE 0x01 +#define DMA_MODE_MASK 0x01 + +#define DMA_AUTOINIT 0x10 + +/* + * DMAC (dma_info) flags + */ +enum { + DMAC_CHANNELS_CONFIGURED = 0x00, + DMAC_CHANNELS_TEI_CAPABLE = 0x01, +}; + +/* + * DMA channel capabilities / flags + */ +enum { + DMA_CONFIGURED = 0x00, + DMA_TEI_CAPABLE = 0x01, +}; + +extern spinlock_t dma_spin_lock; + +struct dma_channel; + +struct dma_ops { + int (*request)(struct dma_channel *chan); + void (*free)(struct dma_channel *chan); + + int (*get_residue)(struct dma_channel *chan); + int (*xfer)(struct dma_channel *chan); + void (*configure)(struct dma_channel *chan, unsigned long flags); +}; + +struct dma_channel { + char dev_id[16]; + + unsigned int chan; + unsigned int mode; + unsigned int count; + + unsigned long sar; + unsigned long dar; + + unsigned long flags; + atomic_t busy; + + struct semaphore sem; + wait_queue_head_t wait_queue; + + struct sys_device dev; +}; + +struct dma_info { + const char *name; + unsigned int nr_channels; + unsigned long flags; + + struct dma_ops *ops; + struct dma_channel *channels; + + struct list_head list; +}; + +#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev) + +/* arch/sh/drivers/dma/dma-api.c */ +extern int dma_xfer(unsigned int chan, unsigned long from, + unsigned long to, size_t size, unsigned int mode); + +#define dma_write(chan, from, to, size) \ + dma_xfer(chan, from, to, size, DMA_MODE_WRITE) +#define dma_write_page(chan, from, to) \ + dma_write(chan, from, to, PAGE_SIZE) + +#define dma_read(chan, from, to, size) \ + dma_xfer(chan, from, to, size, DMA_MODE_READ) +#define dma_read_page(chan, from, to) \ + dma_read(chan, from, to, PAGE_SIZE) + +extern int request_dma(unsigned int chan, const char *dev_id); +extern void free_dma(unsigned int chan); +extern int get_dma_residue(unsigned int chan); +extern struct dma_info *get_dma_info(unsigned int chan); +extern struct dma_channel *get_dma_channel(unsigned int chan); +extern void dma_wait_for_completion(unsigned int chan); +extern void dma_configure_channel(unsigned int chan, unsigned long flags); + +extern int register_dmac(struct dma_info *info); +extern void unregister_dmac(struct dma_info *info); + +#ifdef CONFIG_SYSFS +/* arch/sh/drivers/dma/dma-sysfs.c */ +extern int dma_create_sysfs_files(struct dma_channel *); +#endif + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_DMA_H */ diff --git a/include/asm-sh/dmida/io.h b/include/asm-sh/dmida/io.h new file mode 100644 index 0000000..21bd416 --- /dev/null +++ b/include/asm-sh/dmida/io.h @@ -0,0 +1,10 @@ +#ifndef __ASM_SH_DMIDA_IO_H +#define __ASM_SH_DMIDA_IO_H + +/* + * Nothing special here.. just use the generic cchip io routines. + */ +#include <asm/hd64465/io.h> + +#endif /* __ASM_SH_DMIDA_IO_H */ + diff --git a/include/asm-sh/dreamcast/dma.h b/include/asm-sh/dreamcast/dma.h new file mode 100644 index 0000000..ddd68e7 --- /dev/null +++ b/include/asm-sh/dreamcast/dma.h @@ -0,0 +1,34 @@ +/* + * include/asm-sh/dreamcast/dma.h + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_DREAMCAST_DMA_H +#define __ASM_SH_DREAMCAST_DMA_H + +/* Number of DMA channels */ +#define ONCHIP_NR_DMA_CHANNELS 4 +#define G2_NR_DMA_CHANNELS 4 +#define PVR2_NR_DMA_CHANNELS 1 + +/* Channels for cascading */ +#define PVR2_CASCADE_CHAN 2 +#define G2_CASCADE_CHAN 3 + +/* PVR2 DMA Registers */ +#define PVR2_DMA_BASE 0xa05f6800 +#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0) +#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4) +#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8) +#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132) +#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136) + +/* G2 DMA Register */ +#define G2_DMA_BASE 0xa05f7800 + +#endif /* __ASM_SH_DREAMCAST_DMA_H */ + diff --git a/include/asm-sh/dreamcast/pci.h b/include/asm-sh/dreamcast/pci.h new file mode 100644 index 0000000..e401b24 --- /dev/null +++ b/include/asm-sh/dreamcast/pci.h @@ -0,0 +1,25 @@ +/* + * include/asm-sh/dreamcast/pci.h + * + * Copyright (C) 2001, 2002 M. R. Brown + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_DREAMCAST_PCI_H +#define __ASM_SH_DREAMCAST_PCI_H + +#include <asm/mach/sysasic.h> + +#define GAPSPCI_REGS 0x01001400 +#define GAPSPCI_DMA_BASE 0x01840000 +#define GAPSPCI_DMA_SIZE 32768 +#define GAPSPCI_BBA_CONFIG 0x01001600 +#define GAPSPCI_BBA_CONFIG_SIZE 0x2000 + +#define GAPSPCI_IRQ HW_EVENT_EXTERNAL + +#endif /* __ASM_SH_DREAMCAST_PCI_H */ + diff --git a/include/asm-sh/dreamcast/sysasic.h b/include/asm-sh/dreamcast/sysasic.h new file mode 100644 index 0000000..c885853 --- /dev/null +++ b/include/asm-sh/dreamcast/sysasic.h @@ -0,0 +1,43 @@ +/* include/asm-sh/dc_sysasic.h + * + * Definitions for the Dreamcast System ASIC and related peripherals. + * + * Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org> + * Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org> + * + * This file is part of the LinuxDC project (www.linuxdc.org) + * + * Released under the terms of the GNU GPL v2.0. + * + */ +#ifndef __ASM_SH_DREAMCAST_SYSASIC_H +#define __ASM_SH_DREAMCAST_SYSASIC_H + +#include <asm/irq.h> + +/* Hardware events - + + Each of these events correspond to a bit within the Event Mask Registers/ + Event Status Registers. Because of the virtual IRQ numbering scheme, a + base offset must be used when calculating the virtual IRQ that each event + takes. +*/ + +#define HW_EVENT_IRQ_BASE OFFCHIP_IRQ_BASE /* 48 */ + +/* IRQ 13 */ +#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */ +#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */ +#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */ +#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */ +#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */ + +/* IRQ 11 */ +#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */ +#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */ +#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */ + +#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95) + +#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */ + diff --git a/include/asm-sh/ec3104/ec3104.h b/include/asm-sh/ec3104/ec3104.h new file mode 100644 index 0000000..639cfa4 --- /dev/null +++ b/include/asm-sh/ec3104/ec3104.h @@ -0,0 +1,43 @@ +#ifndef __ASM_EC3104_H +#define __ASM_EC3104_H + + +/* + * Most of the register set is at 0xb0ec0000 - 0xb0ecffff. + * + * as far as I've figured it out the register map is: + * 0xb0ec0000 - id string + * 0xb0ec0XXX - power management + * 0xb0ec1XXX - interrupt control + * 0xb0ec3XXX - ps2 port (touch pad on aero 8000) + * 0xb0ec6XXX - i2c + * 0xb0ec7000 - first serial port (proprietary connector on aero 8000) + * 0xb0ec8000 - second serial port + * 0xb0ec9000 - third serial port + * 0xb0eca000 - fourth serial port (keyboard controller on aero 8000) + * 0xb0eccXXX - GPIO + * 0xb0ecdXXX - GPIO + */ + +#define EC3104_BASE 0xb0ec0000 + +#define EC3104_SER4_DATA (EC3104_BASE+0xa000) +#define EC3104_SER4_IIR (EC3104_BASE+0xa008) +#define EC3104_SER4_MCR (EC3104_BASE+0xa010) +#define EC3104_SER4_LSR (EC3104_BASE+0xa014) +#define EC3104_SER4_MSR (EC3104_BASE+0xa018) + +/* + * our ISA bus. this seems to be real ISA. + */ +#define EC3104_ISA_BASE 0xa5000000 + +#define EC3104_IRQ 11 +#define EC3104_IRQBASE 64 + +#define EC3104_IRQ_SER1 EC3104_IRQBASE + 7 +#define EC3104_IRQ_SER2 EC3104_IRQBASE + 8 +#define EC3104_IRQ_SER3 EC3104_IRQBASE + 9 +#define EC3104_IRQ_SER4 EC3104_IRQBASE + 10 + +#endif /* __ASM_EC3104_H */ diff --git a/include/asm-sh/ec3104/io.h b/include/asm-sh/ec3104/io.h new file mode 100644 index 0000000..ea5c8e6 --- /dev/null +++ b/include/asm-sh/ec3104/io.h @@ -0,0 +1,16 @@ +#ifndef _ASM_SH_IO_EC3104_H +#define _ASM_SH_IO_EC3104_H + +#include <linux/types.h> + +extern unsigned char ec3104_inb(unsigned long port); +extern unsigned short ec3104_inw(unsigned long port); +extern unsigned long ec3104_inl(unsigned long port); + +extern void ec3104_outb(unsigned char value, unsigned long port); +extern void ec3104_outw(unsigned short value, unsigned long port); +extern void ec3104_outl(unsigned long value, unsigned long port); + +extern int ec3104_irq_demux(int irq); + +#endif /* _ASM_SH_IO_EC3104_H */ diff --git a/include/asm-sh/ec3104/keyboard.h b/include/asm-sh/ec3104/keyboard.h new file mode 100644 index 0000000..0dee7b0 --- /dev/null +++ b/include/asm-sh/ec3104/keyboard.h @@ -0,0 +1,17 @@ +extern unsigned char ec3104_kbd_sysrq_xlate[]; +extern int ec3104_kbd_setkeycode(unsigned int scancode, unsigned int keycode); +extern int ec3104_kbd_getkeycode(unsigned int scancode); +extern int ec3104_kbd_translate(unsigned char, unsigned char *, char); +extern char ec3104_kbd_unexpected_up(unsigned char); +extern void ec3104_kbd_leds(unsigned char); +extern void ec3104_kbd_init_hw(void); + +#define SYSRQ_KEY 0x54 + +#define kbd_sysrq_xlate ec3104_kbd_sysrq_xlate +#define kbd_setkeycode ec3104_kbd_setkeycode +#define kbd_getkeycode ec3104_kbd_getkeycode +#define kbd_translate ec3104_kbd_translate +#define kbd_unexpected_up ec3104_kbd_unexpected_up +#define kbd_leds ec3104_kbd_leds +#define kbd_init_hw ec3104_kbd_init_hw diff --git a/include/asm-sh/ec3104/serial.h b/include/asm-sh/ec3104/serial.h new file mode 100644 index 0000000..f8eb163 --- /dev/null +++ b/include/asm-sh/ec3104/serial.h @@ -0,0 +1,22 @@ +#include <asm/ec3104.h> +/* Naturally we don't know the exact value but 115200 baud has a divisor + * of 9 and 19200 baud has a divisor of 52, so this seems like a good + * guess. */ +#define BASE_BAUD (16800000 / 16) + +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +/* there is a fourth serial port with the expected values as well, but + * it's got the keyboard controller behind it so we can't really use it + * (without moving the keyboard driver to userspace, which doesn't sound + * like a very good idea) */ +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \ + { 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */ + +#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS + +/* XXX: This should be moved ino irq.h */ +#define irq_cannonicalize(x) (x) diff --git a/include/asm-sh/edosk7705/io.h b/include/asm-sh/edosk7705/io.h new file mode 100644 index 0000000..a1089a6 --- /dev/null +++ b/include/asm-sh/edosk7705/io.h @@ -0,0 +1,30 @@ +/* + * include/asm-sh/edosk7705/io.h + * + * Modified version of io_se.h for the EDOSK7705 specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Hitachi EDOSK7705 development board + */ + +#ifndef __ASM_SH_EDOSK7705_IO_H +#define __ASM_SH_EDOSK7705_IO_H + +#include <asm/io_generic.h> + +extern unsigned char sh_edosk7705_inb(unsigned long port); +extern unsigned int sh_edosk7705_inl(unsigned long port); + +extern void sh_edosk7705_outb(unsigned char value, unsigned long port); +extern void sh_edosk7705_outl(unsigned int value, unsigned long port); + +extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count); +extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count); +extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset); + +#endif /* __ASM_SH_EDOSK7705_IO_H */ diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h new file mode 100644 index 0000000..8fe00a1 --- /dev/null +++ b/include/asm-sh/elf.h @@ -0,0 +1,121 @@ +#ifndef __ASM_SH_ELF_H +#define __ASM_SH_ELF_H + +/* SH relocation types */ +#define R_SH_NONE 0 +#define R_SH_DIR32 1 +#define R_SH_REL32 2 +#define R_SH_DIR8WPN 3 +#define R_SH_IND12W 4 +#define R_SH_DIR8WPL 5 +#define R_SH_DIR8WPZ 6 +#define R_SH_DIR8BP 7 +#define R_SH_DIR8W 8 +#define R_SH_DIR8L 9 +#define R_SH_SWITCH16 25 +#define R_SH_SWITCH32 26 +#define R_SH_USES 27 +#define R_SH_COUNT 28 +#define R_SH_ALIGN 29 +#define R_SH_CODE 30 +#define R_SH_DATA 31 +#define R_SH_LABEL 32 +#define R_SH_SWITCH8 33 +#define R_SH_GNU_VTINHERIT 34 +#define R_SH_GNU_VTENTRY 35 +#define R_SH_TLS_GD_32 144 +#define R_SH_TLS_LD_32 145 +#define R_SH_TLS_LDO_32 146 +#define R_SH_TLS_IE_32 147 +#define R_SH_TLS_LE_32 148 +#define R_SH_TLS_DTPMOD32 149 +#define R_SH_TLS_DTPOFF32 150 +#define R_SH_TLS_TPOFF32 151 +#define R_SH_GOT32 160 +#define R_SH_PLT32 161 +#define R_SH_COPY 162 +#define R_SH_GLOB_DAT 163 +#define R_SH_JMP_SLOT 164 +#define R_SH_RELATIVE 165 +#define R_SH_GOTOFF 166 +#define R_SH_GOTPC 167 +/* Keep this the last entry. */ +#define R_SH_NUM 256 + +/* + * ELF register definitions.. + */ + +#include <asm/ptrace.h> +#include <asm/user.h> + +typedef unsigned long elf_greg_t; + +#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) +typedef elf_greg_t elf_gregset_t[ELF_NGREG]; + +typedef struct user_fpu_struct elf_fpregset_t; + +/* + * This is used to ensure we don't load something for the wrong architecture. + */ +#define elf_check_arch(x) ( (x)->e_machine == EM_SH ) + +/* + * These are used to set parameters in the core dumps. + */ +#define ELF_CLASS ELFCLASS32 +#ifdef __LITTLE_ENDIAN__ +#define ELF_DATA ELFDATA2LSB +#else +#define ELF_DATA ELFDATA2MSB +#endif +#define ELF_ARCH EM_SH + +#define USE_ELF_CORE_DUMP +#define ELF_EXEC_PAGESIZE 4096 + +/* This is the location that an ET_DYN program is loaded if exec'ed. Typical + use of this is to invoke "./ld.so someprog" to test out a new version of + the loader. We need to make sure that it is out of the way of the program + that it will "exec", and that there is sufficient room for the brk. */ + +#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3) + + +#define ELF_CORE_COPY_REGS(_dest,_regs) \ + memcpy((char *) &_dest, (char *) _regs, \ + sizeof(struct pt_regs)); + +/* This yields a mask that user programs can use to figure out what + instruction set this CPU supports. This could be done in user space, + but it's not easy, and we've already done it here. */ + +#define ELF_HWCAP (0) + +/* This yields a string that ld.so will use to load implementation + specific libraries for optimization. This is more specific in + intent than poking at uname or /proc/cpuinfo. + + For the moment, we have only optimizations for the Intel generations, + but that could change... */ + +#define ELF_PLATFORM (NULL) + +#define ELF_PLAT_INIT(_r, load_addr) \ + do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \ + _r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \ + _r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \ + _r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \ + _r->sr = SR_FD; } while (0) + +#ifdef __KERNEL__ +#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT) +extern int dump_task_regs (struct task_struct *, elf_gregset_t *); +extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *); + +#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) +#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs) +#endif + +#endif /* __ASM_SH_ELF_H */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h new file mode 100644 index 0000000..51cf6f9 --- /dev/null +++ b/include/asm-sh/errno.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_ERRNO_H +#define __ASM_SH_ERRNO_H + +#include <asm-generic/errno.h> + +#endif /* __ASM_SH_ERRNO_H */ diff --git a/include/asm-sh/fcntl.h b/include/asm-sh/fcntl.h new file mode 100644 index 0000000..0b3ae52 --- /dev/null +++ b/include/asm-sh/fcntl.h @@ -0,0 +1,88 @@ +#ifndef __ASM_SH_FCNTL_H +#define __ASM_SH_FCNTL_H + +/* open/fcntl - O_SYNC is only implemented on blocks devices and on files + located on an ext2 file system */ +#define O_ACCMODE 0003 +#define O_RDONLY 00 +#define O_WRONLY 01 +#define O_RDWR 02 +#define O_CREAT 0100 /* not fcntl */ +#define O_EXCL 0200 /* not fcntl */ +#define O_NOCTTY 0400 /* not fcntl */ +#define O_TRUNC 01000 /* not fcntl */ +#define O_APPEND 02000 +#define O_NONBLOCK 04000 +#define O_NDELAY O_NONBLOCK +#define O_SYNC 010000 +#define FASYNC 020000 /* fcntl, for BSD compatibility */ +#define O_DIRECT 040000 /* direct disk access hint - currently ignored */ +#define O_LARGEFILE 0100000 +#define O_DIRECTORY 0200000 /* must be a directory */ +#define O_NOFOLLOW 0400000 /* don't follow links */ +#define O_NOATIME 01000000 + +#define F_DUPFD 0 /* dup */ +#define F_GETFD 1 /* get close_on_exec */ +#define F_SETFD 2 /* set/clear close_on_exec */ +#define F_GETFL 3 /* get file->f_flags */ +#define F_SETFL 4 /* set file->f_flags */ +#define F_GETLK 5 +#define F_SETLK 6 +#define F_SETLKW 7 + +#define F_SETOWN 8 /* for sockets. */ +#define F_GETOWN 9 /* for sockets. */ +#define F_SETSIG 10 /* for sockets. */ +#define F_GETSIG 11 /* for sockets. */ + +#define F_GETLK64 12 /* using 'struct flock64' */ +#define F_SETLK64 13 +#define F_SETLKW64 14 + +/* for F_[GET|SET]FL */ +#define FD_CLOEXEC 1 /* actually anything with low bit set goes */ + +/* for posix fcntl() and lockf() */ +#define F_RDLCK 0 +#define F_WRLCK 1 +#define F_UNLCK 2 + +/* for old implementation of bsd flock () */ +#define F_EXLCK 4 /* or 3 */ +#define F_SHLCK 8 /* or 4 */ + +/* for leases */ +#define F_INPROGRESS 16 + +/* operations for bsd flock(), also used by the kernel implementation */ +#define LOCK_SH 1 /* shared lock */ +#define LOCK_EX 2 /* exclusive lock */ +#define LOCK_NB 4 /* or'd with one of the above to prevent + blocking */ +#define LOCK_UN 8 /* remove lock */ + +#define LOCK_MAND 32 /* This is a mandatory flock */ +#define LOCK_READ 64 /* ... Which allows concurrent read operations */ +#define LOCK_WRITE 128 /* ... Which allows concurrent write operations */ +#define LOCK_RW 192 /* ... Which allows concurrent read & write ops */ + +struct flock { + short l_type; + short l_whence; + off_t l_start; + off_t l_len; + pid_t l_pid; +}; + +struct flock64 { + short l_type; + short l_whence; + loff_t l_start; + loff_t l_len; + pid_t l_pid; +}; + +#define F_LINUX_SPECIFIC_BASE 1024 +#endif /* __ASM_SH_FCNTL_H */ + diff --git a/include/asm-sh/fixmap.h b/include/asm-sh/fixmap.h new file mode 100644 index 0000000..509224b --- /dev/null +++ b/include/asm-sh/fixmap.h @@ -0,0 +1,111 @@ +/* + * fixmap.h: compile-time virtual memory allocation + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998 Ingo Molnar + * + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 + */ + +#ifndef _ASM_FIXMAP_H +#define _ASM_FIXMAP_H + +#include <linux/config.h> +#include <linux/kernel.h> +#include <asm/page.h> +#ifdef CONFIG_HIGHMEM +#include <linux/threads.h> +#include <asm/kmap_types.h> +#endif + +/* + * Here we define all the compile-time 'special' virtual + * addresses. The point is to have a constant address at + * compile time, but to set the physical address only + * in the boot process. We allocate these special addresses + * from the end of virtual memory (0xfffff000) backwards. + * Also this lets us do fail-safe vmalloc(), we + * can guarantee that these special addresses and + * vmalloc()-ed addresses never overlap. + * + * these 'compile-time allocated' memory buffers are + * fixed-size 4k pages. (or larger if used with an increment + * highger than 1) use fixmap_set(idx,phys) to associate + * physical memory with fixmap indices. + * + * TLB entries of such buffers will not be flushed across + * task switches. + */ + +/* + * on UP currently we will have no trace of the fixmap mechanizm, + * no page table allocations, etc. This might change in the + * future, say framebuffers for the console driver(s) could be + * fix-mapped? + */ +enum fixed_addresses { +#ifdef CONFIG_HIGHMEM + FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ + FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, +#endif + __end_of_fixed_addresses +}; + +extern void __set_fixmap (enum fixed_addresses idx, + unsigned long phys, pgprot_t flags); + +#define set_fixmap(idx, phys) \ + __set_fixmap(idx, phys, PAGE_KERNEL) +/* + * Some hardware wants to get fixmapped without caching. + */ +#define set_fixmap_nocache(idx, phys) \ + __set_fixmap(idx, phys, PAGE_KERNEL_NOCACHE) +/* + * used by vmalloc.c. + * + * Leave one empty page between vmalloc'ed areas and + * the start of the fixmap, and leave one page empty + * at the top of mem.. + */ +#define FIXADDR_TOP (P4SEG - PAGE_SIZE) +#define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) +#define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) + +#define __fix_to_virt(x) (FIXADDR_TOP - ((x) << PAGE_SHIFT)) +#define __virt_to_fix(x) ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT) + +extern void __this_fixmap_does_not_exist(void); + +/* + * 'index to address' translation. If anyone tries to use the idx + * directly without tranlation, we catch the bug with a NULL-deference + * kernel oops. Illegal ranges of incoming indices are caught too. + */ +static inline unsigned long fix_to_virt(const unsigned int idx) +{ + /* + * this branch gets completely eliminated after inlining, + * except when someone tries to use fixaddr indices in an + * illegal way. (such as mixing up address types or using + * out-of-range indices). + * + * If it doesn't get removed, the linker will complain + * loudly with a reasonably clear error message.. + */ + if (idx >= __end_of_fixed_addresses) + __this_fixmap_does_not_exist(); + + return __fix_to_virt(idx); +} + +static inline unsigned long virt_to_fix(const unsigned long vaddr) +{ + BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START); + return __virt_to_fix(vaddr); +} + +#endif diff --git a/include/asm-sh/flat.h b/include/asm-sh/flat.h new file mode 100644 index 0000000..f29072e --- /dev/null +++ b/include/asm-sh/flat.h @@ -0,0 +1,23 @@ +/* + * include/asm-sh/flat.h + * + * uClinux flat-format executables + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive for + * more details. + */ +#ifndef __ASM_SH_FLAT_H +#define __ASM_SH_FLAT_H + +#define flat_stack_align(sp) /* nothing needed */ +#define flat_argvp_envp_on_stack() 1 +#define flat_old_ram_flag(flags) (flags) +#define flat_reloc_valid(reloc, size) ((reloc) <= (size)) +#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp) +#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp) +#define flat_get_relocate_addr(rel) (rel) + +#endif /* __ASM_SH_FLAT_H */ diff --git a/include/asm-sh/floppy.h b/include/asm-sh/floppy.h new file mode 100644 index 0000000..f030ca0 --- /dev/null +++ b/include/asm-sh/floppy.h @@ -0,0 +1,274 @@ +/* + * Architecture specific parts of the Floppy driver + * include/asm-i386/floppy.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1995 + */ +#ifndef __ASM_SH_FLOPPY_H +#define __ASM_SH_FLOPPY_H + +#include <linux/vmalloc.h> + + +/* + * The DMA channel used by the floppy controller cannot access data at + * addresses >= 16MB + * + * Went back to the 1MB limit, as some people had problems with the floppy + * driver otherwise. It doesn't matter much for performance anyway, as most + * floppy accesses go through the track buffer. + */ +#define _CROSS_64KB(a,s,vdma) \ +(!vdma && ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)) + +#define CROSS_64KB(a,s) _CROSS_64KB(a,s,use_virtual_dma & 1) + + +#define SW fd_routine[use_virtual_dma&1] +#define CSW fd_routine[can_use_virtual_dma & 1] + + +#define fd_inb(port) inb_p(port) +#define fd_outb(value,port) outb_p(value,port) + +#define fd_request_dma() CSW._request_dma(FLOPPY_DMA,"floppy") +#define fd_free_dma() CSW._free_dma(FLOPPY_DMA) +#define fd_enable_irq() enable_irq(FLOPPY_IRQ) +#define fd_disable_irq() disable_irq(FLOPPY_IRQ) +#define fd_free_irq() free_irq(FLOPPY_IRQ, NULL) +#define fd_get_dma_residue() SW._get_dma_residue(FLOPPY_DMA) +#define fd_dma_mem_alloc(size) SW._dma_mem_alloc(size) +#define fd_dma_setup(addr, size, mode, io) SW._dma_setup(addr, size, mode, io) + +#define FLOPPY_CAN_FALLBACK_ON_NODMA + +static int virtual_dma_count; +static int virtual_dma_residue; +static char *virtual_dma_addr; +static int virtual_dma_mode; +static int doing_pdma; + +static void floppy_hardint(int irq, void *dev_id, struct pt_regs * regs) +{ + register unsigned char st; + +#undef TRACE_FLPY_INT + +#ifdef TRACE_FLPY_INT + static int calls=0; + static int bytes=0; + static int dma_wait=0; +#endif + if(!doing_pdma) { + floppy_interrupt(irq, dev_id, regs); + return; + } + +#ifdef TRACE_FLPY_INT + if(!calls) + bytes = virtual_dma_count; +#endif + + { + register int lcount; + register char *lptr; + + st = 1; + for(lcount=virtual_dma_count, lptr=virtual_dma_addr; + lcount; lcount--, lptr++) { + st=inb(virtual_dma_port+4) & 0xa0 ; + if(st != 0xa0) + break; + if(virtual_dma_mode) + outb_p(*lptr, virtual_dma_port+5); + else + *lptr = inb_p(virtual_dma_port+5); + } + virtual_dma_count = lcount; + virtual_dma_addr = lptr; + st = inb(virtual_dma_port+4); + } + +#ifdef TRACE_FLPY_INT + calls++; +#endif + if(st == 0x20) + return; + if(!(st & 0x20)) { + virtual_dma_residue += virtual_dma_count; + virtual_dma_count=0; +#ifdef TRACE_FLPY_INT + printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n", + virtual_dma_count, virtual_dma_residue, calls, bytes, + dma_wait); + calls = 0; + dma_wait=0; +#endif + doing_pdma = 0; + floppy_interrupt(irq, dev_id, regs); + return; + } +#ifdef TRACE_FLPY_INT + if(!virtual_dma_count) + dma_wait++; +#endif +} + +static void fd_disable_dma(void) +{ + if(! (can_use_virtual_dma & 1)) + disable_dma(FLOPPY_DMA); + doing_pdma = 0; + virtual_dma_residue += virtual_dma_count; + virtual_dma_count=0; +} + +static int vdma_request_dma(unsigned int dmanr, const char * device_id) +{ + return 0; +} + +static void vdma_nop(unsigned int dummy) +{ +} + + +static int vdma_get_dma_residue(unsigned int dummy) +{ + return virtual_dma_count + virtual_dma_residue; +} + + +static int fd_request_irq(void) +{ + if(can_use_virtual_dma) + return request_irq(FLOPPY_IRQ, floppy_hardint,SA_INTERRUPT, + "floppy", NULL); + else + return request_irq(FLOPPY_IRQ, floppy_interrupt, + SA_INTERRUPT|SA_SAMPLE_RANDOM, + "floppy", NULL); + +} + +static unsigned long dma_mem_alloc(unsigned long size) +{ + return __get_dma_pages(GFP_KERNEL,get_order(size)); +} + + +static unsigned long vdma_mem_alloc(unsigned long size) +{ + return (unsigned long) vmalloc(size); + +} + +#define nodma_mem_alloc(size) vdma_mem_alloc(size) + +static void _fd_dma_mem_free(unsigned long addr, unsigned long size) +{ + if((unsigned int) addr >= (unsigned int) high_memory) + return vfree((void *)addr); + else + free_pages(addr, get_order(size)); +} + +#define fd_dma_mem_free(addr, size) _fd_dma_mem_free(addr, size) + +static void _fd_chose_dma_mode(char *addr, unsigned long size) +{ + if(can_use_virtual_dma == 2) { + if((unsigned int) addr >= (unsigned int) high_memory || + virt_to_bus(addr) >= 0x10000000) + use_virtual_dma = 1; + else + use_virtual_dma = 0; + } else { + use_virtual_dma = can_use_virtual_dma & 1; + } +} + +#define fd_chose_dma_mode(addr, size) _fd_chose_dma_mode(addr, size) + + +static int vdma_dma_setup(char *addr, unsigned long size, int mode, int io) +{ + doing_pdma = 1; + virtual_dma_port = io; + virtual_dma_mode = (mode == DMA_MODE_WRITE); + virtual_dma_addr = addr; + virtual_dma_count = size; + virtual_dma_residue = 0; + return 0; +} + +static int hard_dma_setup(char *addr, unsigned long size, int mode, int io) +{ +#ifdef FLOPPY_SANITY_CHECK + if (CROSS_64KB(addr, size)) { + printk("DMA crossing 64-K boundary %p-%p\n", addr, addr+size); + return -1; + } +#endif + + dma_cache_wback_inv(addr, size); + + /* actual, physical DMA */ + doing_pdma = 0; + clear_dma_ff(FLOPPY_DMA); + set_dma_mode(FLOPPY_DMA,mode); + set_dma_addr(FLOPPY_DMA,virt_to_bus(addr)); + set_dma_count(FLOPPY_DMA,size); + enable_dma(FLOPPY_DMA); + return 0; +} + +struct fd_routine_l { + int (*_request_dma)(unsigned int dmanr, const char * device_id); + void (*_free_dma)(unsigned int dmanr); + int (*_get_dma_residue)(unsigned int dummy); + unsigned long (*_dma_mem_alloc) (unsigned long size); + int (*_dma_setup)(char *addr, unsigned long size, int mode, int io); +} fd_routine[] = { + { + request_dma, + free_dma, + get_dma_residue, + dma_mem_alloc, + hard_dma_setup + }, + { + vdma_request_dma, + vdma_nop, + vdma_get_dma_residue, + vdma_mem_alloc, + vdma_dma_setup + } +}; + + +static int FDC1 = 0x3f0; +static int FDC2 = -1; + +/* + * Floppy types are stored in the rtc's CMOS RAM and so rtc_lock + * is needed to prevent corrupted CMOS RAM in case "insmod floppy" + * coincides with another rtc CMOS user. Paul G. + */ +#define FLOPPY0_TYPE (4) +#define FLOPPY1_TYPE (0) + +#define N_FDC 2 +#define N_DRIVE 8 + +#define FLOPPY_MOTOR_MASK 0xf0 + +#define AUTO_DMA + +#define EXTRA_FLOPPY_PARAMS + +#endif /* __ASM_SH_FLOPPY_H */ diff --git a/include/asm-sh/freq.h b/include/asm-sh/freq.h new file mode 100644 index 0000000..2c0fde4 --- /dev/null +++ b/include/asm-sh/freq.h @@ -0,0 +1,29 @@ +/* + * include/asm-sh/freq.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __ASM_SH_FREQ_H +#define __ASM_SH_FREQ_H +#ifdef __KERNEL__ + +#include <asm/cpu/freq.h> + +/* arch/sh/kernel/time.c */ +extern void get_current_frequency_divisors(unsigned int *ifc, unsigned int *pfc, unsigned int *bfc); + +extern unsigned int get_ifc_divisor(unsigned int value); +extern unsigned int get_ifc_divisor(unsigned int value); +extern unsigned int get_ifc_divisor(unsigned int value); + +extern unsigned int get_ifc_value(unsigned int divisor); +extern unsigned int get_pfc_value(unsigned int divisor); +extern unsigned int get_bfc_value(unsigned int divisor); + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_FREQ_H */ diff --git a/include/asm-sh/hardirq.h b/include/asm-sh/hardirq.h new file mode 100644 index 0000000..f2fdf0f --- /dev/null +++ b/include/asm-sh/hardirq.h @@ -0,0 +1,17 @@ +#ifndef __ASM_SH_HARDIRQ_H +#define __ASM_SH_HARDIRQ_H + +#include <linux/config.h> +#include <linux/threads.h> +#include <linux/irq.h> + +/* entry.S is sensitive to the offsets of these fields */ +typedef struct { + unsigned int __softirq_pending; +} ____cacheline_aligned irq_cpustat_t; + +#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */ + +extern void ack_bad_irq(unsigned int irq); + +#endif /* __ASM_SH_HARDIRQ_H */ diff --git a/include/asm-sh/harp/harp.h b/include/asm-sh/harp/harp.h new file mode 100644 index 0000000..b2fbcfa --- /dev/null +++ b/include/asm-sh/harp/harp.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Defintions applicable to the STMicroelectronics ST40STB1 HARP and + * compatible boards. + */ + +#if defined(CONFIG_SH_STB1_HARP) + +#define EPLD_BASE 0xa0800000 + +#define EPLD_LED (EPLD_BASE+0x000c0000) +#define EPLD_INTSTAT0 (EPLD_BASE+0x00200000) +#define EPLD_INTSTAT1 (EPLD_BASE+0x00240000) +#define EPLD_INTMASK0 (EPLD_BASE+0x00280000) +#define EPLD_INTMASK1 (EPLD_BASE+0x002c0000) +#define EPLD_PAGEADDR (EPLD_BASE+0x00300000) +#define EPLD_REVID1 (EPLD_BASE+0x00380000) +#define EPLD_REVID2 (EPLD_BASE+0x003c0000) + +#define EPLD_LED_ON 1 +#define EPLD_LED_OFF 0 + +#elif defined(CONFIG_SH_STB1_OVERDRIVE) + +#define EPLD_BASE 0xa7000000 + +#define EPLD_REVID (EPLD_BASE+0x00000000) +#define EPLD_LED (EPLD_BASE+0x00040000) +#define EPLD_INTMASK0 (EPLD_BASE+0x001c0000) +#define EPLD_INTMASK1 (EPLD_BASE+0x00200000) +#define EPLD_INTSTAT0 (EPLD_BASE+0x00240000) +#define EPLD_INTSTAT1 (EPLD_BASE+0x00280000) + +#define EPLD_LED_ON 0 +#define EPLD_LED_OFF 1 + +#else +#error Unknown board +#endif diff --git a/include/asm-sh/harp/io.h b/include/asm-sh/harp/io.h new file mode 100644 index 0000000..68f39e0 --- /dev/null +++ b/include/asm-sh/harp/io.h @@ -0,0 +1,10 @@ +#ifndef __ASM_SH_HARP_IO_H +#define __ASM_SH_HARP_IO_H + +/* + * Nothing special here.. just use the generic cchip io routines. + */ +#include <asm/hd64465/io.h> + +#endif /* __ASM_SH_HARP_IO_H */ + diff --git a/include/asm-sh/hd64461/hd64461.h b/include/asm-sh/hd64461/hd64461.h new file mode 100644 index 0000000..c457ca2 --- /dev/null +++ b/include/asm-sh/hd64461/hd64461.h @@ -0,0 +1,203 @@ +#ifndef __ASM_SH_HD64461 +#define __ASM_SH_HD64461 +/* + * $Id: hd64461.h,v 1.5 2004/03/16 00:07:51 lethal Exp $ + * Copyright (C) 2000 YAEGASHI Takeshi + * Hitachi HD64461 companion chip support + */ +#include <linux/config.h> + +/* Constants for PCMCIA mappings */ +#define HD64461_PCC_WINDOW 0x01000000 + +#define HD64461_PCC0_BASE 0xb8000000 /* area 6 */ +#define HD64461_PCC0_ATTR (HD64461_PCC0_BASE) +#define HD64461_PCC0_COMM (HD64461_PCC0_BASE+HD64461_PCC_WINDOW) +#define HD64461_PCC0_IO (HD64461_PCC0_BASE+2*HD64461_PCC_WINDOW) + +#define HD64461_PCC1_BASE 0xb4000000 /* area 5 */ +#define HD64461_PCC1_ATTR (HD64461_PCC1_BASE) +#define HD64461_PCC1_COMM (HD64461_PCC1_BASE+HD64461_PCC_WINDOW) + +#define HD64461_STBCR 0x10000 +#define HD64461_STBCR_CKIO_STBY 0x2000 +#define HD64461_STBCR_SAFECKE_IST 0x1000 +#define HD64461_STBCR_SLCKE_IST 0x0800 +#define HD64461_STBCR_SAFECKE_OST 0x0400 +#define HD64461_STBCR_SLCKE_OST 0x0200 +#define HD64461_STBCR_SMIAST 0x0100 +#define HD64461_STBCR_SLCDST 0x0080 +#define HD64461_STBCR_SPC0ST 0x0040 +#define HD64461_STBCR_SPC1ST 0x0020 +#define HD64461_STBCR_SAFEST 0x0010 +#define HD64461_STBCR_STM0ST 0x0008 +#define HD64461_STBCR_STM1ST 0x0004 +#define HD64461_STBCR_SIRST 0x0002 +#define HD64461_STBCR_SURTST 0x0001 + +#define HD64461_SYSCR 0x10002 +#define HD64461_SCPUCR 0x10004 + +#define HD64461_LCDCBAR 0x11000 +#define HD64461_LCDCLOR 0x11002 +#define HD64461_LCDCCR 0x11004 +#define HD64461_LCDCCR_MOFF 0x80 + +#define HD64461_LDR1 0x11010 +#define HD64461_LDR1_DON 0x01 +#define HD64461_LDR1_DINV 0x80 + +#define HD64461_LDR2 0x11012 +#define HD64461_LDHNCR 0x11014 +#define HD64461_LDHNSR 0x11016 +#define HD64461_LDVNTR 0x11018 +#define HD64461_LDVNDR 0x1101a +#define HD64461_LDVSPR 0x1101c +#define HD64461_LDR3 0x1101e + +#define HD64461_CPTWAR 0x11030 +#define HD64461_CPTWDR 0x11032 +#define HD64461_CPTRAR 0x11034 +#define HD64461_CPTRDR 0x11036 + +#define HD64461_GRDOR 0x11040 +#define HD64461_GRSCR 0x11042 +#define HD64461_GRCFGR 0x11044 +#define HD64461_GRCFGR_ACCSTATUS 0x10 +#define HD64461_GRCFGR_ACCRESET 0x08 +#define HD64461_GRCFGR_ACCSTART_BITBLT 0x06 +#define HD64461_GRCFGR_ACCSTART_LINE 0x04 +#define HD64461_GRCFGR_COLORDEPTH16 0x01 + +#define HD64461_LNSARH 0x11046 +#define HD64461_LNSARL 0x11048 +#define HD64461_LNAXLR 0x1104a +#define HD64461_LNDGR 0x1104c +#define HD64461_LNAXR 0x1104e +#define HD64461_LNERTR 0x11050 +#define HD64461_LNMDR 0x11052 +#define HD64461_BBTSSARH 0x11054 +#define HD64461_BBTSSARL 0x11056 +#define HD64461_BBTDSARH 0x11058 +#define HD64461_BBTDSARL 0x1105a +#define HD64461_BBTDWR 0x1105c +#define HD64461_BBTDHR 0x1105e +#define HD64461_BBTPARH 0x11060 +#define HD64461_BBTPARL 0x11062 +#define HD64461_BBTMARH 0x11064 +#define HD64461_BBTMARL 0x11066 +#define HD64461_BBTROPR 0x11068 +#define HD64461_BBTMDR 0x1106a + +/* PC Card Controller Registers */ +#define HD64461_PCC0ISR 0x12000 /* socket 0 interface status */ +#define HD64461_PCC0GCR 0x12002 /* socket 0 general control */ +#define HD64461_PCC0CSCR 0x12004 /* socket 0 card status change */ +#define HD64461_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ +#define HD64461_PCC0SCR 0x12008 /* socket 0 software control */ +#define HD64461_PCC1ISR 0x12010 /* socket 1 interface status */ +#define HD64461_PCC1GCR 0x12012 /* socket 1 general control */ +#define HD64461_PCC1CSCR 0x12014 /* socket 1 card status change */ +#define HD64461_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ +#define HD64461_PCC1SCR 0x12018 /* socket 1 software control */ + +/* PCC Interface Status Register */ +#define HD64461_PCCISR_READY 0x80 /* card ready */ +#define HD64461_PCCISR_MWP 0x40 /* card write-protected */ +#define HD64461_PCCISR_VS2 0x20 /* voltage select pin 2 */ +#define HD64461_PCCISR_VS1 0x10 /* voltage select pin 1 */ +#define HD64461_PCCISR_CD2 0x08 /* card detect 2 */ +#define HD64461_PCCISR_CD1 0x04 /* card detect 1 */ +#define HD64461_PCCISR_BVD2 0x02 /* battery 1 */ +#define HD64461_PCCISR_BVD1 0x01 /* battery 1 */ + +#define HD64461_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64461_PCCISR_BVD_MASK 0x03 /* battery voltage */ +#define HD64461_PCCISR_BVD_BATGOOD 0x03 /* battery good */ +#define HD64461_PCCISR_BVD_BATWARN 0x01 /* battery low warning */ +#define HD64461_PCCISR_BVD_BATDEAD1 0x02 /* battery dead */ +#define HD64461_PCCISR_BVD_BATDEAD2 0x00 /* battery dead */ + +/* PCC General Control Register */ +#define HD64461_PCCGCR_DRVE 0x80 /* output drive */ +#define HD64461_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64461_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64461_PCCGCR_VCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64461_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64461_PCCGCR_PA25 0x04 /* pin A25 */ +#define HD64461_PCCGCR_PA24 0x02 /* pin A24 */ +#define HD64461_PCCGCR_REG 0x01 /* pin PCC0REG# */ + +/* PCC Card Status Change Register */ +#define HD64461_PCCCSCR_SCDI 0x80 /* sw card detect intr */ +#define HD64461_PCCCSCR_SRV1 0x40 /* reserved */ +#define HD64461_PCCCSCR_IREQ 0x20 /* IREQ intr req */ +#define HD64461_PCCCSCR_SC 0x10 /* STSCHG (status change) pin */ +#define HD64461_PCCCSCR_CDC 0x08 /* CD (card detect) change */ +#define HD64461_PCCCSCR_RC 0x04 /* READY change */ +#define HD64461_PCCCSCR_BW 0x02 /* battery warning change */ +#define HD64461_PCCCSCR_BD 0x01 /* battery dead change */ + +/* PCC Card Status Change Interrupt Enable Register */ +#define HD64461_PCCCSCIER_CRE 0x80 /* change reset enable */ +#define HD64461_PCCCSCIER_IREQE_MASK 0x60 /* IREQ enable */ +#define HD64461_PCCCSCIER_IREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64461_PCCCSCIER_IREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64461_PCCCSCIER_IREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64461_PCCCSCIER_IREQE_RISING 0x60 /* IREQ rising-edge-trig */ + +#define HD64461_PCCCSCIER_SCE 0x10 /* status change enable */ +#define HD64461_PCCCSCIER_CDE 0x08 /* card detect change enable */ +#define HD64461_PCCCSCIER_RE 0x04 /* ready change enable */ +#define HD64461_PCCCSCIER_BWE 0x02 /* battery warn change enable */ +#define HD64461_PCCCSCIER_BDE 0x01 /* battery dead change enable*/ + +/* PCC Software Control Register */ +#define HD64461_PCCSCR_VCC1 0x02 /* voltage control pin 1 */ +#define HD64461_PCCSCR_SWP 0x01 /* write protect */ + + +#define HD64461_P0OCR 0x1202a +#define HD64461_P1OCR 0x1202c +#define HD64461_PGCR 0x1202e + +#define HD64461_GPACR 0x14000 +#define HD64461_GPBCR 0x14002 +#define HD64461_GPCCR 0x14004 +#define HD64461_GPDCR 0x14006 +#define HD64461_GPADR 0x14010 +#define HD64461_GPBDR 0x14012 +#define HD64461_GPCDR 0x14014 +#define HD64461_GPDDR 0x14016 +#define HD64461_GPAICR 0x14020 +#define HD64461_GPBICR 0x14022 +#define HD64461_GPCICR 0x14024 +#define HD64461_GPDICR 0x14026 +#define HD64461_GPAISR 0x14040 +#define HD64461_GPBISR 0x14042 +#define HD64461_GPCISR 0x14044 +#define HD64461_GPDISR 0x14046 + +#define HD64461_NIRR 0x15000 +#define HD64461_NIMR 0x15002 + +#ifndef CONFIG_HD64461_IOBASE +#define CONFIG_HD64461_IOBASE 0xb0000000 +#endif +#ifndef CONFIG_HD64461_IRQ +#define CONFIG_HD64461_IRQ 36 +#endif + +#define HD64461_IRQBASE OFFCHIP_IRQ_BASE +#define HD64461_IRQ_NUM 16 + +#define HD64461_IRQ_UART (HD64461_IRQBASE+5) +#define HD64461_IRQ_IRDA (HD64461_IRQBASE+6) +#define HD64461_IRQ_TMU1 (HD64461_IRQBASE+9) +#define HD64461_IRQ_TMU0 (HD64461_IRQBASE+10) +#define HD64461_IRQ_GPIO (HD64461_IRQBASE+11) +#define HD64461_IRQ_AFE (HD64461_IRQBASE+12) +#define HD64461_IRQ_PCC1 (HD64461_IRQBASE+13) +#define HD64461_IRQ_PCC0 (HD64461_IRQBASE+14) + +#endif diff --git a/include/asm-sh/hd64461/io.h b/include/asm-sh/hd64461/io.h new file mode 100644 index 0000000..67f2489 --- /dev/null +++ b/include/asm-sh/hd64461/io.h @@ -0,0 +1,43 @@ +/* + * include/asm-sh/io_hd64461.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an HD64461 + */ + +#ifndef _ASM_SH_IO_HD64461_H +#define _ASM_SH_IO_HD64461_H + +extern unsigned char hd64461_inb(unsigned long port); +extern unsigned short hd64461_inw(unsigned long port); +extern unsigned int hd64461_inl(unsigned long port); + +extern void hd64461_outb(unsigned char value, unsigned long port); +extern void hd64461_outw(unsigned short value, unsigned long port); +extern void hd64461_outl(unsigned int value, unsigned long port); + +extern unsigned char hd64461_inb_p(unsigned long port); +extern void hd64461_outb_p(unsigned char value, unsigned long port); + +extern void hd64461_insb(unsigned long port, void *addr, unsigned long count); +extern void hd64461_insw(unsigned long port, void *addr, unsigned long count); +extern void hd64461_insl(unsigned long port, void *addr, unsigned long count); + +extern void hd64461_outsb(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_outsw(unsigned long port, const void *buffer, unsigned long count); +extern void hd64461_outsl(unsigned long port, const void *buffer, unsigned long count); + +extern unsigned short hd64461_readw(unsigned long addr); +extern void hd64461_writew(unsigned short b, unsigned long addr); + + +extern int hd64461_irq_demux(int irq); +extern void hd64461_register_irq_demux(int irq, + int (*demux)(int irq, void *dev), void *dev); +extern void hd64461_unregister_irq_demux(int irq); + +#endif /* _ASM_SH_IO_HD64461_H */ diff --git a/include/asm-sh/hd64465/gpio.h b/include/asm-sh/hd64465/gpio.h new file mode 100644 index 0000000..a3cdca2 --- /dev/null +++ b/include/asm-sh/hd64465/gpio.h @@ -0,0 +1,46 @@ +#ifndef _ASM_SH_HD64465_GPIO_ +#define _ASM_SH_HD64465_GPIO_ 1 +/* + * $Id: gpio.h,v 1.3 2003/05/04 19:30:14 lethal Exp $ + * + * Hitachi HD64465 companion chip: General Purpose IO pins support. + * This layer enables other device drivers to configure GPIO + * pins, get and set their values, and register an interrupt + * routine for when input pins change in hardware. + * + * by Greg Banks <gbanks@pocketpenguins.com> + * (c) 2000 PocketPenguins Inc. + */ +#include <asm/hd64465.h> + +/* Macro to construct a portpin number (used in all + * subsequent functions) from a port letter and a pin + * number, e.g. HD64465_GPIO_PORTPIN('A', 5). + */ +#define HD64465_GPIO_PORTPIN(port,pin) (((port)-'A')<<3|(pin)) + +/* Pin configuration constants for _configure() */ +#define HD64465_GPIO_FUNCTION2 0 /* use the pin's *other* function */ +#define HD64465_GPIO_OUT 1 /* output */ +#define HD64465_GPIO_IN_PULLUP 2 /* input, pull-up MOS on */ +#define HD64465_GPIO_IN 3 /* input */ + +/* Configure a pin's direction */ +extern void hd64465_gpio_configure(int portpin, int direction); + +/* Get, set value */ +extern void hd64465_gpio_set_pin(int portpin, unsigned int value); +extern unsigned int hd64465_gpio_get_pin(int portpin); +extern void hd64465_gpio_set_port(int port, unsigned int value); +extern unsigned int hd64465_gpio_get_port(int port); + +/* mode constants for _register_irq() */ +#define HD64465_GPIO_FALLING 0 +#define HD64465_GPIO_RISING 1 + +/* Interrupt on external value change */ +extern void hd64465_gpio_register_irq(int portpin, int mode, + void (*handler)(int portpin, void *dev), void *dev); +extern void hd64465_gpio_unregister_irq(int portpin); + +#endif /* _ASM_SH_HD64465_GPIO_ */ diff --git a/include/asm-sh/hd64465/hd64465.h b/include/asm-sh/hd64465/hd64465.h new file mode 100644 index 0000000..c672032 --- /dev/null +++ b/include/asm-sh/hd64465/hd64465.h @@ -0,0 +1,257 @@ +#ifndef _ASM_SH_HD64465_ +#define _ASM_SH_HD64465_ 1 +/* + * $Id: hd64465.h,v 1.3 2003/05/04 19:30:15 lethal Exp $ + * + * Hitachi HD64465 companion chip support + * + * by Greg Banks <gbanks@pocketpenguins.com> + * (c) 2000 PocketPenguins Inc. + * + * Derived from <asm/hd64461.h> which bore the message: + * Copyright (C) 2000 YAEGASHI Takeshi + */ +#include <linux/config.h> +#include <asm/io.h> +#include <asm/irq.h> + +/* + * Note that registers are defined here as virtual port numbers, + * which have no meaning except to get translated by hd64465_isa_port2addr() + * to an address in the range 0xb0000000-0xb3ffffff. Note that + * this translation happens to consist of adding the lower 16 bits + * of the virtual port number to 0xb0000000. Note also that the manual + * shows addresses as absolute physical addresses starting at 0x10000000, + * so e.g. the NIRR register is listed as 0x15000 here, 0x10005000 in the + * manual, and accessed using address 0xb0005000 - Greg. + */ + +/* System registers */ +#define HD64465_REG_SRR 0x1000c /* System Revision Register */ +#define HD64465_REG_SDID 0x10010 /* System Device ID Reg */ +#define HD64465_SDID 0x8122 /* 64465 device ID */ + +/* Power Management registers */ +#define HD64465_REG_SMSCR 0x10000 /* System Module Standby Control Reg */ +#define HD64465_SMSCR_PS2ST 0x4000 /* PS/2 Standby */ +#define HD64465_SMSCR_ADCST 0x1000 /* ADC Standby */ +#define HD64465_SMSCR_UARTST 0x0800 /* UART Standby */ +#define HD64465_SMSCR_SCDIST 0x0200 /* Serial Codec Standby */ +#define HD64465_SMSCR_PPST 0x0100 /* Parallel Port Standby */ +#define HD64465_SMSCR_PC0ST 0x0040 /* PCMCIA0 Standby */ +#define HD64465_SMSCR_PC1ST 0x0020 /* PCMCIA1 Standby */ +#define HD64465_SMSCR_AFEST 0x0010 /* AFE Standby */ +#define HD64465_SMSCR_TM0ST 0x0008 /* Timer0 Standby */ +#define HD64465_SMSCR_TM1ST 0x0004 /* Timer1 Standby */ +#define HD64465_SMSCR_IRDAST 0x0002 /* IRDA Standby */ +#define HD64465_SMSCR_KBCST 0x0001 /* Keyboard Controller Standby */ + +/* Interrupt Controller registers */ +#define HD64465_REG_NIRR 0x15000 /* Interrupt Request Register */ +#define HD64465_REG_NIMR 0x15002 /* Interrupt Mask Register */ +#define HD64465_REG_NITR 0x15004 /* Interrupt Trigger Mode Register */ + +/* Timer registers */ +#define HD64465_REG_TCVR1 0x16000 /* Timer 1 constant value register */ +#define HD64465_REG_TCVR0 0x16002 /* Timer 0 constant value register */ +#define HD64465_REG_TRVR1 0x16004 /* Timer 1 read value register */ +#define HD64465_REG_TRVR0 0x16006 /* Timer 0 read value register */ +#define HD64465_REG_TCR1 0x16008 /* Timer 1 control register */ +#define HD64465_REG_TCR0 0x1600A /* Timer 0 control register */ +#define HD64465_TCR_EADT 0x10 /* Enable ADTRIG# signal */ +#define HD64465_TCR_ETMO 0x08 /* Enable TMO signal */ +#define HD64465_TCR_PST_MASK 0x06 /* Clock Prescale */ +#define HD64465_TCR_PST_1 0x06 /* 1:1 */ +#define HD64465_TCR_PST_4 0x04 /* 1:4 */ +#define HD64465_TCR_PST_8 0x02 /* 1:8 */ +#define HD64465_TCR_PST_16 0x00 /* 1:16 */ +#define HD64465_TCR_TSTP 0x01 /* Start/Stop timer */ +#define HD64465_REG_TIRR 0x1600C /* Timer interrupt request register */ +#define HD64465_REG_TIDR 0x1600E /* Timer interrupt disable register */ +#define HD64465_REG_PWM1CS 0x16010 /* PWM 1 clock scale register */ +#define HD64465_REG_PWM1LPC 0x16012 /* PWM 1 low pulse width counter register */ +#define HD64465_REG_PWM1HPC 0x16014 /* PWM 1 high pulse width counter register */ +#define HD64465_REG_PWM0CS 0x16018 /* PWM 0 clock scale register */ +#define HD64465_REG_PWM0LPC 0x1601A /* PWM 0 low pulse width counter register */ +#define HD64465_REG_PWM0HPC 0x1601C /* PWM 0 high pulse width counter register */ + +/* Analog/Digital Converter registers */ +#define HD64465_REG_ADDRA 0x1E000 /* A/D data register A */ +#define HD64465_REG_ADDRB 0x1E002 /* A/D data register B */ +#define HD64465_REG_ADDRC 0x1E004 /* A/D data register C */ +#define HD64465_REG_ADDRD 0x1E006 /* A/D data register D */ +#define HD64465_REG_ADCSR 0x1E008 /* A/D control/status register */ +#define HD64465_ADCSR_ADF 0x80 /* A/D End Flag */ +#define HD64465_ADCSR_ADST 0x40 /* A/D Start Flag */ +#define HD64465_ADCSR_ADIS 0x20 /* A/D Interrupt Status */ +#define HD64465_ADCSR_TRGE 0x10 /* A/D Trigger Enable */ +#define HD64465_ADCSR_ADIE 0x08 /* A/D Interrupt Enable */ +#define HD64465_ADCSR_SCAN 0x04 /* A/D Scan Mode */ +#define HD64465_ADCSR_CH_MASK 0x03 /* A/D Channel */ +#define HD64465_REG_ADCALCR 0x1E00A /* A/D calibration sample control */ +#define HD64465_REG_ADCAL 0x1E00C /* A/D calibration data register */ + + +/* General Purpose I/O ports registers */ +#define HD64465_REG_GPACR 0x14000 /* Port A Control Register */ +#define HD64465_REG_GPBCR 0x14002 /* Port B Control Register */ +#define HD64465_REG_GPCCR 0x14004 /* Port C Control Register */ +#define HD64465_REG_GPDCR 0x14006 /* Port D Control Register */ +#define HD64465_REG_GPECR 0x14008 /* Port E Control Register */ +#define HD64465_REG_GPADR 0x14010 /* Port A Data Register */ +#define HD64465_REG_GPBDR 0x14012 /* Port B Data Register */ +#define HD64465_REG_GPCDR 0x14014 /* Port C Data Register */ +#define HD64465_REG_GPDDR 0x14016 /* Port D Data Register */ +#define HD64465_REG_GPEDR 0x14018 /* Port E Data Register */ +#define HD64465_REG_GPAICR 0x14020 /* Port A Interrupt Control Register */ +#define HD64465_REG_GPBICR 0x14022 /* Port B Interrupt Control Register */ +#define HD64465_REG_GPCICR 0x14024 /* Port C Interrupt Control Register */ +#define HD64465_REG_GPDICR 0x14026 /* Port D Interrupt Control Register */ +#define HD64465_REG_GPEICR 0x14028 /* Port E Interrupt Control Register */ +#define HD64465_REG_GPAISR 0x14040 /* Port A Interrupt Status Register */ +#define HD64465_REG_GPBISR 0x14042 /* Port B Interrupt Status Register */ +#define HD64465_REG_GPCISR 0x14044 /* Port C Interrupt Status Register */ +#define HD64465_REG_GPDISR 0x14046 /* Port D Interrupt Status Register */ +#define HD64465_REG_GPEISR 0x14048 /* Port E Interrupt Status Register */ + +/* PCMCIA bridge interface */ +#define HD64465_REG_PCC0ISR 0x12000 /* socket 0 interface status */ +#define HD64465_PCCISR_PREADY 0x80 /* mem card ready / io card IREQ */ +#define HD64465_PCCISR_PIREQ 0x80 +#define HD64465_PCCISR_PMWP 0x40 /* mem card write-protected */ +#define HD64465_PCCISR_PVS2 0x20 /* voltage select pin 2 */ +#define HD64465_PCCISR_PVS1 0x10 /* voltage select pin 1 */ +#define HD64465_PCCISR_PCD_MASK 0x0c /* card detect */ +#define HD64465_PCCISR_PBVD_MASK 0x03 /* battery voltage */ +#define HD64465_PCCISR_PBVD_BATGOOD 0x03 /* battery good */ +#define HD64465_PCCISR_PBVD_BATWARN 0x01 /* battery low warning */ +#define HD64465_PCCISR_PBVD_BATDEAD1 0x02 /* battery dead */ +#define HD64465_PCCISR_PBVD_BATDEAD2 0x00 /* battery dead */ +#define HD64465_REG_PCC0GCR 0x12002 /* socket 0 general control */ +#define HD64465_PCCGCR_PDRV 0x80 /* output drive */ +#define HD64465_PCCGCR_PCCR 0x40 /* PC card reset */ +#define HD64465_PCCGCR_PCCT 0x20 /* PC card type, 1=IO&mem, 0=mem */ +#define HD64465_PCCGCR_PVCC0 0x10 /* voltage control pin VCC0SEL0 */ +#define HD64465_PCCGCR_PMMOD 0x08 /* memory mode */ +#define HD64465_PCCGCR_PPA25 0x04 /* pin A25 */ +#define HD64465_PCCGCR_PPA24 0x02 /* pin A24 */ +#define HD64465_PCCGCR_PREG 0x01 /* ping PCC0REG# */ +#define HD64465_REG_PCC0CSCR 0x12004 /* socket 0 card status change */ +#define HD64465_PCCCSCR_PSCDI 0x80 /* sw card detect intr */ +#define HD64465_PCCCSCR_PSWSEL 0x40 /* power select */ +#define HD64465_PCCCSCR_PIREQ 0x20 /* IREQ intr req */ +#define HD64465_PCCCSCR_PSC 0x10 /* STSCHG (status change) pin */ +#define HD64465_PCCCSCR_PCDC 0x08 /* CD (card detect) change */ +#define HD64465_PCCCSCR_PRC 0x04 /* ready change */ +#define HD64465_PCCCSCR_PBW 0x02 /* battery warning change */ +#define HD64465_PCCCSCR_PBD 0x01 /* battery dead change */ +#define HD64465_REG_PCC0CSCIER 0x12006 /* socket 0 card status change interrupt enable */ +#define HD64465_PCCCSCIER_PCRE 0x80 /* change reset enable */ +#define HD64465_PCCCSCIER_PIREQE_MASK 0x60 /* IREQ enable */ +#define HD64465_PCCCSCIER_PIREQE_DISABLED 0x00 /* IREQ disabled */ +#define HD64465_PCCCSCIER_PIREQE_LEVEL 0x20 /* IREQ level-triggered */ +#define HD64465_PCCCSCIER_PIREQE_FALLING 0x40 /* IREQ falling-edge-trig */ +#define HD64465_PCCCSCIER_PIREQE_RISING 0x60 /* IREQ rising-edge-trig */ +#define HD64465_PCCCSCIER_PSCE 0x10 /* status change enable */ +#define HD64465_PCCCSCIER_PCDE 0x08 /* card detect change enable */ +#define HD64465_PCCCSCIER_PRE 0x04 /* ready change enable */ +#define HD64465_PCCCSCIER_PBWE 0x02 /* battery warn change enable */ +#define HD64465_PCCCSCIER_PBDE 0x01 /* battery dead change enable*/ +#define HD64465_REG_PCC0SCR 0x12008 /* socket 0 software control */ +#define HD64465_PCCSCR_SHDN 0x10 /* TPS2206 SHutDowN pin */ +#define HD64465_PCCSCR_SWP 0x01 /* write protect */ +#define HD64465_REG_PCCPSR 0x1200A /* serial power switch control */ +#define HD64465_REG_PCC1ISR 0x12010 /* socket 1 interface status */ +#define HD64465_REG_PCC1GCR 0x12012 /* socket 1 general control */ +#define HD64465_REG_PCC1CSCR 0x12014 /* socket 1 card status change */ +#define HD64465_REG_PCC1CSCIER 0x12016 /* socket 1 card status change interrupt enable */ +#define HD64465_REG_PCC1SCR 0x12018 /* socket 1 software control */ + + +/* PS/2 Keyboard and mouse controller -- *not* register compatible */ +#define HD64465_REG_KBCSR 0x1dc00 /* Keyboard Control/Status reg */ +#define HD64465_KBCSR_KBCIE 0x8000 /* KBCK Input Enable */ +#define HD64465_KBCSR_KBCOE 0x4000 /* KBCK Output Enable */ +#define HD64465_KBCSR_KBDOE 0x2000 /* KB DATA Output Enable */ +#define HD64465_KBCSR_KBCD 0x1000 /* KBCK Driven */ +#define HD64465_KBCSR_KBDD 0x0800 /* KB DATA Driven */ +#define HD64465_KBCSR_KBCS 0x0400 /* KBCK pin Status */ +#define HD64465_KBCSR_KBDS 0x0200 /* KB DATA pin Status */ +#define HD64465_KBCSR_KBDP 0x0100 /* KB DATA Parity bit */ +#define HD64465_KBCSR_KBD_MASK 0x00ff /* KD DATA shift reg */ +#define HD64465_REG_KBISR 0x1dc04 /* Keyboard Interrupt Status reg */ +#define HD64465_KBISR_KBRDF 0x0001 /* KB Received Data Full */ +#define HD64465_REG_MSCSR 0x1dc10 /* Mouse Control/Status reg */ +#define HD64465_REG_MSISR 0x1dc14 /* Mouse Interrupt Status reg */ + + +/* + * Logical address at which the HD64465 is mapped. Note that this + * should always be in the P2 segment (uncached and untranslated). + */ +#ifndef CONFIG_HD64465_IOBASE +#define CONFIG_HD64465_IOBASE 0xb0000000 +#endif +/* + * The HD64465 multiplexes all its modules' interrupts onto + * this single interrupt. + */ +#ifndef CONFIG_HD64465_IRQ +#define CONFIG_HD64465_IRQ 5 +#endif + + +#define _HD64465_IO_MASK 0xf8000000 +#define is_hd64465_addr(addr) \ + ((addr & _HD64465_IO_MASK) == (CONFIG_HD64465_IOBASE & _HD64465_IO_MASK)) + +/* + * A range of 16 virtual interrupts generated by + * demuxing the HD64465 muxed interrupt. + */ +#define HD64465_IRQ_BASE OFFCHIP_IRQ_BASE +#define HD64465_IRQ_NUM 16 +#define HD64465_IRQ_ADC (HD64465_IRQ_BASE+0) +#define HD64465_IRQ_USB (HD64465_IRQ_BASE+1) +#define HD64465_IRQ_SCDI (HD64465_IRQ_BASE+2) +#define HD64465_IRQ_PARALLEL (HD64465_IRQ_BASE+3) +/* bit 4 is reserved */ +#define HD64465_IRQ_UART (HD64465_IRQ_BASE+5) +#define HD64465_IRQ_IRDA (HD64465_IRQ_BASE+6) +#define HD64465_IRQ_PS2MOUSE (HD64465_IRQ_BASE+7) +#define HD64465_IRQ_KBC (HD64465_IRQ_BASE+8) +#define HD64465_IRQ_TIMER1 (HD64465_IRQ_BASE+9) +#define HD64465_IRQ_TIMER0 (HD64465_IRQ_BASE+10) +#define HD64465_IRQ_GPIO (HD64465_IRQ_BASE+11) +#define HD64465_IRQ_AFE (HD64465_IRQ_BASE+12) +#define HD64465_IRQ_PCMCIA1 (HD64465_IRQ_BASE+13) +#define HD64465_IRQ_PCMCIA0 (HD64465_IRQ_BASE+14) +#define HD64465_IRQ_PS2KBD (HD64465_IRQ_BASE+15) + +/* Constants for PCMCIA mappings */ +#define HD64465_PCC_WINDOW 0x01000000 + +#define HD64465_PCC0_BASE 0xb8000000 /* area 6 */ +#define HD64465_PCC0_ATTR (HD64465_PCC0_BASE) +#define HD64465_PCC0_COMM (HD64465_PCC0_BASE+HD64465_PCC_WINDOW) +#define HD64465_PCC0_IO (HD64465_PCC0_BASE+2*HD64465_PCC_WINDOW) + +#define HD64465_PCC1_BASE 0xb4000000 /* area 5 */ +#define HD64465_PCC1_ATTR (HD64465_PCC1_BASE) +#define HD64465_PCC1_COMM (HD64465_PCC1_BASE+HD64465_PCC_WINDOW) +#define HD64465_PCC1_IO (HD64465_PCC1_BASE+2*HD64465_PCC_WINDOW) + +/* + * Base of USB controller interface (as memory) + */ +#define HD64465_USB_BASE (CONFIG_HD64465_IOBASE+0xb000) +#define HD64465_USB_LEN 0x1000 +/* + * Base of embedded SRAM, used for USB controller. + */ +#define HD64465_SRAM_BASE (CONFIG_HD64465_IOBASE+0x9000) +#define HD64465_SRAM_LEN 0x1000 + + + +#endif /* _ASM_SH_HD64465_ */ diff --git a/include/asm-sh/hd64465/io.h b/include/asm-sh/hd64465/io.h new file mode 100644 index 0000000..1100bcf --- /dev/null +++ b/include/asm-sh/hd64465/io.h @@ -0,0 +1,44 @@ +/* + * include/asm-sh/io_hd64465.h + * + * By Greg Banks <gbanks@pocketpenguins.com> + * (c) 2000 PocketPenguins Inc. + * + * Derived from io_hd64461.h, which bore the message: + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an HD64465 "Windows CE Intelligent Peripheral Controller". + */ + +#ifndef _ASM_SH_IO_HD64465_H +#define _ASM_SH_IO_HD64465_H + +extern unsigned char hd64465_inb(unsigned long port); +extern unsigned short hd64465_inw(unsigned long port); +extern unsigned int hd64465_inl(unsigned long port); + +extern void hd64465_outb(unsigned char value, unsigned long port); +extern void hd64465_outw(unsigned short value, unsigned long port); +extern void hd64465_outl(unsigned int value, unsigned long port); + +extern unsigned char hd64465_inb_p(unsigned long port); +extern void hd64465_outb_p(unsigned char value, unsigned long port); + +extern unsigned long hd64465_isa_port2addr(unsigned long offset); +extern int hd64465_irq_demux(int irq); +/* Provision for generic secondary demux step -- used by PCMCIA code */ +extern void hd64465_register_irq_demux(int irq, + int (*demux)(int irq, void *dev), void *dev); +extern void hd64465_unregister_irq_demux(int irq); +/* Set this variable to 1 to see port traffic */ +extern int hd64465_io_debug; +/* Map a range of ports to a range of kernel virtual memory. + */ +extern void hd64465_port_map(unsigned short baseport, unsigned int nports, + unsigned long addr, unsigned char shift); +extern void hd64465_port_unmap(unsigned short baseport, unsigned int nports); + +#endif /* _ASM_SH_IO_HD64465_H */ diff --git a/include/asm-sh/hdreg.h b/include/asm-sh/hdreg.h new file mode 100644 index 0000000..7f7fd1a --- /dev/null +++ b/include/asm-sh/hdreg.h @@ -0,0 +1 @@ +#include <asm-generic/hdreg.h> diff --git a/include/asm-sh/hp6xx/hp6xx.h b/include/asm-sh/hp6xx/hp6xx.h new file mode 100644 index 0000000..a26247f --- /dev/null +++ b/include/asm-sh/hp6xx/hp6xx.h @@ -0,0 +1,31 @@ +#ifndef __ASM_SH_HP6XX_H +#define __ASM_SH_HP6XX_H + +/* + * Copyright (C) 2003 Andriy Skulysh + */ + +#define HP680_TS_IRQ IRQ3_IRQ + +#define DAC_LCD_BRIGHTNESS 0 +#define DAC_SPEAKER_VOLUME 1 + +#define PHDR_TS_PEN_DOWN 0x08 + +#define SCPDR_TS_SCAN_ENABLE 0x20 +#define SCPDR_TS_SCAN_Y 0x02 +#define SCPDR_TS_SCAN_X 0x01 + +#define SCPCR_TS_ENABLE 0x405 +#define SCPCR_TS_MASK 0xc0f + +#define ADC_CHANNEL_TS_Y 1 +#define ADC_CHANNEL_TS_X 2 + +#define HD64461_GPADR_SPEAKER 0x01 +#define HD64461_GPADR_PCMCIA0 (0x02|0x08) +#define HD64461_GPBDR_LCDOFF 0x01 +#define HD64461_GPBDR_LED_RED 0x80 + + +#endif /* __ASM_SH_HP6XX_H */ diff --git a/include/asm-sh/hp6xx/ide.h b/include/asm-sh/hp6xx/ide.h new file mode 100644 index 0000000..570395a --- /dev/null +++ b/include/asm-sh/hp6xx/ide.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_HP6XX_IDE_H +#define __ASM_SH_HP6XX_IDE_H + +#define IRQ_CFCARD 93 +#define IRQ_PCMCIA 94 + +#endif /* __ASM_SH_HP6XX_IDE_H */ + diff --git a/include/asm-sh/hp6xx/io.h b/include/asm-sh/hp6xx/io.h new file mode 100644 index 0000000..7317980 --- /dev/null +++ b/include/asm-sh/hp6xx/io.h @@ -0,0 +1,10 @@ +#ifndef __ASM_SH_HP6XX_IO_H +#define __ASM_SH_HP6XX_IO_H + +/* + * Nothing special here.. just use the generic cchip io routines. + */ +#include <asm/hd64461/io.h> + +#endif /* __ASM_SH_HP6XX_IO_H */ + diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h new file mode 100644 index 0000000..5f995f9 --- /dev/null +++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h @@ -0,0 +1,47 @@ +#ifndef __ASM_SH_RENESAS_HS7751RVOIP_H +#define __ASM_SH_RENESAS_HS7751RVOIP_H + +/* + * linux/include/asm-sh/hs7751rvoip/hs7751rvoip.h + * + * Copyright (C) 2000 Atom Create Engineering Co., Ltd. + * + * Renesas Technology Sales HS7751RVoIP support + */ + +/* Box specific addresses. */ + +#define PA_BCR 0xa4000000 /* FPGA */ +#define PA_SLICCNTR1 0xa4000006 /* SLIC PIO Control 1 */ +#define PA_SLICCNTR2 0xa4000008 /* SLIC PIO Control 2 */ +#define PA_DMACNTR 0xa400000a /* USB DMA Control */ +#define PA_INPORTR 0xa400000c /* Input Port Register */ +#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */ +#define PA_VERREG 0xa4000014 /* FPGA Version Register */ + +#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ +#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ +#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ + +#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ +#define IRLCNTR2 (PA_BCR + 2) /* Interrupt Control Register2 */ +#define IRLCNTR3 (PA_BCR + 4) /* Interrupt Control Register3 */ +#define IRLCNTR4 (PA_BCR + 16) /* Interrupt Control Register4 */ +#define IRLCNTR5 (PA_BCR + 18) /* Interrupt Control Register5 */ + +#define IRQ_PCIETH 6 /* PCI Ethernet IRQ */ +#define IRQ_PCIHUB 7 /* PCI Ethernet Hub IRQ */ +#define IRQ_USBCOM 8 /* USB Comunication IRQ */ +#define IRQ_USBCON 9 /* USB Connect IRQ */ +#define IRQ_USBDMA 10 /* USB DMA IRQ */ +#define IRQ_CFCARD 11 /* CF Card IRQ */ +#define IRQ_PCMCIA 12 /* PCMCIA IRQ */ +#define IRQ_PCISLOT 13 /* PCI Slot #1 IRQ */ +#define IRQ_ONHOOK1 0 /* ON HOOK1 IRQ */ +#define IRQ_OFFHOOK1 1 /* OFF HOOK1 IRQ */ +#define IRQ_ONHOOK2 2 /* ON HOOK2 IRQ */ +#define IRQ_OFFHOOK2 3 /* OFF HOOK2 IRQ */ +#define IRQ_RINGING 4 /* Ringing IRQ */ +#define IRQ_CODEC 5 /* CODEC IRQ */ + +#endif /* __ASM_SH_RENESAS_HS7751RVOIP */ diff --git a/include/asm-sh/hs7751rvoip/ide.h b/include/asm-sh/hs7751rvoip/ide.h new file mode 100644 index 0000000..65ad1d0 --- /dev/null +++ b/include/asm-sh/hs7751rvoip/ide.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_HS7751RVOIP_IDE_H +#define __ASM_SH_HS7751RVOIP_IDE_H + +/* Nothing to see here.. */ +#include <asm/hs7751rvoip/hs7751rvoip.h> + +#endif /* __ASM_SH_HS7751RVOIP_IDE_H */ + diff --git a/include/asm-sh/hs7751rvoip/io.h b/include/asm-sh/hs7751rvoip/io.h new file mode 100644 index 0000000..513c851 --- /dev/null +++ b/include/asm-sh/hs7751rvoip/io.h @@ -0,0 +1,39 @@ +/* + * include/asm-sh/hs7751rvoip/hs7751rvoip.h + * + * Modified version of io_se.h for the hs7751rvoip-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Renesas Technology sales HS7751RVOIP + */ + +#ifndef _ASM_SH_IO_HS7751RVOIP_H +#define _ASM_SH_IO_HS7751RVOIP_H + +#include <asm/io_generic.h> + +extern unsigned char hs7751rvoip_inb(unsigned long port); +extern unsigned short hs7751rvoip_inw(unsigned long port); +extern unsigned int hs7751rvoip_inl(unsigned long port); + +extern void hs7751rvoip_outb(unsigned char value, unsigned long port); +extern void hs7751rvoip_outw(unsigned short value, unsigned long port); +extern void hs7751rvoip_outl(unsigned int value, unsigned long port); + +extern unsigned char hs7751rvoip_inb_p(unsigned long port); +extern void hs7751rvoip_outb_p(unsigned char value, unsigned long port); + +extern void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count); +extern void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count); +extern void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count); +extern void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count); +extern void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count); +extern void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count); + +extern void *hs7751rvoip_ioremap(unsigned long offset, unsigned long size); + +extern unsigned long hs7751rvoip_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_HS7751RVOIP_H */ diff --git a/include/asm-sh/hw_irq.h b/include/asm-sh/hw_irq.h new file mode 100644 index 0000000..1d934fb --- /dev/null +++ b/include/asm-sh/hw_irq.h @@ -0,0 +1,9 @@ +#ifndef __ASM_SH_HW_IRQ_H +#define __ASM_SH_HW_IRQ_H + +static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) +{ + /* Nothing to do */ +} + +#endif /* __ASM_SH_HW_IRQ_H */ diff --git a/include/asm-sh/ide.h b/include/asm-sh/ide.h new file mode 100644 index 0000000..f42cf39 --- /dev/null +++ b/include/asm-sh/ide.h @@ -0,0 +1,29 @@ +/* + * linux/include/asm-sh/ide.h + * + * Copyright (C) 1994-1996 Linus Torvalds & authors + */ + +/* + * This file contains the i386 architecture specific IDE code. + * In future, SuperH code. + */ + +#ifndef __ASM_SH_IDE_H +#define __ASM_SH_IDE_H + +#ifdef __KERNEL__ + +#include <linux/config.h> + +#ifndef MAX_HWIFS +#define MAX_HWIFS CONFIG_IDE_MAX_HWIFS +#endif + +#define ide_default_io_ctl(base) (0) + +#include <asm-generic/ide_iops.h> + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_IDE_H */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h new file mode 100644 index 0000000..6bc343fe --- /dev/null +++ b/include/asm-sh/io.h @@ -0,0 +1,311 @@ +#ifndef __ASM_SH_IO_H +#define __ASM_SH_IO_H + +/* + * Convention: + * read{b,w,l}/write{b,w,l} are for PCI, + * while in{b,w,l}/out{b,w,l} are for ISA + * These may (will) be platform specific function. + * In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p + * and 'string' versions: ins{b,w,l}/outs{b,w,l} + * For read{b,w,l} and write{b,w,l} there are also __raw versions, which + * do not have a memory barrier after them. + * + * In addition, we have + * ctrl_in{b,w,l}/ctrl_out{b,w,l} for SuperH specific I/O. + * which are processor specific. + */ + +/* + * We follow the Alpha convention here: + * __inb expands to an inline function call (which calls via the mv) + * _inb is a real function call (note ___raw fns are _ version of __raw) + * inb by default expands to _inb, but the machine specific code may + * define it to __inb if it chooses. + */ + +#include <asm/cache.h> +#include <asm/system.h> +#include <asm/addrspace.h> +#include <asm/machvec.h> +#include <linux/config.h> + +/* + * Depending on which platform we are running on, we need different + * I/O functions. + */ + +#ifdef __KERNEL__ +/* + * Since boards are able to define their own set of I/O routines through + * their respective machine vector, we always wrap through the mv. + * + * Also, in the event that a board hasn't provided its own definition for + * a given routine, it will be wrapped to generic code at run-time. + */ + +# define __inb(p) sh_mv.mv_inb((p)) +# define __inw(p) sh_mv.mv_inw((p)) +# define __inl(p) sh_mv.mv_inl((p)) +# define __outb(x,p) sh_mv.mv_outb((x),(p)) +# define __outw(x,p) sh_mv.mv_outw((x),(p)) +# define __outl(x,p) sh_mv.mv_outl((x),(p)) + +# define __inb_p(p) sh_mv.mv_inb_p((p)) +# define __inw_p(p) sh_mv.mv_inw_p((p)) +# define __inl_p(p) sh_mv.mv_inl_p((p)) +# define __outb_p(x,p) sh_mv.mv_outb_p((x),(p)) +# define __outw_p(x,p) sh_mv.mv_outw_p((x),(p)) +# define __outl_p(x,p) sh_mv.mv_outl_p((x),(p)) + +# define __insb(p,b,c) sh_mv.mv_insb((p), (b), (c)) +# define __insw(p,b,c) sh_mv.mv_insw((p), (b), (c)) +# define __insl(p,b,c) sh_mv.mv_insl((p), (b), (c)) +# define __outsb(p,b,c) sh_mv.mv_outsb((p), (b), (c)) +# define __outsw(p,b,c) sh_mv.mv_outsw((p), (b), (c)) +# define __outsl(p,b,c) sh_mv.mv_outsl((p), (b), (c)) + +# define __readb(a) sh_mv.mv_readb((a)) +# define __readw(a) sh_mv.mv_readw((a)) +# define __readl(a) sh_mv.mv_readl((a)) +# define __writeb(v,a) sh_mv.mv_writeb((v),(a)) +# define __writew(v,a) sh_mv.mv_writew((v),(a)) +# define __writel(v,a) sh_mv.mv_writel((v),(a)) + +# define __ioremap(a,s) sh_mv.mv_ioremap((a), (s)) +# define __iounmap(a) sh_mv.mv_iounmap((a)) + +# define __isa_port2addr(a) sh_mv.mv_isa_port2addr(a) + +# define inb __inb +# define inw __inw +# define inl __inl +# define outb __outb +# define outw __outw +# define outl __outl + +# define inb_p __inb_p +# define inw_p __inw_p +# define inl_p __inl_p +# define outb_p __outb_p +# define outw_p __outw_p +# define outl_p __outl_p + +# define insb __insb +# define insw __insw +# define insl __insl +# define outsb __outsb +# define outsw __outsw +# define outsl __outsl + +# define __raw_readb __readb +# define __raw_readw __readw +# define __raw_readl __readl +# define __raw_writeb __writeb +# define __raw_writew __writew +# define __raw_writel __writel + +/* + * The platform header files may define some of these macros to use + * the inlined versions where appropriate. These macros may also be + * redefined by userlevel programs. + */ +#ifdef __raw_readb +# define readb(a) ({ unsigned long r_ = __raw_readb((unsigned long)a); mb(); r_; }) +#endif +#ifdef __raw_readw +# define readw(a) ({ unsigned long r_ = __raw_readw((unsigned long)a); mb(); r_; }) +#endif +#ifdef __raw_readl +# define readl(a) ({ unsigned long r_ = __raw_readl((unsigned long)a); mb(); r_; }) +#endif + +#ifdef __raw_writeb +# define writeb(v,a) ({ __raw_writeb((v),(unsigned long)(a)); mb(); }) +#endif +#ifdef __raw_writew +# define writew(v,a) ({ __raw_writew((v),(unsigned long)(a)); mb(); }) +#endif +#ifdef __raw_writel +# define writel(v,a) ({ __raw_writel((v),(unsigned long)(a)); mb(); }) +#endif + +#define readb_relaxed(a) readb(a) +#define readw_relaxed(a) readw(a) +#define readl_relaxed(a) readl(a) + +#define mmiowb() + +/* + * If the platform has PC-like I/O, this function converts the offset into + * an address. + */ +static __inline__ unsigned long isa_port2addr(unsigned long offset) +{ + return __isa_port2addr(offset); +} + +/* + * This function provides a method for the generic case where a board-specific + * isa_port2addr simply needs to return the port + some arbitrary port base. + * + * We use this at board setup time to implicitly set the port base, and + * as a result, we can use the generic isa_port2addr. + */ +static inline void __set_io_port_base(unsigned long pbase) +{ + extern unsigned long generic_io_base; + + generic_io_base = pbase; +} + +#define isa_readb(a) readb(isa_port2addr(a)) +#define isa_readw(a) readw(isa_port2addr(a)) +#define isa_readl(a) readl(isa_port2addr(a)) +#define isa_writeb(b,a) writeb(b,isa_port2addr(a)) +#define isa_writew(w,a) writew(w,isa_port2addr(a)) +#define isa_writel(l,a) writel(l,isa_port2addr(a)) +#define isa_memset_io(a,b,c) \ + memset((void *)(isa_port2addr((unsigned long)a)),(b),(c)) +#define isa_memcpy_fromio(a,b,c) \ + memcpy((a),(void *)(isa_port2addr((unsigned long)(b))),(c)) +#define isa_memcpy_toio(a,b,c) \ + memcpy((void *)(isa_port2addr((unsigned long)(a))),(b),(c)) + +/* We really want to try and get these to memcpy etc */ +extern void memcpy_fromio(void *, unsigned long, unsigned long); +extern void memcpy_toio(unsigned long, const void *, unsigned long); +extern void memset_io(unsigned long, int, unsigned long); + +/* SuperH on-chip I/O functions */ +static __inline__ unsigned char ctrl_inb(unsigned long addr) +{ + return *(volatile unsigned char*)addr; +} + +static __inline__ unsigned short ctrl_inw(unsigned long addr) +{ + return *(volatile unsigned short*)addr; +} + +static __inline__ unsigned int ctrl_inl(unsigned long addr) +{ + return *(volatile unsigned long*)addr; +} + +static __inline__ void ctrl_outb(unsigned char b, unsigned long addr) +{ + *(volatile unsigned char*)addr = b; +} + +static __inline__ void ctrl_outw(unsigned short b, unsigned long addr) +{ + *(volatile unsigned short*)addr = b; +} + +static __inline__ void ctrl_outl(unsigned int b, unsigned long addr) +{ + *(volatile unsigned long*)addr = b; +} + +#define IO_SPACE_LIMIT 0xffffffff + +/* + * Change virtual addresses to physical addresses and vv. + * These are trivial on the 1:1 Linux/SuperH mapping + */ +static __inline__ unsigned long virt_to_phys(volatile void * address) +{ + return PHYSADDR(address); +} + +static __inline__ void * phys_to_virt(unsigned long address) +{ + return (void *)P1SEGADDR(address); +} + +#define virt_to_bus virt_to_phys +#define bus_to_virt phys_to_virt +#define page_to_bus page_to_phys + +/* + * readX/writeX() are used to access memory mapped devices. On some + * architectures the memory mapped IO stuff needs to be accessed + * differently. On the x86 architecture, we just read/write the + * memory location directly. + * + * On SH, we have the whole physical address space mapped at all times + * (as MIPS does), so "ioremap()" and "iounmap()" do not need to do + * anything. (This isn't true for all machines but we still handle + * these cases with wired TLB entries anyway ...) + * + * We cheat a bit and always return uncachable areas until we've fixed + * the drivers to handle caching properly. + */ +static __inline__ void * ioremap(unsigned long offset, unsigned long size) +{ + return __ioremap(offset, size); +} + +static __inline__ void iounmap(void *addr) +{ + return __iounmap(addr); +} + +#define ioremap_nocache(off,size) ioremap(off,size) + +static __inline__ int check_signature(unsigned long io_addr, + const unsigned char *signature, int length) +{ + int retval = 0; + do { + if (readb(io_addr) != *signature) + goto out; + io_addr++; + signature++; + length--; + } while (length); + retval = 1; +out: + return retval; +} + +/* + * The caches on some architectures aren't dma-coherent and have need to + * handle this in software. There are three types of operations that + * can be applied to dma buffers. + * + * - dma_cache_wback_inv(start, size) makes caches and RAM coherent by + * writing the content of the caches back to memory, if necessary. + * The function also invalidates the affected part of the caches as + * necessary before DMA transfers from outside to memory. + * - dma_cache_inv(start, size) invalidates the affected parts of the + * caches. Dirty lines of the caches may be written back or simply + * be discarded. This operation is necessary before dma operations + * to the memory. + * - dma_cache_wback(start, size) writes back any dirty lines but does + * not invalidate the cache. This can be used before DMA reads from + * memory, + */ + +#define dma_cache_wback_inv(_start,_size) \ + __flush_purge_region(_start,_size) +#define dma_cache_inv(_start,_size) \ + __flush_invalidate_region(_start,_size) +#define dma_cache_wback(_start,_size) \ + __flush_wback_region(_start,_size) + +/* + * Convert a physical pointer to a virtual kernel pointer for /dev/mem + * access + */ +#define xlate_dev_mem_ptr(p) __va(p) + +/* + * Convert a virtual cached pointer to an uncached pointer + */ +#define xlate_dev_kmem_ptr(p) p + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/io_generic.h b/include/asm-sh/io_generic.h new file mode 100644 index 0000000..be14587 --- /dev/null +++ b/include/asm-sh/io_generic.h @@ -0,0 +1,51 @@ +/* + * include/asm-sh/io_generic.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Generic IO functions + */ + +#ifndef _ASM_SH_IO_GENERIC_H +#define _ASM_SH_IO_GENERIC_H + +extern unsigned long generic_io_base; + +extern unsigned char generic_inb(unsigned long port); +extern unsigned short generic_inw(unsigned long port); +extern unsigned int generic_inl(unsigned long port); + +extern void generic_outb(unsigned char value, unsigned long port); +extern void generic_outw(unsigned short value, unsigned long port); +extern void generic_outl(unsigned int value, unsigned long port); + +extern unsigned char generic_inb_p(unsigned long port); +extern unsigned short generic_inw_p(unsigned long port); +extern unsigned int generic_inl_p(unsigned long port); +extern void generic_outb_p(unsigned char value, unsigned long port); +extern void generic_outw_p(unsigned short value, unsigned long port); +extern void generic_outl_p(unsigned int value, unsigned long port); + +extern void generic_insb(unsigned long port, void *addr, unsigned long count); +extern void generic_insw(unsigned long port, void *addr, unsigned long count); +extern void generic_insl(unsigned long port, void *addr, unsigned long count); +extern void generic_outsb(unsigned long port, const void *addr, unsigned long count); +extern void generic_outsw(unsigned long port, const void *addr, unsigned long count); +extern void generic_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned char generic_readb(unsigned long addr); +extern unsigned short generic_readw(unsigned long addr); +extern unsigned int generic_readl(unsigned long addr); +extern void generic_writeb(unsigned char b, unsigned long addr); +extern void generic_writew(unsigned short b, unsigned long addr); +extern void generic_writel(unsigned int b, unsigned long addr); + +extern void *generic_ioremap(unsigned long offset, unsigned long size); +extern void generic_iounmap(void *addr); + +extern unsigned long generic_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_GENERIC_H */ diff --git a/include/asm-sh/ioctl.h b/include/asm-sh/ioctl.h new file mode 100644 index 0000000..524700e --- /dev/null +++ b/include/asm-sh/ioctl.h @@ -0,0 +1,75 @@ +/* $Id: ioctl.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $ + * + * linux/ioctl.h for Linux by H.H. Bergman. + */ + +#ifndef __ASM_SH_IOCTL_H +#define __ASM_SH_IOCTL_H + +/* ioctl command encoding: 32 bits total, command in lower 16 bits, + * size of the parameter structure in the lower 14 bits of the + * upper 16 bits. + * Encoding the size of the parameter structure in the ioctl request + * is useful for catching programs compiled with old versions + * and to avoid overwriting user space outside the user buffer area. + * The highest 2 bits are reserved for indicating the ``access mode''. + * NOTE: This limits the max parameter size to 16kB -1 ! + */ + +/* + * The following is for compatibility across the various Linux + * platforms. The i386 ioctl numbering scheme doesn't really enforce + * a type field. De facto, however, the top 8 bits of the lower 16 + * bits are indeed used as a type field, so we might just as well make + * this explicit here. Please be sure to use the decoding macros + * below from now on. + */ +#define _IOC_NRBITS 8 +#define _IOC_TYPEBITS 8 +#define _IOC_SIZEBITS 14 +#define _IOC_DIRBITS 2 + +#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1) +#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1) +#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1) +#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1) + +#define _IOC_NRSHIFT 0 +#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS) +#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS) +#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS) + +/* + * Direction bits. + */ +#define _IOC_NONE 0U +#define _IOC_WRITE 1U +#define _IOC_READ 2U + +#define _IOC(dir,type,nr,size) \ + (((dir) << _IOC_DIRSHIFT) | \ + ((type) << _IOC_TYPESHIFT) | \ + ((nr) << _IOC_NRSHIFT) | \ + ((size) << _IOC_SIZESHIFT)) + +/* used to create numbers */ +#define _IO(type,nr) _IOC(_IOC_NONE,(type),(nr),0) +#define _IOR(type,nr,size) _IOC(_IOC_READ,(type),(nr),sizeof(size)) +#define _IOW(type,nr,size) _IOC(_IOC_WRITE,(type),(nr),sizeof(size)) +#define _IOWR(type,nr,size) _IOC(_IOC_READ|_IOC_WRITE,(type),(nr),sizeof(size)) + +/* used to decode ioctl numbers.. */ +#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK) +#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK) +#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK) +#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK) + +/* ...and for the drivers/sound files... */ + +#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT) +#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT) +#define IOC_INOUT ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT) +#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT) +#define IOCSIZE_SHIFT (_IOC_SIZESHIFT) + +#endif /* __ASM_SH_IOCTL_H */ diff --git a/include/asm-sh/ioctls.h b/include/asm-sh/ioctls.h new file mode 100644 index 0000000..1866f3f --- /dev/null +++ b/include/asm-sh/ioctls.h @@ -0,0 +1,99 @@ +#ifndef __ASM_SH_IOCTLS_H +#define __ASM_SH_IOCTLS_H + +#include <asm/ioctl.h> + +#define FIOCLEX _IO('f', 1) +#define FIONCLEX _IO('f', 2) +#define FIOASYNC _IOW('f', 125, int) +#define FIONBIO _IOW('f', 126, int) +#define FIONREAD _IOR('f', 127, int) +#define TIOCINQ FIONREAD +#define FIOQSIZE _IOR('f', 128, loff_t) + +#define TCGETS 0x5401 +#define TCSETS 0x5402 +#define TCSETSW 0x5403 +#define TCSETSF 0x5404 + +#define TCGETA _IOR('t', 23, struct termio) +#define TCSETA _IOW('t', 24, struct termio) +#define TCSETAW _IOW('t', 25, struct termio) +#define TCSETAF _IOW('t', 28, struct termio) + +#define TCSBRK _IO('t', 29) +#define TCXONC _IO('t', 30) +#define TCFLSH _IO('t', 31) + +#define TIOCSWINSZ _IOW('t', 103, struct winsize) +#define TIOCGWINSZ _IOR('t', 104, struct winsize) +#define TIOCSTART _IO('t', 110) /* start output, like ^Q */ +#define TIOCSTOP _IO('t', 111) /* stop output, like ^S */ +#define TIOCOUTQ _IOR('t', 115, int) /* output queue size */ + +#define TIOCSPGRP _IOW('t', 118, int) +#define TIOCGPGRP _IOR('t', 119, int) + +#define TIOCEXCL _IO('T', 12) /* 0x540C */ +#define TIOCNXCL _IO('T', 13) /* 0x540D */ +#define TIOCSCTTY _IO('T', 14) /* 0x540E */ + +#define TIOCSTI _IOW('T', 18, char) /* 0x5412 */ +#define TIOCMGET _IOR('T', 21, unsigned int) /* 0x5415 */ +#define TIOCMBIS _IOW('T', 22, unsigned int) /* 0x5416 */ +#define TIOCMBIC _IOW('T', 23, unsigned int) /* 0x5417 */ +#define TIOCMSET _IOW('T', 24, unsigned int) /* 0x5418 */ +# define TIOCM_LE 0x001 +# define TIOCM_DTR 0x002 +# define TIOCM_RTS 0x004 +# define TIOCM_ST 0x008 +# define TIOCM_SR 0x010 +# define TIOCM_CTS 0x020 +# define TIOCM_CAR 0x040 +# define TIOCM_RNG 0x080 +# define TIOCM_DSR 0x100 +# define TIOCM_CD TIOCM_CAR +# define TIOCM_RI TIOCM_RNG + +#define TIOCGSOFTCAR _IOR('T', 25, unsigned int) /* 0x5419 */ +#define TIOCSSOFTCAR _IOW('T', 26, unsigned int) /* 0x541A */ +#define TIOCLINUX _IOW('T', 28, char) /* 0x541C */ +#define TIOCCONS _IO('T', 29) /* 0x541D */ +#define TIOCGSERIAL _IOR('T', 30, struct serial_struct) /* 0x541E */ +#define TIOCSSERIAL _IOW('T', 31, struct serial_struct) /* 0x541F */ +#define TIOCPKT _IOW('T', 32, int) /* 0x5420 */ +# define TIOCPKT_DATA 0 +# define TIOCPKT_FLUSHREAD 1 +# define TIOCPKT_FLUSHWRITE 2 +# define TIOCPKT_STOP 4 +# define TIOCPKT_START 8 +# define TIOCPKT_NOSTOP 16 +# define TIOCPKT_DOSTOP 32 + + +#define TIOCNOTTY _IO('T', 34) /* 0x5422 */ +#define TIOCSETD _IOW('T', 35, int) /* 0x5423 */ +#define TIOCGETD _IOR('T', 36, int) /* 0x5424 */ +#define TCSBRKP _IOW('T', 37, int) /* 0x5425 */ /* Needed for POSIX tcsendbreak() */ +#define TIOCSBRK _IO('T', 39) /* 0x5427 */ /* BSD compatibility */ +#define TIOCCBRK _IO('T', 40) /* 0x5428 */ /* BSD compatibility */ +#define TIOCGSID _IOR('T', 41, pid_t) /* 0x5429 */ /* Return the session ID of FD */ +#define TIOCGPTN _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */ +#define TIOCSPTLCK _IOW('T',0x31, int) /* Lock/unlock Pty */ + +#define TIOCSERCONFIG _IO('T', 83) /* 0x5453 */ +#define TIOCSERGWILD _IOR('T', 84, int) /* 0x5454 */ +#define TIOCSERSWILD _IOW('T', 85, int) /* 0x5455 */ +#define TIOCGLCKTRMIOS 0x5456 +#define TIOCSLCKTRMIOS 0x5457 +#define TIOCSERGSTRUCT _IOR('T', 88, struct async_struct) /* 0x5458 */ /* For debugging only */ +#define TIOCSERGETLSR _IOR('T', 89, unsigned int) /* 0x5459 */ /* Get line status register */ + /* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ +# define TIOCSER_TEMT 0x01 /* Transmitter physically empty */ +#define TIOCSERGETMULTI _IOR('T', 90, struct serial_multiport_struct) /* 0x545A */ /* Get multiport config */ +#define TIOCSERSETMULTI _IOW('T', 91, struct serial_multiport_struct) /* 0x545B */ /* Set multiport config */ + +#define TIOCMIWAIT _IO('T', 92) /* 0x545C */ /* wait for a change on serial input line(s) */ +#define TIOCGICOUNT _IOR('T', 93, struct async_icount) /* 0x545D */ /* read serial port inline interrupt counts */ + +#endif /* __ASM_SH_IOCTLS_H */ diff --git a/include/asm-sh/ipc.h b/include/asm-sh/ipc.h new file mode 100644 index 0000000..a46e3d9 --- /dev/null +++ b/include/asm-sh/ipc.h @@ -0,0 +1 @@ +#include <asm-generic/ipc.h> diff --git a/include/asm-sh/ipcbuf.h b/include/asm-sh/ipcbuf.h new file mode 100644 index 0000000..5ffc997 --- /dev/null +++ b/include/asm-sh/ipcbuf.h @@ -0,0 +1,29 @@ +#ifndef __ASM_SH_IPCBUF_H__ +#define __ASM_SH_IPCBUF_H__ + +/* + * The ipc64_perm structure for i386 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 32-bit mode_t and seq + * - 2 miscellaneous 32-bit values + */ + +struct ipc64_perm +{ + __kernel_key_t key; + __kernel_uid32_t uid; + __kernel_gid32_t gid; + __kernel_uid32_t cuid; + __kernel_gid32_t cgid; + __kernel_mode_t mode; + unsigned short __pad1; + unsigned short seq; + unsigned short __pad2; + unsigned long __unused1; + unsigned long __unused2; +}; + +#endif /* __ASM_SH_IPCBUF_H__ */ diff --git a/include/asm-sh/irq-sh73180.h b/include/asm-sh/irq-sh73180.h new file mode 100644 index 0000000..bf2e431 --- /dev/null +++ b/include/asm-sh/irq-sh73180.h @@ -0,0 +1,350 @@ +#ifndef __ASM_SH_IRQ_SH73180_H +#define __ASM_SH_IRQ_SH73180_H + +/* + * linux/include/asm-sh/irq-sh73180.h + * + * Copyright (C) 2004 Takashi SHUDO <shudo@hitachi-ul.co.jp> + */ + +#undef INTC_IPRA +#undef INTC_IPRB +#undef INTC_IPRC +#undef INTC_IPRD + +#undef DMTE0_IRQ +#undef DMTE1_IRQ +#undef DMTE2_IRQ +#undef DMTE3_IRQ +#undef DMTE4_IRQ +#undef DMTE5_IRQ +#undef DMTE6_IRQ +#undef DMTE7_IRQ +#undef DMAE_IRQ +#undef DMA_IPR_ADDR +#undef DMA_IPR_POS +#undef DMA_PRIORITY + +#undef NR_IRQS + +#undef __irq_demux +#undef irq_demux + +#undef INTC_IMCR0 +#undef INTC_IMCR1 +#undef INTC_IMCR2 +#undef INTC_IMCR3 +#undef INTC_IMCR4 +#undef INTC_IMCR5 +#undef INTC_IMCR6 +#undef INTC_IMCR7 +#undef INTC_IMCR8 +#undef INTC_IMCR9 +#undef INTC_IMCR10 + + +#define INTC_IPRA 0xA4080000UL +#define INTC_IPRB 0xA4080004UL +#define INTC_IPRC 0xA4080008UL +#define INTC_IPRD 0xA408000CUL +#define INTC_IPRE 0xA4080010UL +#define INTC_IPRF 0xA4080014UL +#define INTC_IPRG 0xA4080018UL +#define INTC_IPRH 0xA408001CUL +#define INTC_IPRI 0xA4080020UL +#define INTC_IPRJ 0xA4080024UL +#define INTC_IPRK 0xA4080028UL + +#define INTC_IMR0 0xA4080080UL +#define INTC_IMR1 0xA4080084UL +#define INTC_IMR2 0xA4080088UL +#define INTC_IMR3 0xA408008CUL +#define INTC_IMR4 0xA4080090UL +#define INTC_IMR5 0xA4080094UL +#define INTC_IMR6 0xA4080098UL +#define INTC_IMR7 0xA408009CUL +#define INTC_IMR8 0xA40800A0UL +#define INTC_IMR9 0xA40800A4UL +#define INTC_IMR10 0xA40800A8UL +#define INTC_IMR11 0xA40800ACUL + +#define INTC_IMCR0 0xA40800C0UL +#define INTC_IMCR1 0xA40800C4UL +#define INTC_IMCR2 0xA40800C8UL +#define INTC_IMCR3 0xA40800CCUL +#define INTC_IMCR4 0xA40800D0UL +#define INTC_IMCR5 0xA40800D4UL +#define INTC_IMCR6 0xA40800D8UL +#define INTC_IMCR7 0xA40800DCUL +#define INTC_IMCR8 0xA40800E0UL +#define INTC_IMCR9 0xA40800E4UL +#define INTC_IMCR10 0xA40800E8UL +#define INTC_IMCR11 0xA40800ECUL + +#define INTC_ICR0 0xA4140000UL +#define INTC_ICR1 0xA414001CUL + +#define INTMSK0 0xa4140044 +#define INTMSKCLR0 0xa4140064 +#define INTC_INTPRI0 0xa4140010 + +/* + NOTE: + + *_IRQ = (INTEVT2 - 0x200)/0x20 +*/ + +/* TMU0 */ +#define TMU0_IRQ 16 +#define TMU0_IPR_ADDR INTC_IPRA +#define TMU0_IPR_POS 3 +#define TMU0_PRIORITY 2 + +#define TIMER_IRQ 16 +#define TIMER_IPR_ADDR INTC_IPRA +#define TIMER_IPR_POS 3 +#define TIMER_PRIORITY 2 + +/* TMU1 */ +#define TMU1_IRQ 17 +#define TMU1_IPR_ADDR INTC_IPRA +#define TMU1_IPR_POS 2 +#define TMU1_PRIORITY 2 + +/* TMU2 */ +#define TMU2_IRQ 18 +#define TMU2_IPR_ADDR INTC_IPRA +#define TMU2_IPR_POS 1 +#define TMU2_PRIORITY 2 + +/* LCDC */ +#define LCDC_IRQ 28 +#define LCDC_IPR_ADDR INTC_IPRB +#define LCDC_IPR_POS 2 +#define LCDC_PRIORITY 2 + +/* VIO (Video I/O) */ +#define CEU_IRQ 52 +#define BEU_IRQ 53 +#define VEU_IRQ 54 +#define VOU_IRQ 55 +#define VIO_IPR_ADDR INTC_IPRE +#define VIO_IPR_POS 2 +#define VIO_PRIORITY 2 + +/* MFI (Multi Functional Interface) */ +#define MFI_IRQ 56 +#define MFI_IPR_ADDR INTC_IPRE +#define MFI_IPR_POS 1 +#define MFI_PRIORITY 2 + +/* VPU (Video Processing Unit) */ +#define VPU_IRQ 60 +#define VPU_IPR_ADDR INTC_IPRE +#define VPU_IPR_POS 0 +#define VPU_PRIORITY 2 + +/* 3DG */ +#define TDG_IRQ 63 +#define TDG_IPR_ADDR INTC_IPRJ +#define TDG_IPR_POS 2 +#define TDG_PRIORITY 2 + +/* DMAC(1) */ +#define DMTE0_IRQ 48 +#define DMTE1_IRQ 49 +#define DMTE2_IRQ 50 +#define DMTE3_IRQ 51 +#define DMA1_IPR_ADDR INTC_IPRE +#define DMA1_IPR_POS 3 +#define DMA1_PRIORITY 7 + +/* DMAC(2) */ +#define DMTE4_IRQ 76 +#define DMTE5_IRQ 77 +#define DMA2_IPR_ADDR INTC_IPRF +#define DMA2_IPR_POS 2 +#define DMA2_PRIORITY 7 + +/* SCIF0 */ +#define SCIF_ERI_IRQ 80 +#define SCIF_RXI_IRQ 81 +#define SCIF_BRI_IRQ 82 +#define SCIF_TXI_IRQ 83 +#define SCIF_IPR_ADDR INTC_IPRG +#define SCIF_IPR_POS 3 +#define SCIF_PRIORITY 3 + +/* SIOF0 */ +#define SIOF0_IRQ 84 +#define SIOF0_IPR_ADDR INTC_IPRH +#define SIOF0_IPR_POS 3 +#define SIOF0_PRIORITY 3 + +/* FLCTL (Flash Memory Controller) */ +#define FLSTE_IRQ 92 +#define FLTEND_IRQ 93 +#define FLTRQ0_IRQ 94 +#define FLTRQ1_IRQ 95 +#define FLCTL_IPR_ADDR INTC_IPRH +#define FLCTL_IPR_POS 1 +#define FLCTL_PRIORITY 3 + +/* IIC(0) (IIC Bus Interface) */ +#define IIC0_ALI_IRQ 96 +#define IIC0_TACKI_IRQ 97 +#define IIC0_WAITI_IRQ 98 +#define IIC0_DTEI_IRQ 99 +#define IIC0_IPR_ADDR INTC_IPRH +#define IIC0_IPR_POS 0 +#define IIC0_PRIORITY 3 + +/* IIC(1) (IIC Bus Interface) */ +#define IIC1_ALI_IRQ 44 +#define IIC1_TACKI_IRQ 45 +#define IIC1_WAITI_IRQ 46 +#define IIC1_DTEI_IRQ 47 +#define IIC1_IPR_ADDR INTC_IPRG +#define IIC1_IPR_POS 0 +#define IIC1_PRIORITY 3 + +/* SIO0 */ +#define SIO0_IRQ 88 +#define SIO0_IPR_ADDR INTC_IPRI +#define SIO0_IPR_POS 3 +#define SIO0_PRIORITY 3 + +/* SDHI */ +#define SDHI_SDHII0_IRQ 100 +#define SDHI_SDHII1_IRQ 101 +#define SDHI_SDHII2_IRQ 102 +#define SDHI_SDHII3_IRQ 103 +#define SDHI_IPR_ADDR INTC_IPRK +#define SDHI_IPR_POS 0 +#define SDHI_PRIORITY 3 + +/* SIU (Sound Interface Unit) */ +#define SIU_IRQ 108 +#define SIU_IPR_ADDR INTC_IPRJ +#define SIU_IPR_POS 1 +#define SIU_PRIORITY 3 + + +/* ONCHIP_NR_IRQS */ +#define NR_IRQS 109 + +/* In a generic kernel, NR_IRQS is an upper bound, and we should use + * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. + */ +#define ACTUAL_NR_IRQS NR_IRQS + + +extern void disable_irq(unsigned int); +extern void disable_irq_nosync(unsigned int); +extern void enable_irq(unsigned int); + +/* + * Simple Mask Register Support + */ +extern void make_maskreg_irq(unsigned int irq); +extern unsigned short *irq_mask_register; + +/* + * Function for "on chip support modules". + */ +extern void make_ipr_irq(unsigned int irq, unsigned int addr, + int pos, int priority); +extern void make_imask_irq(unsigned int irq); + +#define PORT_PACR 0xA4050100UL +#define PORT_PBCR 0xA4050102UL +#define PORT_PCCR 0xA4050104UL +#define PORT_PDCR 0xA4050106UL +#define PORT_PECR 0xA4050108UL +#define PORT_PFCR 0xA405010AUL +#define PORT_PGCR 0xA405010CUL +#define PORT_PHCR 0xA405010EUL +#define PORT_PJCR 0xA4050110UL +#define PORT_PKCR 0xA4050112UL +#define PORT_PLCR 0xA4050114UL +#define PORT_SCPCR 0xA4050116UL +#define PORT_PMCR 0xA4050118UL +#define PORT_PNCR 0xA405011AUL +#define PORT_PQCR 0xA405011CUL +#define PORT_PRCR 0xA405011EUL +#define PORT_PTCR 0xA405014CUL +#define PORT_PUCR 0xA405014EUL +#define PORT_PVCR 0xA4050150UL + +#define PORT_PSELA 0xA4050140UL +#define PORT_PSELB 0xA4050142UL +#define PORT_PSELC 0xA4050144UL +#define PORT_PSELE 0xA4050158UL + +#define PORT_HIZCRA 0xA4050146UL +#define PORT_HIZCRB 0xA4050148UL +#define PORT_DRVCR 0xA405014AUL + +#define PORT_PADR 0xA4050120UL +#define PORT_PBDR 0xA4050122UL +#define PORT_PCDR 0xA4050124UL +#define PORT_PDDR 0xA4050126UL +#define PORT_PEDR 0xA4050128UL +#define PORT_PFDR 0xA405012AUL +#define PORT_PGDR 0xA405012CUL +#define PORT_PHDR 0xA405012EUL +#define PORT_PJDR 0xA4050130UL +#define PORT_PKDR 0xA4050132UL +#define PORT_PLDR 0xA4050134UL +#define PORT_SCPDR 0xA4050136UL +#define PORT_PMDR 0xA4050138UL +#define PORT_PNDR 0xA405013AUL +#define PORT_PQDR 0xA405013CUL +#define PORT_PRDR 0xA405013EUL +#define PORT_PTDR 0xA405016CUL +#define PORT_PUDR 0xA405016EUL +#define PORT_PVDR 0xA4050170UL + +#define IRQ0_IRQ 32 +#define IRQ1_IRQ 33 +#define IRQ2_IRQ 34 +#define IRQ3_IRQ 35 +#define IRQ4_IRQ 36 +#define IRQ5_IRQ 37 +#define IRQ6_IRQ 38 +#define IRQ7_IRQ 39 + +#define INTPRI00 0xA4140010UL + +#define IRQ0_IPR_ADDR INTPRI00 +#define IRQ1_IPR_ADDR INTPRI00 +#define IRQ2_IPR_ADDR INTPRI00 +#define IRQ3_IPR_ADDR INTPRI00 +#define IRQ4_IPR_ADDR INTPRI00 +#define IRQ5_IPR_ADDR INTPRI00 +#define IRQ6_IPR_ADDR INTPRI00 +#define IRQ7_IPR_ADDR INTPRI00 + +#define IRQ0_IPR_POS 7 +#define IRQ1_IPR_POS 6 +#define IRQ2_IPR_POS 5 +#define IRQ3_IPR_POS 4 +#define IRQ4_IPR_POS 3 +#define IRQ5_IPR_POS 2 +#define IRQ6_IPR_POS 1 +#define IRQ7_IPR_POS 0 + +#define IRQ0_PRIORITY 1 +#define IRQ1_PRIORITY 1 +#define IRQ2_PRIORITY 1 +#define IRQ3_PRIORITY 1 +#define IRQ4_PRIORITY 1 +#define IRQ5_PRIORITY 1 +#define IRQ6_PRIORITY 1 +#define IRQ7_PRIORITY 1 + +extern int shmse_irq_demux(int irq); +#define __irq_demux(irq) shmse_irq_demux(irq) +#define irq_demux(irq) __irq_demux(irq) + +#endif /* __ASM_SH_IRQ_SH73180_H */ diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h new file mode 100644 index 0000000..831e52e --- /dev/null +++ b/include/asm-sh/irq.h @@ -0,0 +1,598 @@ +#ifndef __ASM_SH_IRQ_H +#define __ASM_SH_IRQ_H + +/* + * + * linux/include/asm-sh/irq.h + * + * Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi + * Copyright (C) 2000 Kazumoto Kojima + * Copyright (C) 2003 Paul Mundt + * + */ + +#include <linux/config.h> +#include <asm/machvec.h> +#include <asm/ptrace.h> /* for pt_regs */ + +#if defined(CONFIG_SH_HP600) || \ + defined(CONFIG_SH_RTS7751R2D) || \ + defined(CONFIG_SH_HS7751RVOIP) || \ + defined(CONFIG_SH_SH03) +#include <asm/mach/ide.h> +#endif + +#if defined(CONFIG_CPU_SH3) +#define INTC_IPRA 0xfffffee2UL +#define INTC_IPRB 0xfffffee4UL +#elif defined(CONFIG_CPU_SH4) +#define INTC_IPRA 0xffd00004UL +#define INTC_IPRB 0xffd00008UL +#define INTC_IPRC 0xffd0000cUL +#define INTC_IPRD 0xffd00010UL +#endif + +#ifdef CONFIG_IDE +# ifndef IRQ_CFCARD +# define IRQ_CFCARD 14 +# endif +# ifndef IRQ_PCMCIA +# define IRQ_PCMCIA 15 +# endif +#endif + +#define TIMER_IRQ 16 +#define TIMER_IPR_ADDR INTC_IPRA +#define TIMER_IPR_POS 3 +#define TIMER_PRIORITY 2 + +#define TIMER1_IRQ 17 +#define TIMER1_IPR_ADDR INTC_IPRA +#define TIMER1_IPR_POS 2 +#define TIMER1_PRIORITY 4 + +#define RTC_IRQ 22 +#define RTC_IPR_ADDR INTC_IPRA +#define RTC_IPR_POS 0 +#define RTC_PRIORITY TIMER_PRIORITY + +#if defined(CONFIG_CPU_SH3) +#define DMTE0_IRQ 48 +#define DMTE1_IRQ 49 +#define DMTE2_IRQ 50 +#define DMTE3_IRQ 51 +#define DMA_IPR_ADDR INTC_IPRE +#define DMA_IPR_POS 3 +#define DMA_PRIORITY 7 +#if defined(CONFIG_CPU_SUBTYPE_SH7300) +/* TMU2 */ +#define TIMER2_IRQ 18 +#define TIMER2_IPR_ADDR INTC_IPRA +#define TIMER2_IPR_POS 1 +#define TIMER2_PRIORITY 2 + +/* WDT */ +#define WDT_IRQ 27 +#define WDT_IPR_ADDR INTC_IPRB +#define WDT_IPR_POS 3 +#define WDT_PRIORITY 2 + +/* SIM (SIM Card Module) */ +#define SIM_ERI_IRQ 23 +#define SIM_RXI_IRQ 24 +#define SIM_TXI_IRQ 25 +#define SIM_TEND_IRQ 26 +#define SIM_IPR_ADDR INTC_IPRB +#define SIM_IPR_POS 1 +#define SIM_PRIORITY 2 + +/* VIO (Video I/O) */ +#define VIO_IRQ 52 +#define VIO_IPR_ADDR INTC_IPRE +#define VIO_IPR_POS 2 +#define VIO_PRIORITY 2 + +/* MFI (Multi Functional Interface) */ +#define MFI_IRQ 56 +#define MFI_IPR_ADDR INTC_IPRE +#define MFI_IPR_POS 1 +#define MFI_PRIORITY 2 + +/* VPU (Video Processing Unit) */ +#define VPU_IRQ 60 +#define VPU_IPR_ADDR INTC_IPRE +#define VPU_IPR_POS 0 +#define VPU_PRIORITY 2 + +/* KEY (Key Scan Interface) */ +#define KEY_IRQ 79 +#define KEY_IPR_ADDR INTC_IPRF +#define KEY_IPR_POS 3 +#define KEY_PRIORITY 2 + +/* CMT (Compare Match Timer) */ +#define CMT_IRQ 104 +#define CMT_IPR_ADDR INTC_IPRF +#define CMT_IPR_POS 0 +#define CMT_PRIORITY 2 + +/* DMAC(1) */ +#define DMTE0_IRQ 48 +#define DMTE1_IRQ 49 +#define DMTE2_IRQ 50 +#define DMTE3_IRQ 51 +#define DMA1_IPR_ADDR INTC_IPRE +#define DMA1_IPR_POS 3 +#define DMA1_PRIORITY 7 + +/* DMAC(2) */ +#define DMTE4_IRQ 76 +#define DMTE5_IRQ 77 +#define DMA2_IPR_ADDR INTC_IPRF +#define DMA2_IPR_POS 2 +#define DMA2_PRIORITY 7 + +/* SIOF0 */ +#define SIOF0_IRQ 84 +#define SIOF0_IPR_ADDR INTC_IPRH +#define SIOF0_IPR_POS 3 +#define SIOF0_PRIORITY 3 + +/* FLCTL (Flash Memory Controller) */ +#define FLSTE_IRQ 92 +#define FLTEND_IRQ 93 +#define FLTRQ0_IRQ 94 +#define FLTRQ1_IRQ 95 +#define FLCTL_IPR_ADDR INTC_IPRH +#define FLCTL_IPR_POS 1 +#define FLCTL_PRIORITY 3 + +/* IIC (IIC Bus Interface) */ +#define IIC_ALI_IRQ 96 +#define IIC_TACKI_IRQ 97 +#define IIC_WAITI_IRQ 98 +#define IIC_DTEI_IRQ 99 +#define IIC_IPR_ADDR INTC_IPRH +#define IIC_IPR_POS 0 +#define IIC_PRIORITY 3 + +/* SIO0 */ +#define SIO0_IRQ 88 +#define SIO0_IPR_ADDR INTC_IPRI +#define SIO0_IPR_POS 3 +#define SIO0_PRIORITY 3 + +/* SIU (Sound Interface Unit) */ +#define SIU_IRQ 108 +#define SIU_IPR_ADDR INTC_IPRJ +#define SIU_IPR_POS 1 +#define SIU_PRIORITY 3 + +#endif +#elif defined(CONFIG_CPU_SH4) +#define DMTE0_IRQ 34 +#define DMTE1_IRQ 35 +#define DMTE2_IRQ 36 +#define DMTE3_IRQ 37 +#define DMTE4_IRQ 44 /* 7751R only */ +#define DMTE5_IRQ 45 /* 7751R only */ +#define DMTE6_IRQ 46 /* 7751R only */ +#define DMTE7_IRQ 47 /* 7751R only */ +#define DMAE_IRQ 38 +#define DMA_IPR_ADDR INTC_IPRC +#define DMA_IPR_POS 2 +#define DMA_PRIORITY 7 +#endif + +#if defined (CONFIG_CPU_SUBTYPE_SH7707) || defined (CONFIG_CPU_SUBTYPE_SH7708) || \ + defined (CONFIG_CPU_SUBTYPE_SH7709) || defined (CONFIG_CPU_SUBTYPE_SH7750) || \ + defined (CONFIG_CPU_SUBTYPE_SH7751) +#define SCI_ERI_IRQ 23 +#define SCI_RXI_IRQ 24 +#define SCI_TXI_IRQ 25 +#define SCI_IPR_ADDR INTC_IPRB +#define SCI_IPR_POS 1 +#define SCI_PRIORITY 3 +#endif + +#if defined(CONFIG_CPU_SUBTYPE_SH7300) +#define SCIF0_IRQ 80 +#define SCIF0_IPR_ADDR INTC_IPRG +#define SCIF0_IPR_POS 3 +#define SCIF0_PRIORITY 3 +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) +#define SCIF_ERI_IRQ 56 +#define SCIF_RXI_IRQ 57 +#define SCIF_BRI_IRQ 58 +#define SCIF_TXI_IRQ 59 +#define SCIF_IPR_ADDR INTC_IPRE +#define SCIF_IPR_POS 1 +#define SCIF_PRIORITY 3 + +#define IRDA_ERI_IRQ 52 +#define IRDA_RXI_IRQ 53 +#define IRDA_BRI_IRQ 54 +#define IRDA_TXI_IRQ 55 +#define IRDA_IPR_ADDR INTC_IPRE +#define IRDA_IPR_POS 2 +#define IRDA_PRIORITY 3 +#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ + defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202) +#define SCIF_ERI_IRQ 40 +#define SCIF_RXI_IRQ 41 +#define SCIF_BRI_IRQ 42 +#define SCIF_TXI_IRQ 43 +#define SCIF_IPR_ADDR INTC_IPRC +#define SCIF_IPR_POS 1 +#define SCIF_PRIORITY 3 +#if defined(CONFIG_CPU_SUBTYPE_ST40STB1) +#define SCIF1_ERI_IRQ 23 +#define SCIF1_RXI_IRQ 24 +#define SCIF1_BRI_IRQ 25 +#define SCIF1_TXI_IRQ 26 +#define SCIF1_IPR_ADDR INTC_IPRB +#define SCIF1_IPR_POS 1 +#define SCIF1_PRIORITY 3 +#endif +#endif + +/* NR_IRQS is made from three components: + * 1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules + * 2. PINT_NR_IRQS - number of PINT interrupts + * 3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules + */ + +/* 1. ONCHIP_NR_IRQS */ +#ifdef CONFIG_SH_GENERIC +# define ONCHIP_NR_IRQS 144 +#else +# if defined(CONFIG_CPU_SUBTYPE_SH7604) +# define ONCHIP_NR_IRQS 24 // Actually 21 +# elif defined(CONFIG_CPU_SUBTYPE_SH7707) +# define ONCHIP_NR_IRQS 64 +# define PINT_NR_IRQS 16 +# elif defined(CONFIG_CPU_SUBTYPE_SH7708) +# define ONCHIP_NR_IRQS 32 +# elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7705) +# define ONCHIP_NR_IRQS 64 // Actually 61 +# define PINT_NR_IRQS 16 +# elif defined(CONFIG_CPU_SUBTYPE_SH7750) +# define ONCHIP_NR_IRQS 48 // Actually 44 +# elif defined(CONFIG_CPU_SUBTYPE_SH7751) +# define ONCHIP_NR_IRQS 72 +# elif defined(CONFIG_CPU_SUBTYPE_SH7760) +# define ONCHIP_NR_IRQS 110 +# elif defined(CONFIG_CPU_SUBTYPE_SH4_202) +# define ONCHIP_NR_IRQS 72 +# elif defined(CONFIG_CPU_SUBTYPE_ST40STB1) +# define ONCHIP_NR_IRQS 144 +# elif defined(CONFIG_CPU_SUBTYPE_SH7300) +# define ONCHIP_NR_IRQS 109 +# endif +#endif + +/* 2. PINT_NR_IRQS */ +#ifdef CONFIG_SH_GENERIC +# define PINT_NR_IRQS 16 +#else +# ifndef PINT_NR_IRQS +# define PINT_NR_IRQS 0 +# endif +#endif + +#if PINT_NR_IRQS > 0 +# define PINT_IRQ_BASE ONCHIP_NR_IRQS +#endif + +/* 3. OFFCHIP_NR_IRQS */ +#ifdef CONFIG_SH_GENERIC +# define OFFCHIP_NR_IRQS 16 +#else +# if defined(CONFIG_HD64461) +# define OFFCHIP_NR_IRQS 18 +# elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */ +# define OFFCHIP_NR_IRQS 48 +# elif defined(CONFIG_HD64465) +# define OFFCHIP_NR_IRQS 16 +# elif defined (CONFIG_SH_EC3104) +# define OFFCHIP_NR_IRQS 16 +# elif defined (CONFIG_SH_DREAMCAST) +# define OFFCHIP_NR_IRQS 96 +# else +# define OFFCHIP_NR_IRQS 0 +# endif +#endif + +#if OFFCHIP_NR_IRQS > 0 +# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS) +#endif + +/* NR_IRQS. 1+2+3 */ +#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) + +/* In a generic kernel, NR_IRQS is an upper bound, and we should use + * ACTUAL_NR_IRQS (which uses the machine vector) to get the correct value. + */ +#ifdef CONFIG_SH_GENERIC +# define ACTUAL_NR_IRQS (sh_mv.mv_nr_irqs) +#else +# define ACTUAL_NR_IRQS NR_IRQS +#endif + + +extern void disable_irq(unsigned int); +extern void disable_irq_nosync(unsigned int); +extern void enable_irq(unsigned int); + +/* + * Simple Mask Register Support + */ +extern void make_maskreg_irq(unsigned int irq); +extern unsigned short *irq_mask_register; + +/* + * Function for "on chip support modules". + */ +extern void make_ipr_irq(unsigned int irq, unsigned int addr, + int pos, int priority); +extern void make_imask_irq(unsigned int irq); + +#if defined(CONFIG_CPU_SUBTYPE_SH7300) +#undef INTC_IPRA +#undef INTC_IPRB +#define INTC_IPRA 0xA414FEE2UL +#define INTC_IPRB 0xA414FEE4UL +#define INTC_IPRC 0xA4140016UL +#define INTC_IPRD 0xA4140018UL +#define INTC_IPRE 0xA414001AUL +#define INTC_IPRF 0xA4080000UL +#define INTC_IPRG 0xA4080002UL +#define INTC_IPRH 0xA4080004UL +#define INTC_IPRI 0xA4080006UL +#define INTC_IPRJ 0xA4080008UL + +#define INTC_IMR0 0xA4080040UL +#define INTC_IMR1 0xA4080042UL +#define INTC_IMR2 0xA4080044UL +#define INTC_IMR3 0xA4080046UL +#define INTC_IMR4 0xA4080048UL +#define INTC_IMR5 0xA408004AUL +#define INTC_IMR6 0xA408004CUL +#define INTC_IMR7 0xA408004EUL +#define INTC_IMR8 0xA4080050UL +#define INTC_IMR9 0xA4080052UL +#define INTC_IMR10 0xA4080054UL + +#define INTC_IMCR0 0xA4080060UL +#define INTC_IMCR1 0xA4080062UL +#define INTC_IMCR2 0xA4080064UL +#define INTC_IMCR3 0xA4080066UL +#define INTC_IMCR4 0xA4080068UL +#define INTC_IMCR5 0xA408006AUL +#define INTC_IMCR6 0xA408006CUL +#define INTC_IMCR7 0xA408006EUL +#define INTC_IMCR8 0xA4080070UL +#define INTC_IMCR9 0xA4080072UL +#define INTC_IMCR10 0xA4080074UL + +#define INTC_ICR0 0xA414FEE0UL +#define INTC_ICR1 0xA4140010UL + +#define INTC_IRR0 0xA4140004UL + +#define PORT_PACR 0xA4050100UL +#define PORT_PBCR 0xA4050102UL +#define PORT_PCCR 0xA4050104UL +#define PORT_PDCR 0xA4050106UL +#define PORT_PECR 0xA4050108UL +#define PORT_PFCR 0xA405010AUL +#define PORT_PGCR 0xA405010CUL +#define PORT_PHCR 0xA405010EUL +#define PORT_PJCR 0xA4050110UL +#define PORT_PKCR 0xA4050112UL +#define PORT_PLCR 0xA4050114UL +#define PORT_SCPCR 0xA4050116UL +#define PORT_PMCR 0xA4050118UL +#define PORT_PNCR 0xA405011AUL +#define PORT_PQCR 0xA405011CUL + +#define PORT_PSELA 0xA4050140UL +#define PORT_PSELB 0xA4050142UL +#define PORT_PSELC 0xA4050144UL + +#define PORT_HIZCRA 0xA4050146UL +#define PORT_HIZCRB 0xA4050148UL +#define PORT_DRVCR 0xA4050150UL + +#define PORT_PADR 0xA4050120UL +#define PORT_PBDR 0xA4050122UL +#define PORT_PCDR 0xA4050124UL +#define PORT_PDDR 0xA4050126UL +#define PORT_PEDR 0xA4050128UL +#define PORT_PFDR 0xA405012AUL +#define PORT_PGDR 0xA405012CUL +#define PORT_PHDR 0xA405012EUL +#define PORT_PJDR 0xA4050130UL +#define PORT_PKDR 0xA4050132UL +#define PORT_PLDR 0xA4050134UL +#define PORT_SCPDR 0xA4050136UL +#define PORT_PMDR 0xA4050138UL +#define PORT_PNDR 0xA405013AUL +#define PORT_PQDR 0xA405013CUL + +#define IRQ0_IRQ 32 +#define IRQ1_IRQ 33 +#define IRQ2_IRQ 34 +#define IRQ3_IRQ 35 +#define IRQ4_IRQ 36 +#define IRQ5_IRQ 37 + +#define IRQ0_IPR_ADDR INTC_IPRC +#define IRQ1_IPR_ADDR INTC_IPRC +#define IRQ2_IPR_ADDR INTC_IPRC +#define IRQ3_IPR_ADDR INTC_IPRC +#define IRQ4_IPR_ADDR INTC_IPRD +#define IRQ5_IPR_ADDR INTC_IPRD + +#define IRQ0_IPR_POS 0 +#define IRQ1_IPR_POS 1 +#define IRQ2_IPR_POS 2 +#define IRQ3_IPR_POS 3 +#define IRQ4_IPR_POS 0 +#define IRQ5_IPR_POS 1 + +#define IRQ0_PRIORITY 1 +#define IRQ1_PRIORITY 1 +#define IRQ2_PRIORITY 1 +#define IRQ3_PRIORITY 1 +#define IRQ4_PRIORITY 1 +#define IRQ5_PRIORITY 1 + +extern int ipr_irq_demux(int irq); +#define __irq_demux(irq) ipr_irq_demux(irq) + +#elif defined(CONFIG_CPU_SUBTYPE_SH7604) +#define INTC_IPRA 0xfffffee2UL +#define INTC_IPRB 0xfffffe60UL + +#define INTC_VCRA 0xfffffe62UL +#define INTC_VCRB 0xfffffe64UL +#define INTC_VCRC 0xfffffe66UL +#define INTC_VCRD 0xfffffe68UL + +#define INTC_VCRWDT 0xfffffee4UL +#define INTC_VCRDIV 0xffffff0cUL +#define INTC_VCRDMA0 0xffffffa0UL +#define INTC_VCRDMA1 0xffffffa8UL + +#define INTC_ICR 0xfffffee0UL +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ + defined(CONFIG_CPU_SUBTYPE_SH7707) || \ + defined(CONFIG_CPU_SUBTYPE_SH7709) +#define INTC_IRR0 0xa4000004UL +#define INTC_IRR1 0xa4000006UL +#define INTC_IRR2 0xa4000008UL + +#define INTC_ICR0 0xfffffee0UL +#define INTC_ICR1 0xa4000010UL +#define INTC_ICR2 0xa4000012UL +#define INTC_INTER 0xa4000014UL + +#define INTC_IPRC 0xa4000016UL +#define INTC_IPRD 0xa4000018UL +#define INTC_IPRE 0xa400001aUL +#if defined(CONFIG_CPU_SUBTYPE_SH7707) +#define INTC_IPRF 0xa400001cUL +#elif defined(CONFIG_CPU_SUBTYPE_SH7705) +#define INTC_IPRF 0xa4080000UL +#define INTC_IPRG 0xa4080002UL +#define INTC_IPRH 0xa4080004UL +#endif + +#define PORT_PACR 0xa4000100UL +#define PORT_PBCR 0xa4000102UL +#define PORT_PCCR 0xa4000104UL +#define PORT_PFCR 0xa400010aUL +#define PORT_PADR 0xa4000120UL +#define PORT_PBDR 0xa4000122UL +#define PORT_PCDR 0xa4000124UL +#define PORT_PFDR 0xa400012aUL + +#define IRQ0_IRQ 32 +#define IRQ1_IRQ 33 +#define IRQ2_IRQ 34 +#define IRQ3_IRQ 35 +#define IRQ4_IRQ 36 +#define IRQ5_IRQ 37 + +#define IRQ0_IPR_ADDR INTC_IPRC +#define IRQ1_IPR_ADDR INTC_IPRC +#define IRQ2_IPR_ADDR INTC_IPRC +#define IRQ3_IPR_ADDR INTC_IPRC +#define IRQ4_IPR_ADDR INTC_IPRD +#define IRQ5_IPR_ADDR INTC_IPRD + +#define IRQ0_IPR_POS 0 +#define IRQ1_IPR_POS 1 +#define IRQ2_IPR_POS 2 +#define IRQ3_IPR_POS 3 +#define IRQ4_IPR_POS 0 +#define IRQ5_IPR_POS 1 + +#define IRQ0_PRIORITY 1 +#define IRQ1_PRIORITY 1 +#define IRQ2_PRIORITY 1 +#define IRQ3_PRIORITY 1 +#define IRQ4_PRIORITY 1 +#define IRQ5_PRIORITY 1 + +#define PINT0_IRQ 40 +#define PINT8_IRQ 41 + +#define PINT0_IPR_ADDR INTC_IPRD +#define PINT8_IPR_ADDR INTC_IPRD + +#define PINT0_IPR_POS 3 +#define PINT8_IPR_POS 2 +#define PINT0_PRIORITY 2 +#define PINT8_PRIORITY 2 + +extern int ipr_irq_demux(int irq); +#define __irq_demux(irq) ipr_irq_demux(irq) + +#else +#define __irq_demux(irq) irq +#endif /* CONFIG_CPU_SUBTYPE_SH7707 || CONFIG_CPU_SUBTYPE_SH7709 */ + +#if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751) || \ + defined(CONFIG_CPU_SUBTYPE_ST40STB1) || defined(CONFIG_CPU_SUBTYPE_SH4_202) +#define INTC_ICR 0xffd00000 +#define INTC_ICR_NMIL (1<<15) +#define INTC_ICR_MAI (1<<14) +#define INTC_ICR_NMIB (1<<9) +#define INTC_ICR_NMIE (1<<8) +#define INTC_ICR_IRLM (1<<7) +#endif + +#ifdef CONFIG_CPU_SUBTYPE_ST40STB1 + +#define INTC2_FIRST_IRQ 64 +#define NR_INTC2_IRQS 25 + +#define INTC2_BASE 0xfe080000 +#define INTC2_INTC2MODE (INTC2_BASE+0x80) + +#define INTC2_INTPRI_OFFSET 0x00 +#define INTC2_INTREQ_OFFSET 0x20 +#define INTC2_INTMSK_OFFSET 0x40 +#define INTC2_INTMSKCLR_OFFSET 0x60 + +void make_intc2_irq(unsigned int irq, + unsigned int ipr_offset, unsigned int ipr_shift, + unsigned int msk_offset, unsigned int msk_shift, + unsigned int priority); +void init_IRQ_intc2(void); +void intc2_add_clear_irq(int irq, int (*fn)(int)); + +#endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */ + +static inline int generic_irq_demux(int irq) +{ + return irq; +} + +#define irq_canonicalize(irq) (irq) +#define irq_demux(irq) __irq_demux(sh_mv.mv_irq_demux(irq)) + +struct irqaction; +struct pt_regs; +int handle_IRQ_event(unsigned int, struct pt_regs *, struct irqaction *); + +#if defined(CONFIG_CPU_SUBTYPE_SH73180) +#include <asm/irq-sh73180.h> +#endif + +#endif /* __ASM_SH_IRQ_H */ diff --git a/include/asm-sh/keyboard.h b/include/asm-sh/keyboard.h new file mode 100644 index 0000000..1103df0 --- /dev/null +++ b/include/asm-sh/keyboard.h @@ -0,0 +1,14 @@ +#ifndef __ASM_SH_KEYBOARD_H +#define __ASM_SH_KEYBOARD_H +/* + * $Id: keyboard.h,v 1.1.1.1 2001/10/15 20:45:09 mrbrown Exp $ + */ + +#include <linux/kd.h> +#include <linux/config.h> +#include <asm/machvec.h> + +#ifdef CONFIG_SH_MPC1211 +#include <asm/mpc1211/keyboard-mpc1211.h> +#endif +#endif diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h new file mode 100644 index 0000000..1653ffb --- /dev/null +++ b/include/asm-sh/kgdb.h @@ -0,0 +1,131 @@ +/* + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * Based on original code by Glenn Engel, Jim Kingdon, + * David Grothe <dave@gcom.com>, Tigran Aivazian, <tigran@sco.com> and + * Amit S. Kale <akale@veritas.com> + * + * Super-H port based on sh-stub.c (Ben Lee and Steve Chamberlain) by + * Henry Bell <henry.bell@st.com> + * + * Header file for low-level support for remote debug using GDB. + * + */ + +#ifndef __KGDB_H +#define __KGDB_H + +#include <asm/ptrace.h> + +struct console; + +/* Same as pt_regs but has vbr in place of syscall_nr */ +struct kgdb_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + unsigned long vbr; +}; + +/* State info */ +extern char kgdb_in_gdb_mode; +extern int kgdb_done_init; +extern int kgdb_enabled; +extern int kgdb_nofault; /* Ignore bus errors (in gdb mem access) */ +extern int kgdb_halt; /* Execute initial breakpoint at startup */ +extern char in_nmi; /* Debounce flag to prevent NMI reentry*/ + +/* SCI */ +extern int kgdb_portnum; +extern int kgdb_baud; +extern char kgdb_parity; +extern char kgdb_bits; +extern int kgdb_console_setup(struct console *, char *); + +/* Init and interface stuff */ +extern int kgdb_init(void); +extern int (*kgdb_serial_setup)(void); +extern int (*kgdb_getchar)(void); +extern void (*kgdb_putchar)(int); + +struct kgdb_sermap { + char *name; + int namelen; + int (*setup_fn)(struct console *, char *); + struct kgdb_sermap *next; +}; +extern void kgdb_register_sermap(struct kgdb_sermap *map); +extern struct kgdb_sermap *kgdb_porttype; + +/* Trap functions */ +typedef void (kgdb_debug_hook_t)(struct pt_regs *regs); +typedef void (kgdb_bus_error_hook_t)(void); +extern kgdb_debug_hook_t *kgdb_debug_hook; +extern kgdb_bus_error_hook_t *kgdb_bus_err_hook; + +extern void breakpoint(void); + +/* Console */ +struct console; +void kgdb_console_write(struct console *co, const char *s, unsigned count); +void kgdb_console_init(void); + +/* Prototypes for jmp fns */ +#define _JBLEN 9 +typedef int jmp_buf[_JBLEN]; +extern void longjmp(jmp_buf __jmpb, int __retval); +extern int setjmp(jmp_buf __jmpb); + +/* Variadic macro to print our own message to the console */ +#define KGDB_PRINTK(...) printk("KGDB: " __VA_ARGS__) + +/* Forced breakpoint */ +#define BREAKPOINT() do { \ + if (kgdb_enabled) { \ + asm volatile("trapa #0xff"); \ + } \ +} while (0) + +/* KGDB should be able to flush all kernel text space */ +#if defined(CONFIG_CPU_SH4) +#define kgdb_flush_icache_range(start, end) \ +{ \ + extern void __flush_purge_region(void *, int); \ + __flush_purge_region((void*)(start), (int)(end) - (int)(start));\ + flush_icache_range((start), (end)); \ +} +#else +#define kgdb_flush_icache_range(start, end) do { } while (0) +#endif + +/* Kernel assert macros */ +#ifdef CONFIG_KGDB_KERNEL_ASSERTS + +/* Predefined conditions */ +#define KA_VALID_ERRNO(errno) ((errno) > 0 && (errno) <= EMEDIUMTYPE) +#define KA_VALID_PTR_ERR(ptr) KA_VALID_ERRNO(-PTR_ERR(ptr)) +#define KA_VALID_KPTR(ptr) (!(ptr) || \ + ((void *)(ptr) >= (void *)PAGE_OFFSET && \ + (void *)(ptr) < ERR_PTR(-EMEDIUMTYPE))) +#define KA_VALID_PTRORERR(errptr) \ + (KA_VALID_KPTR(errptr) || KA_VALID_PTR_ERR(errptr)) +#define KA_HELD_GKL() (current->lock_depth >= 0) + +/* The actual assert */ +#define KGDB_ASSERT(condition, message) do { \ + if (!(condition) && (kgdb_enabled)) { \ + KGDB_PRINTK("Assertion failed at %s:%d: %s\n", \ + __FILE__, __LINE__, message);\ + BREAKPOINT(); \ + } \ +} while (0) +#else +#define KGDB_ASSERT(condition, message) +#endif + +#endif diff --git a/include/asm-sh/kmap_types.h b/include/asm-sh/kmap_types.h new file mode 100644 index 0000000..2492ba0 --- /dev/null +++ b/include/asm-sh/kmap_types.h @@ -0,0 +1,33 @@ +#ifndef __SH_KMAP_TYPES_H +#define __SH_KMAP_TYPES_H + +/* Dummy header just to define km_type. */ + +#include <linux/config.h> + +#ifdef CONFIG_DEBUG_HIGHMEM +# define D(n) __KM_FENCE_##n , +#else +# define D(n) +#endif + +enum km_type { +D(0) KM_BOUNCE_READ, +D(1) KM_SKB_SUNRPC_DATA, +D(2) KM_SKB_DATA_SOFTIRQ, +D(3) KM_USER0, +D(4) KM_USER1, +D(5) KM_BIO_SRC_IRQ, +D(6) KM_BIO_DST_IRQ, +D(7) KM_PTE0, +D(8) KM_PTE1, +D(9) KM_IRQ0, +D(10) KM_IRQ1, +D(11) KM_SOFTIRQ0, +D(12) KM_SOFTIRQ1, +D(13) KM_TYPE_NR +}; + +#undef D + +#endif diff --git a/include/asm-sh/linkage.h b/include/asm-sh/linkage.h new file mode 100644 index 0000000..3565a4f --- /dev/null +++ b/include/asm-sh/linkage.h @@ -0,0 +1,7 @@ +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .balign 4 +#define __ALIGN_STR ".balign 4" + +#endif diff --git a/include/asm-sh/local.h b/include/asm-sh/local.h new file mode 100644 index 0000000..9ed9b9c --- /dev/null +++ b/include/asm-sh/local.h @@ -0,0 +1,7 @@ +#ifndef __ASM_SH_LOCAL_H +#define __ASM_SH_LOCAL_H + +#include <asm-generic/local.h> + +#endif /* __ASM_SH_LOCAL_H */ + diff --git a/include/asm-sh/machvec.h b/include/asm-sh/machvec.h new file mode 100644 index 0000000..5771f4b --- /dev/null +++ b/include/asm-sh/machvec.h @@ -0,0 +1,73 @@ +/* + * include/asm-sh/machvec.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ + +#ifndef _ASM_SH_MACHVEC_H +#define _ASM_SH_MACHVEC_H 1 + +#include <linux/config.h> +#include <linux/types.h> +#include <linux/time.h> + +#include <asm/machtypes.h> +#include <asm/machvec_init.h> + +struct device; +struct timeval; + +struct sh_machine_vector +{ + int mv_nr_irqs; + + unsigned char (*mv_inb)(unsigned long); + unsigned short (*mv_inw)(unsigned long); + unsigned int (*mv_inl)(unsigned long); + void (*mv_outb)(unsigned char, unsigned long); + void (*mv_outw)(unsigned short, unsigned long); + void (*mv_outl)(unsigned int, unsigned long); + + unsigned char (*mv_inb_p)(unsigned long); + unsigned short (*mv_inw_p)(unsigned long); + unsigned int (*mv_inl_p)(unsigned long); + void (*mv_outb_p)(unsigned char, unsigned long); + void (*mv_outw_p)(unsigned short, unsigned long); + void (*mv_outl_p)(unsigned int, unsigned long); + + void (*mv_insb)(unsigned long port, void *addr, unsigned long count); + void (*mv_insw)(unsigned long port, void *addr, unsigned long count); + void (*mv_insl)(unsigned long port, void *addr, unsigned long count); + void (*mv_outsb)(unsigned long port, const void *addr, unsigned long count); + void (*mv_outsw)(unsigned long port, const void *addr, unsigned long count); + void (*mv_outsl)(unsigned long port, const void *addr, unsigned long count); + + unsigned char (*mv_readb)(unsigned long); + unsigned short (*mv_readw)(unsigned long); + unsigned int (*mv_readl)(unsigned long); + void (*mv_writeb)(unsigned char, unsigned long); + void (*mv_writew)(unsigned short, unsigned long); + void (*mv_writel)(unsigned int, unsigned long); + + void* (*mv_ioremap)(unsigned long offset, unsigned long size); + void (*mv_iounmap)(void *addr); + + unsigned long (*mv_isa_port2addr)(unsigned long offset); + + int (*mv_irq_demux)(int irq); + + void (*mv_init_irq)(void); + void (*mv_init_pci)(void); + + void (*mv_heartbeat)(void); + + void *(*mv_consistent_alloc)(struct device *, size_t, dma_addr_t *, int); + int (*mv_consistent_free)(struct device *, size_t, void *, dma_addr_t); +}; + +extern struct sh_machine_vector sh_mv; + +#endif /* _ASM_SH_MACHVEC_H */ diff --git a/include/asm-sh/machvec_init.h b/include/asm-sh/machvec_init.h new file mode 100644 index 0000000..9e7de80 --- /dev/null +++ b/include/asm-sh/machvec_init.h @@ -0,0 +1,54 @@ +/* + * include/asm-sh/machvec_init.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * This file has goodies to help simplify instantiation of machine vectors. + */ + +#ifndef __SH_MACHVEC_INIT_H +#define __SH_MACHVEC_INIT_H + +#include <linux/config.h> + +/* + * In a GENERIC kernel, we have lots of these vectors floating about, + * all but one of which we want to go away. In a non-GENERIC kernel, + * we want only one, ever. + * + * Accomplish this in the GENERIC kernel by puting all of the vectors + * in the .init.data section where they'll go away. We'll copy the + * one we want to the real alpha_mv vector in setup_arch. + * + * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but + * one of the vectors, which will not reside in .init.data. We then + * alias this one vector to alpha_mv, so no copy is needed. + * + * Upshot: set __initdata to nothing for non-GENERIC kernels. + * + * Note we do the same thing for the UNKNOWN kernel, as we need to write + * to the machine vector while setting it up. + */ + +#if defined(CONFIG_SH_GENERIC) || defined(CONFIG_SH_UNKNOWN) +#define __initmv __attribute__((unused,__section__ (".machvec.init"))) +#define ALIAS_MV(x) +#else +#define __initmv + +/* GCC actually has a syntax for defining aliases, but is under some + delusion that you shouldn't be able to declare it extern somewhere + else beforehand. Fine. We'll do it ourselves. */ +#if 0 +#define ALIAS_MV(system) \ + struct sh_machine_vector sh_mv __attribute__((alias("mv_"#system))); +#else +#define ALIAS_MV(system) \ + asm(".global sh_mv\nsh_mv = mv_"#system ); +#endif +#endif /* GENERIC */ + +#endif /* __SH_MACHVEC_INIT_H */ diff --git a/include/asm-sh/mc146818rtc.h b/include/asm-sh/mc146818rtc.h new file mode 100644 index 0000000..1707cfb --- /dev/null +++ b/include/asm-sh/mc146818rtc.h @@ -0,0 +1,176 @@ +/* + * Machine dependent access functions for RTC registers. + */ +#ifndef _ASM_MC146818RTC_H +#define _ASM_MC146818RTC_H + +#ifdef CONFIG_SH_MPC1211 +#undef _ASM_MC146818RTC_H +#undef RTC_IRQ +#include <asm/mpc1211/mc146818rtc.h> +#else + +#include <asm/rtc.h> + +#define RTC_ALWAYS_BCD 1 + +/* FIXME:RTC Interrupt feature is not implemented yet. */ +#undef RTC_IRQ +#define RTC_IRQ 0 + +#if defined(CONFIG_CPU_SH3) +#define RTC_PORT(n) (R64CNT+(n)*2) +#define CMOS_READ(addr) __CMOS_READ(addr,b) +#define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,b) + +#elif defined(CONFIG_SH_SECUREEDGE5410) +#include <asm/snapgear/io.h> + +#define RTC_PORT(n) SECUREEDGE_IOPORT_ADDR +#define CMOS_READ(addr) secureedge5410_cmos_read(addr) +#define CMOS_WRITE(val,addr) secureedge5410_cmos_write(val,addr) +extern unsigned char secureedge5410_cmos_read(int addr); +extern void secureedge5410_cmos_write(unsigned char val, int addr); + +#elif defined(CONFIG_CPU_SH4) +#define RTC_PORT(n) (R64CNT+(n)*4) +#define CMOS_READ(addr) __CMOS_READ(addr,w) +#define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,w) +#endif + +#define __CMOS_READ(addr, s) ({ \ + unsigned char val=0, rcr1, rcr2, r64cnt, retry; \ + switch(addr) { \ + case RTC_SECONDS: \ + val = ctrl_inb(RSECCNT); \ + break; \ + case RTC_SECONDS_ALARM: \ + val = ctrl_inb(RSECAR); \ + break; \ + case RTC_MINUTES: \ + val = ctrl_inb(RMINCNT); \ + break; \ + case RTC_MINUTES_ALARM: \ + val = ctrl_inb(RMINAR); \ + break; \ + case RTC_HOURS: \ + val = ctrl_inb(RHRCNT); \ + break; \ + case RTC_HOURS_ALARM: \ + val = ctrl_inb(RHRAR); \ + break; \ + case RTC_DAY_OF_WEEK: \ + val = ctrl_inb(RWKCNT); \ + break; \ + case RTC_DAY_OF_MONTH: \ + val = ctrl_inb(RDAYCNT); \ + break; \ + case RTC_MONTH: \ + val = ctrl_inb(RMONCNT); \ + break; \ + case RTC_YEAR: \ + val = ctrl_in##s(RYRCNT); \ + break; \ + case RTC_REG_A: /* RTC_FREQ_SELECT */ \ + rcr2 = ctrl_inb(RCR2); \ + val = (rcr2 & RCR2_PESMASK) >> 4; \ + rcr1 = ctrl_inb(RCR1); \ + rcr1 = (rcr1 & (RCR1_CIE | RCR1_AIE)) | RCR1_AF;\ + retry = 0; \ + do { \ + ctrl_outb(rcr1, RCR1); /* clear CF */ \ + r64cnt = ctrl_inb(R64CNT); \ + } while((ctrl_inb(RCR1) & RCR1_CF) && retry++ < 1000);\ + r64cnt ^= RTC_BIT_INVERTED; \ + if(r64cnt == 0x7f || r64cnt == 0) \ + val |= RTC_UIP; \ + break; \ + case RTC_REG_B: /* RTC_CONTROL */ \ + rcr1 = ctrl_inb(RCR1); \ + rcr2 = ctrl_inb(RCR2); \ + if(rcr1 & RCR1_CIE) val |= RTC_UIE; \ + if(rcr1 & RCR1_AIE) val |= RTC_AIE; \ + if(rcr2 & RCR2_PESMASK) val |= RTC_PIE; \ + if(!(rcr2 & RCR2_START))val |= RTC_SET; \ + val |= RTC_24H; \ + break; \ + case RTC_REG_C: /* RTC_INTR_FLAGS */ \ + rcr1 = ctrl_inb(RCR1); \ + rcr1 &= ~(RCR1_CF | RCR1_AF); \ + ctrl_outb(rcr1, RCR1); \ + rcr2 = ctrl_inb(RCR2); \ + rcr2 &= ~RCR2_PEF; \ + ctrl_outb(rcr2, RCR2); \ + break; \ + case RTC_REG_D: /* RTC_VALID */ \ + /* Always valid ... */ \ + val = RTC_VRT; \ + break; \ + default: \ + break; \ + } \ + val; \ +}) + +#define __CMOS_WRITE(val, addr, s) ({ \ + unsigned char rcr1,rcr2; \ + switch(addr) { \ + case RTC_SECONDS: \ + ctrl_outb(val, RSECCNT); \ + break; \ + case RTC_SECONDS_ALARM: \ + ctrl_outb(val, RSECAR); \ + break; \ + case RTC_MINUTES: \ + ctrl_outb(val, RMINCNT); \ + break; \ + case RTC_MINUTES_ALARM: \ + ctrl_outb(val, RMINAR); \ + break; \ + case RTC_HOURS: \ + ctrl_outb(val, RHRCNT); \ + break; \ + case RTC_HOURS_ALARM: \ + ctrl_outb(val, RHRAR); \ + break; \ + case RTC_DAY_OF_WEEK: \ + ctrl_outb(val, RWKCNT); \ + break; \ + case RTC_DAY_OF_MONTH: \ + ctrl_outb(val, RDAYCNT); \ + break; \ + case RTC_MONTH: \ + ctrl_outb(val, RMONCNT); \ + break; \ + case RTC_YEAR: \ + ctrl_out##s((ctrl_in##s(RYRCNT) & 0xff00) | (val & 0xff), RYRCNT);\ + break; \ + case RTC_REG_A: /* RTC_FREQ_SELECT */ \ + rcr2 = ctrl_inb(RCR2); \ + if((val & RTC_DIV_CTL) == RTC_DIV_RESET2) \ + rcr2 |= RCR2_RESET; \ + ctrl_outb(rcr2, RCR2); \ + break; \ + case RTC_REG_B: /* RTC_CONTROL */ \ + rcr1 = (ctrl_inb(RCR1) & 0x99) | RCR1_AF; \ + if(val & RTC_AIE) rcr1 |= RCR1_AIE; \ + else rcr1 &= ~RCR1_AIE; \ + if(val & RTC_UIE) rcr1 |= RCR1_CIE; \ + else rcr1 &= ~RCR1_CIE; \ + ctrl_outb(rcr1, RCR1); \ + rcr2 = ctrl_inb(RCR2); \ + if(val & RTC_SET) rcr2 &= ~RCR2_START; \ + else rcr2 |= RCR2_START; \ + ctrl_outb(rcr2, RCR2); \ + break; \ + case RTC_REG_C: /* RTC_INTR_FLAGS */ \ + break; \ + case RTC_REG_D: /* RTC_VALID */ \ + break; \ + default: \ + break; \ + } \ +}) + +#endif /* CONFIG_SH_MPC1211 */ +#endif /* _ASM_MC146818RTC_H */ diff --git a/include/asm-sh/microdev/io.h b/include/asm-sh/microdev/io.h new file mode 100644 index 0000000..f2ca4ac --- /dev/null +++ b/include/asm-sh/microdev/io.h @@ -0,0 +1,53 @@ +/* + * linux/include/asm-sh/io_microdev.h + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * + * IO functions for the SuperH SH4-202 MicroDev board. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + */ + + +#ifndef _ASM_SH_IO_MICRODEV_H +#define _ASM_SH_IO_MICRODEV_H + +extern unsigned long microdev_isa_port2addr(unsigned long offset); + +extern unsigned char microdev_inb(unsigned long port); +extern unsigned short microdev_inw(unsigned long port); +extern unsigned int microdev_inl(unsigned long port); + +extern void microdev_outb(unsigned char value, unsigned long port); +extern void microdev_outw(unsigned short value, unsigned long port); +extern void microdev_outl(unsigned int value, unsigned long port); + +extern unsigned char microdev_inb_p(unsigned long port); +extern unsigned short microdev_inw_p(unsigned long port); +extern unsigned int microdev_inl_p(unsigned long port); + +extern void microdev_outb_p(unsigned char value, unsigned long port); +extern void microdev_outw_p(unsigned short value, unsigned long port); +extern void microdev_outl_p(unsigned int value, unsigned long port); + +extern void microdev_insb(unsigned long port, void *addr, unsigned long count); +extern void microdev_insw(unsigned long port, void *addr, unsigned long count); +extern void microdev_insl(unsigned long port, void *addr, unsigned long count); + +extern void microdev_outsb(unsigned long port, const void *addr, unsigned long count); +extern void microdev_outsw(unsigned long port, const void *addr, unsigned long count); +extern void microdev_outsl(unsigned long port, const void *addr, unsigned long count); + +#if defined(CONFIG_PCI) +extern unsigned char microdev_pci_inb(unsigned long port); +extern unsigned short microdev_pci_inw(unsigned long port); +extern unsigned long microdev_pci_inl(unsigned long port); +extern void microdev_pci_outb(unsigned char data, unsigned long port); +extern void microdev_pci_outw(unsigned short data, unsigned long port); +extern void microdev_pci_outl(unsigned long data, unsigned long port); +#endif + +#endif /* _ASM_SH_IO_MICRODEV_H */ + diff --git a/include/asm-sh/microdev/irq.h b/include/asm-sh/microdev/irq.h new file mode 100644 index 0000000..47f6f77 --- /dev/null +++ b/include/asm-sh/microdev/irq.h @@ -0,0 +1,72 @@ +/* + * linux/include/asm-sh/irq_microdev.h + * + * Copyright (C) 2003 Sean McGoogan (Sean.McGoogan@superh.com) + * + * IRQ functions for the SuperH SH4-202 MicroDev board. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + */ + + +#ifndef _ASM_SH_IRQ_MICRODEV_H +#define _ASM_SH_IRQ_MICRODEV_H + +extern void init_microdev_irq(void); +extern void microdev_print_fpga_intc_status(void); + + + /* + * The following are useful macros for manipulating the + * interrupt controller (INTC) on the CPU-board FPGA. + * It should be noted that there is an INTC on the FPGA, + * and a seperate INTC on the SH4-202 core - these are + * two different things, both of which need to be prorammed + * to correctly route - unfortunately, they have the + * same name and abbreviations! + */ +#define MICRODEV_FPGA_INTC_BASE 0xa6110000ul /* INTC base address on CPU-board FPGA */ +#define MICRODEV_FPGA_INTENB_REG (MICRODEV_FPGA_INTC_BASE+0ul) /* Interrupt Enable Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTDSB_REG (MICRODEV_FPGA_INTC_BASE+8ul) /* Interrupt Disable Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTC_MASK(n) (1ul<<(n)) /* Interupt mask to enable/disable INTC in CPU-board FPGA */ +#define MICRODEV_FPGA_INTPRI_REG(n) (MICRODEV_FPGA_INTC_BASE+0x10+((n)/8)*8)/* Interrupt Priority Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTPRI_LEVEL(n,x) ((x)<<(((n)%8)*4)) /* MICRODEV_FPGA_INTPRI_LEVEL(int_number, int_level) */ +#define MICRODEV_FPGA_INTPRI_MASK(n) (MICRODEV_FPGA_INTPRI_LEVEL((n),0xful)) /* Interrupt Priority Mask on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTSRC_REG (MICRODEV_FPGA_INTC_BASE+0x30ul) /* Interrupt Source Register on INTC on CPU-board FPGA */ +#define MICRODEV_FPGA_INTREQ_REG (MICRODEV_FPGA_INTC_BASE+0x38ul) /* Interrupt Request Register on INTC on CPU-board FPGA */ + + + /* + * The following are the IRQ numbers for the Linux Kernel for external interrupts. + * i.e. the numbers seen by 'cat /proc/interrupt'. + */ +#define MICRODEV_LINUX_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ +#define MICRODEV_LINUX_IRQ_SERIAL1 2 /* SuperIO Serial #1 */ +#define MICRODEV_LINUX_IRQ_ETHERNET 3 /* on-board Ethnernet */ +#define MICRODEV_LINUX_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ +#define MICRODEV_LINUX_IRQ_USB_HC 7 /* on-board USB HC */ +#define MICRODEV_LINUX_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ +#define MICRODEV_LINUX_IRQ_IDE2 13 /* SuperIO IDE #2 */ +#define MICRODEV_LINUX_IRQ_IDE1 14 /* SuperIO IDE #1 */ + + /* + * The following are the IRQ numbers for the INTC on the FPGA for external interrupts. + * i.e. the bits in the INTC registers in the FPGA. + */ +#define MICRODEV_FPGA_IRQ_KEYBOARD 1 /* SuperIO Keyboard */ +#define MICRODEV_FPGA_IRQ_SERIAL1 3 /* SuperIO Serial #1 */ +#define MICRODEV_FPGA_IRQ_SERIAL2 4 /* SuperIO Serial #2 */ +#define MICRODEV_FPGA_IRQ_MOUSE 12 /* SuperIO PS/2 Mouse */ +#define MICRODEV_FPGA_IRQ_IDE1 14 /* SuperIO IDE #1 */ +#define MICRODEV_FPGA_IRQ_IDE2 15 /* SuperIO IDE #2 */ +#define MICRODEV_FPGA_IRQ_USB_HC 16 /* on-board USB HC */ +#define MICRODEV_FPGA_IRQ_ETHERNET 18 /* on-board Ethnernet */ + +#define MICRODEV_IRQ_PCI_INTA 8 +#define MICRODEV_IRQ_PCI_INTB 9 +#define MICRODEV_IRQ_PCI_INTC 10 +#define MICRODEV_IRQ_PCI_INTD 11 + +#endif /* _ASM_SH_IRQ_MICRODEV_H */ diff --git a/include/asm-sh/mman.h b/include/asm-sh/mman.h new file mode 100644 index 0000000..3ebab5f --- /dev/null +++ b/include/asm-sh/mman.h @@ -0,0 +1,43 @@ +#ifndef __ASM_SH_MMAN_H +#define __ASM_SH_MMAN_H + +#define PROT_READ 0x1 /* page can be read */ +#define PROT_WRITE 0x2 /* page can be written */ +#define PROT_EXEC 0x4 /* page can be executed */ +#define PROT_SEM 0x8 /* page may be used for atomic ops */ +#define PROT_NONE 0x0 /* page can not be accessed */ +#define PROT_GROWSDOWN 0x01000000 /* mprotect flag: extend change to start of growsdown vma */ +#define PROT_GROWSUP 0x02000000 /* mprotect flag: extend change to end of growsup vma */ + +#define MAP_SHARED 0x01 /* Share changes */ +#define MAP_PRIVATE 0x02 /* Changes are private */ +#define MAP_TYPE 0x0f /* Mask for type of mapping */ +#define MAP_FIXED 0x10 /* Interpret addr exactly */ +#define MAP_ANONYMOUS 0x20 /* don't use a file */ + +#define MAP_GROWSDOWN 0x0100 /* stack-like segment */ +#define MAP_DENYWRITE 0x0800 /* ETXTBSY */ +#define MAP_EXECUTABLE 0x1000 /* mark it as an executable */ +#define MAP_LOCKED 0x2000 /* pages are locked */ +#define MAP_NORESERVE 0x4000 /* don't check for reservations */ +#define MAP_POPULATE 0x8000 /* populate (prefault) page tables */ +#define MAP_NONBLOCK 0x10000 /* do not block on IO */ + +#define MS_ASYNC 1 /* sync memory asynchronously */ +#define MS_INVALIDATE 2 /* invalidate the caches */ +#define MS_SYNC 4 /* synchronous memory sync */ + +#define MCL_CURRENT 1 /* lock all current mappings */ +#define MCL_FUTURE 2 /* lock all future mappings */ + +#define MADV_NORMAL 0x0 /* default page-in behavior */ +#define MADV_RANDOM 0x1 /* page-in minimum required */ +#define MADV_SEQUENTIAL 0x2 /* read-ahead aggressively */ +#define MADV_WILLNEED 0x3 /* pre-fault pages */ +#define MADV_DONTNEED 0x4 /* discard these pages */ + +/* compatibility flags */ +#define MAP_ANON MAP_ANONYMOUS +#define MAP_FILE 0 + +#endif /* __ASM_SH_MMAN_H */ diff --git a/include/asm-sh/mmu.h b/include/asm-sh/mmu.h new file mode 100644 index 0000000..72f07be --- /dev/null +++ b/include/asm-sh/mmu.h @@ -0,0 +1,29 @@ +#ifndef __MMU_H +#define __MMU_H + +#if !defined(CONFIG_MMU) + +struct mm_rblock_struct { + int size; + int refcount; + void *kblock; +}; + +struct mm_tblock_struct { + struct mm_rblock_struct *rblock; + struct mm_tblock_struct *next; +}; + +typedef struct { + struct mm_tblock_struct tblock; + unsigned long end_brk; +} mm_context_t; + +#else + +/* Default "unsigned long" context */ +typedef unsigned long mm_context_t; + +#endif /* CONFIG_MMU */ +#endif /* __MMH_H */ + diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h new file mode 100644 index 0000000..6760d06 --- /dev/null +++ b/include/asm-sh/mmu_context.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * ASID handling idea taken from MIPS implementation. + */ +#ifndef __ASM_SH_MMU_CONTEXT_H +#define __ASM_SH_MMU_CONTEXT_H +#ifdef __KERNEL__ + +#include <asm/cpu/mmu_context.h> +#include <asm/tlbflush.h> +#include <asm/pgalloc.h> +#include <asm/uaccess.h> +#include <asm/io.h> + +/* + * The MMU "context" consists of two things: + * (a) TLB cache version (or round, cycle whatever expression you like) + * (b) ASID (Address Space IDentifier) + */ + +/* + * Cache of MMU context last used. + */ +extern unsigned long mmu_context_cache; + +#define MMU_CONTEXT_ASID_MASK 0x000000ff +#define MMU_CONTEXT_VERSION_MASK 0xffffff00 +#define MMU_CONTEXT_FIRST_VERSION 0x00000100 +#define NO_CONTEXT 0 + +/* ASID is 8-bit value, so it can't be 0x100 */ +#define MMU_NO_ASID 0x100 + +/* + * Virtual Page Number mask + */ +#define MMU_VPN_MASK 0xfffff000 + +#ifdef CONFIG_MMU +/* + * Get MMU context if needed. + */ +static __inline__ void +get_mmu_context(struct mm_struct *mm) +{ + extern void flush_tlb_all(void); + unsigned long mc = mmu_context_cache; + + /* Check if we have old version of context. */ + if (((mm->context ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0) + /* It's up to date, do nothing */ + return; + + /* It's old, we need to get new context with new version. */ + mc = ++mmu_context_cache; + if (!(mc & MMU_CONTEXT_ASID_MASK)) { + /* + * We exhaust ASID of this version. + * Flush all TLB and start new cycle. + */ + flush_tlb_all(); + /* + * Fix version; Note that we avoid version #0 + * to distingush NO_CONTEXT. + */ + if (!mc) + mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION; + } + mm->context = mc; +} + +/* + * Initialize the context related info for a new mm_struct + * instance. + */ +static __inline__ int init_new_context(struct task_struct *tsk, + struct mm_struct *mm) +{ + mm->context = NO_CONTEXT; + + return 0; +} + +/* + * Destroy context related info for an mm_struct that is about + * to be put to rest. + */ +static __inline__ void destroy_context(struct mm_struct *mm) +{ + /* Do nothing */ +} + +static __inline__ void set_asid(unsigned long asid) +{ + unsigned long __dummy; + + __asm__ __volatile__ ("mov.l %2, %0\n\t" + "and %3, %0\n\t" + "or %1, %0\n\t" + "mov.l %0, %2" + : "=&r" (__dummy) + : "r" (asid), "m" (__m(MMU_PTEH)), + "r" (0xffffff00)); +} + +static __inline__ unsigned long get_asid(void) +{ + unsigned long asid; + + __asm__ __volatile__ ("mov.l %1, %0" + : "=r" (asid) + : "m" (__m(MMU_PTEH))); + asid &= MMU_CONTEXT_ASID_MASK; + return asid; +} + +/* + * After we have set current->mm to a new value, this activates + * the context for the new mm so we see the new mappings. + */ +static __inline__ void activate_context(struct mm_struct *mm) +{ + get_mmu_context(mm); + set_asid(mm->context & MMU_CONTEXT_ASID_MASK); +} + +/* MMU_TTB can be used for optimizing the fault handling. + (Currently not used) */ +static __inline__ void switch_mm(struct mm_struct *prev, + struct mm_struct *next, + struct task_struct *tsk) +{ + if (likely(prev != next)) { + unsigned long __pgdir = (unsigned long)next->pgd; + + __asm__ __volatile__("mov.l %0, %1" + : /* no output */ + : "r" (__pgdir), "m" (__m(MMU_TTB))); + activate_context(next); + } +} + +#define deactivate_mm(tsk,mm) do { } while (0) + +#define activate_mm(prev, next) \ + switch_mm((prev),(next),NULL) + +static __inline__ void +enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk) +{ +} +#else /* !CONFIG_MMU */ +#define get_mmu_context(mm) do { } while (0) +#define init_new_context(tsk,mm) (0) +#define destroy_context(mm) do { } while (0) +#define set_asid(asid) do { } while (0) +#define get_asid() (0) +#define activate_context(mm) do { } while (0) +#define switch_mm(prev,next,tsk) do { } while (0) +#define deactivate_mm(tsk,mm) do { } while (0) +#define activate_mm(prev,next) do { } while (0) +#define enter_lazy_tlb(mm,tsk) do { } while (0) +#endif /* CONFIG_MMU */ + +#if defined(CONFIG_CPU_SH3) || defined(CONFIG_CPU_SH4) +/* + * If this processor has an MMU, we need methods to turn it off/on .. + * paging_init() will also have to be updated for the processor in + * question. + */ +static inline void enable_mmu(void) +{ + /* Enable MMU */ + ctrl_outl(MMU_CONTROL_INIT, MMUCR); + + /* The manual suggests doing some nops after turning on the MMU */ + __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t"); + + if (mmu_context_cache == NO_CONTEXT) + mmu_context_cache = MMU_CONTEXT_FIRST_VERSION; + + set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK); +} + +static inline void disable_mmu(void) +{ + unsigned long cr; + + cr = ctrl_inl(MMUCR); + cr &= ~MMU_CONTROL_INIT; + ctrl_outl(cr, MMUCR); + __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop\n\t"); +} +#else +/* + * MMU control handlers for processors lacking memory + * management hardware. + */ +#define enable_mmu() do { BUG(); } while (0) +#define disable_mmu() do { BUG(); } while (0) +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_MMU_CONTEXT_H */ diff --git a/include/asm-sh/mmzone.h b/include/asm-sh/mmzone.h new file mode 100644 index 0000000..0e74066 --- /dev/null +++ b/include/asm-sh/mmzone.h @@ -0,0 +1,61 @@ +/* + * linux/include/asm-sh/mmzone.h + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +#ifndef __ASM_SH_MMZONE_H +#define __ASM_SH_MMZONE_H + +#include <linux/config.h> + +#ifdef CONFIG_DISCONTIGMEM + +/* Currently, just for HP690 */ +#define PHYSADDR_TO_NID(phys) ((((phys) - __MEMORY_START) >= 0x01000000)?1:0) + +extern pg_data_t discontig_page_data[MAX_NUMNODES]; +extern bootmem_data_t discontig_node_bdata[MAX_NUMNODES]; + +/* + * Following are macros that each numa implmentation must define. + */ + +/* + * Given a kernel address, find the home node of the underlying memory. + */ +#define KVADDR_TO_NID(kaddr) PHYSADDR_TO_NID(__pa(kaddr)) + +/* + * Return a pointer to the node data for node n. + */ +#define NODE_DATA(nid) (&discontig_page_data[nid]) + +/* + * NODE_MEM_MAP gives the kaddr for the mem_map of the node. + */ +#define NODE_MEM_MAP(nid) (NODE_DATA(nid)->node_mem_map) + +#define phys_to_page(phys) \ +({ unsigned int node = PHYSADDR_TO_NID(phys); \ + NODE_MEM_MAP(node) \ + + (((phys) - NODE_DATA(node)->node_start_paddr) >> PAGE_SHIFT); }) + +static inline int is_valid_page(struct page *page) +{ + unsigned int i; + + for (i = 0; i < MAX_NUMNODES; i++) { + if (page >= NODE_MEM_MAP(i) && + page < NODE_MEM_MAP(i) + NODE_DATA(i)->node_size) + return 1; + } + return 0; +} + +#define VALID_PAGE(page) is_valid_page(page) +#define page_to_phys(page) PHYSADDR(page_address(page)) + +#endif /* CONFIG_DISCONTIGMEM */ +#endif diff --git a/include/asm-sh/module.h b/include/asm-sh/module.h new file mode 100644 index 0000000..118d5a2 --- /dev/null +++ b/include/asm-sh/module.h @@ -0,0 +1,40 @@ +#ifndef _ASM_SH_MODULE_H +#define _ASM_SH_MODULE_H + +/* + * This file contains the SH architecture specific module code. + */ + +struct mod_arch_specific { + /* Nothing to see here .. */ +}; + +#define Elf_Shdr Elf32_Shdr +#define Elf_Sym Elf32_Sym +#define Elf_Ehdr Elf32_Ehdr + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +# ifdef CONFIG_CPU_SH2 +# define MODULE_PROC_FAMILY "SH2LE " +# elif defined CONFIG_CPU_SH3 +# define MODULE_PROC_FAMILY "SH3LE " +# elif defined CONFIG_CPU_SH4 +# define MODULE_PROC_FAMILY "SH4LE " +# else +# error unknown processor family +# endif +#else +# ifdef CONFIG_CPU_SH2 +# define MODULE_PROC_FAMILY "SH2BE " +# elif defined CONFIG_CPU_SH3 +# define MODULE_PROC_FAMILY "SH3BE " +# elif defined CONFIG_CPU_SH4 +# define MODULE_PROC_FAMILY "SH4BE " +# else +# error unknown processor family +# endif +#endif + +#define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY + +#endif /* _ASM_SH_MODULE_H */ diff --git a/include/asm-sh/mpc1211/dma.h b/include/asm-sh/mpc1211/dma.h new file mode 100644 index 0000000..0a2fdab --- /dev/null +++ b/include/asm-sh/mpc1211/dma.h @@ -0,0 +1,304 @@ +/* $Id: dma.h,v 1.7 1992/12/14 00:29:34 root Exp root $ + * linux/include/asm/dma.h: Defines for using and allocating dma channels. + * Written by Hennus Bergman, 1992. + * High DMA channel support & info by Hannu Savolainen + * and John Boyd, Nov. 1992. + */ + +#ifndef _ASM_MPC1211_DMA_H +#define _ASM_MPC1211_DMA_H + +#include <linux/config.h> +#include <linux/spinlock.h> /* And spinlocks */ +#include <asm/io.h> /* need byte IO */ +#include <linux/delay.h> + + +#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER +#define dma_outb outb_p +#else +#define dma_outb outb +#endif + +#define dma_inb inb + +/* + * NOTES about DMA transfers: + * + * controller 1: channels 0-3, byte operations, ports 00-1F + * controller 2: channels 4-7, word operations, ports C0-DF + * + * - ALL registers are 8 bits only, regardless of transfer size + * - channel 4 is not used - cascades 1 into 2. + * - channels 0-3 are byte - addresses/counts are for physical bytes + * - channels 5-7 are word - addresses/counts are for physical words + * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries + * - transfer count loaded to registers is 1 less than actual count + * - controller 2 offsets are all even (2x offsets for controller 1) + * - page registers for 5-7 don't use data bit 0, represent 128K pages + * - page registers for 0-3 use bit 0, represent 64K pages + * + * DMA transfers are limited to the lower 16MB of _physical_ memory. + * Note that addresses loaded into registers must be _physical_ addresses, + * not logical addresses (which may differ if paging is active). + * + * Address mapping for channels 0-3: + * + * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses) + * | ... | | ... | | ... | + * | ... | | ... | | ... | + * | ... | | ... | | ... | + * P7 ... P0 A7 ... A0 A7 ... A0 + * | Page | Addr MSB | Addr LSB | (DMA registers) + * + * Address mapping for channels 5-7: + * + * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses) + * | ... | \ \ ... \ \ \ ... \ \ + * | ... | \ \ ... \ \ \ ... \ (not used) + * | ... | \ \ ... \ \ \ ... \ + * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 + * | Page | Addr MSB | Addr LSB | (DMA registers) + * + * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses + * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at + * the hardware level, so odd-byte transfers aren't possible). + * + * Transfer count (_not # bytes_) is limited to 64K, represented as actual + * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, + * and up to 128K bytes may be transferred on channels 5-7 in one operation. + * + */ + +#define MAX_DMA_CHANNELS 8 + +/* The maximum address that we can perform a DMA transfer to on this platform */ +#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000) + +/* 8237 DMA controllers */ +#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ +#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ + +/* DMA controller registers */ +#define DMA1_CMD_REG 0x08 /* command register (w) */ +#define DMA1_STAT_REG 0x08 /* status register (r) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ +#define DMA1_MODE_REG 0x0B /* mode register (w) */ +#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ + +#define DMA2_CMD_REG 0xD0 /* command register (w) */ +#define DMA2_STAT_REG 0xD0 /* status register (r) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ +#define DMA2_MODE_REG 0xD6 /* mode register (w) */ +#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ + +#define DMA_ADDR_0 0x00 /* DMA address registers */ +#define DMA_ADDR_1 0x02 +#define DMA_ADDR_2 0x04 +#define DMA_ADDR_3 0x06 +#define DMA_ADDR_4 0xC0 +#define DMA_ADDR_5 0xC4 +#define DMA_ADDR_6 0xC8 +#define DMA_ADDR_7 0xCC + +#define DMA_CNT_0 0x01 /* DMA count registers */ +#define DMA_CNT_1 0x03 +#define DMA_CNT_2 0x05 +#define DMA_CNT_3 0x07 +#define DMA_CNT_4 0xC2 +#define DMA_CNT_5 0xC6 +#define DMA_CNT_6 0xCA +#define DMA_CNT_7 0xCE + +#define DMA_PAGE_0 0x87 /* DMA page registers */ +#define DMA_PAGE_1 0x83 +#define DMA_PAGE_2 0x81 +#define DMA_PAGE_3 0x82 +#define DMA_PAGE_5 0x8B +#define DMA_PAGE_6 0x89 +#define DMA_PAGE_7 0x8A + +#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ +#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ + +#define DMA_AUTOINIT 0x10 + + +extern spinlock_t dma_spin_lock; + +static __inline__ unsigned long claim_dma_lock(void) +{ + unsigned long flags; + spin_lock_irqsave(&dma_spin_lock, flags); + return flags; +} + +static __inline__ void release_dma_lock(unsigned long flags) +{ + spin_unlock_irqrestore(&dma_spin_lock, flags); +} + +/* enable/disable a specific DMA channel */ +static __inline__ void enable_dma(unsigned int dmanr) +{ + if (dmanr<=3) + dma_outb(dmanr, DMA1_MASK_REG); + else + dma_outb(dmanr & 3, DMA2_MASK_REG); +} + +static __inline__ void disable_dma(unsigned int dmanr) +{ + if (dmanr<=3) + dma_outb(dmanr | 4, DMA1_MASK_REG); + else + dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); +} + +/* Clear the 'DMA Pointer Flip Flop'. + * Write 0 for LSB/MSB, 1 for MSB/LSB access. + * Use this once to initialize the FF to a known state. + * After that, keep track of it. :-) + * --- In order to do that, the DMA routines below should --- + * --- only be used while holding the DMA lock ! --- + */ +static __inline__ void clear_dma_ff(unsigned int dmanr) +{ + if (dmanr<=3) + dma_outb(0, DMA1_CLEAR_FF_REG); + else + dma_outb(0, DMA2_CLEAR_FF_REG); +} + +/* set mode (above) for a specific DMA channel */ +static __inline__ void set_dma_mode(unsigned int dmanr, char mode) +{ + if (dmanr<=3) + dma_outb(mode | dmanr, DMA1_MODE_REG); + else + dma_outb(mode | (dmanr&3), DMA2_MODE_REG); +} + +/* Set only the page register bits of the transfer address. + * This is used for successive transfers when we know the contents of + * the lower 16 bits of the DMA current address register, but a 64k boundary + * may have been crossed. + */ +static __inline__ void set_dma_page(unsigned int dmanr, unsigned int pagenr) +{ + switch(dmanr) { + case 0: + dma_outb( pagenr & 0xff, DMA_PAGE_0); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_0 + 0x400); + break; + case 1: + dma_outb( pagenr & 0xff, DMA_PAGE_1); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_1 + 0x400); + break; + case 2: + dma_outb( pagenr & 0xff, DMA_PAGE_2); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_2 + 0x400); + break; + case 3: + dma_outb( pagenr & 0xff, DMA_PAGE_3); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_3 + 0x400); + break; + case 5: + dma_outb( pagenr & 0xfe, DMA_PAGE_5); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_5 + 0x400); + break; + case 6: + dma_outb( pagenr & 0xfe, DMA_PAGE_6); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_6 + 0x400); + break; + case 7: + dma_outb( pagenr & 0xfe, DMA_PAGE_7); + dma_outb((pagenr >> 8) & 0xff, DMA_PAGE_7 + 0x400); + break; + } +} + + +/* Set transfer address & page bits for specific DMA channel. + * Assumes dma flipflop is clear. + */ +static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) +{ + set_dma_page(dmanr, a>>16); + if (dmanr <= 3) { + dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); + dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); + } else { + dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); + dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); + } +} + + +/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for + * a specific DMA channel. + * You must ensure the parameters are valid. + * NOTE: from a manual: "the number of transfers is one more + * than the initial word count"! This is taken into account. + * Assumes dma flip-flop is clear. + * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. + */ +static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) +{ + count--; + if (dmanr <= 3) { + dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); + dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); + } else { + dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); + dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); + } +} + + +/* Get DMA residue count. After a DMA transfer, this + * should return zero. Reading this while a DMA transfer is + * still in progress will return unpredictable results. + * If called before the channel has been used, it may return 1. + * Otherwise, it returns the number of _bytes_ left to transfer. + * + * Assumes DMA flip-flop is clear. + */ +static __inline__ int get_dma_residue(unsigned int dmanr) +{ + unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE + : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; + + /* using short to get 16-bit wrap around */ + unsigned short count; + + count = 1 + dma_inb(io_port); + count += dma_inb(io_port) << 8; + return (dmanr<=3)? count : (count<<1); +} + + +/* These are in kernel/dma.c: */ +extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ +extern void free_dma(unsigned int dmanr); /* release it again */ + +/* From PCI */ + +#ifdef CONFIG_PCI +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) +#endif + +#endif /* _ASM_MPC1211_DMA_H */ diff --git a/include/asm-sh/mpc1211/io.h b/include/asm-sh/mpc1211/io.h new file mode 100644 index 0000000..eba8a0b --- /dev/null +++ b/include/asm-sh/mpc1211/io.h @@ -0,0 +1,22 @@ +/* + * include/asm-sh/io_mpc1211.h + * + * Copyright 2001 Saito.K & Jeanne + * + * IO functions for an Interface MPC-1211 + */ + +#ifndef _ASM_SH_IO_MPC1211_H +#define _ASM_SH_IO_MPC1211_H + +#include <linux/time.h> + +extern int mpc1211_irq_demux(int irq); + +extern void init_mpc1211_IRQ(void); +extern void heartbeat_mpc1211(void); + +extern void mpc1211_rtc_gettimeofday(struct timeval *tv); +extern int mpc1211_rtc_settimeofday(const struct timeval *tv); + +#endif /* _ASM_SH_IO_MPC1211_H */ diff --git a/include/asm-sh/mpc1211/keyboard.h b/include/asm-sh/mpc1211/keyboard.h new file mode 100644 index 0000000..5f0b908 --- /dev/null +++ b/include/asm-sh/mpc1211/keyboard.h @@ -0,0 +1,64 @@ +/* + * MPC1211 specific keybord definitions + * Taken from the old asm-i386/keybord.h for PC/AT-style definitions + * created 3 Nov 1996 by Geert Uytterhoeven. + */ + +#ifdef __KERNEL__ + +#include <linux/kernel.h> +#include <linux/ioport.h> +#include <linux/kd.h> +#include <linux/pm.h> +#include <asm/io.h> + +#define KEYBOARD_IRQ 1 +#define DISABLE_KBD_DURING_INTERRUPTS 0 + +extern int pckbd_setkeycode(unsigned int scancode, unsigned int keycode); +extern int pckbd_getkeycode(unsigned int scancode); +extern int pckbd_translate(unsigned char scancode, unsigned char *keycode, + char raw_mode); +extern char pckbd_unexpected_up(unsigned char keycode); +extern void pckbd_leds(unsigned char leds); +extern void pckbd_init_hw(void); +extern int pckbd_pm_resume(struct pm_dev *, pm_request_t, void *); +extern pm_callback pm_kbd_request_override; +extern unsigned char pckbd_sysrq_xlate[128]; + +#define kbd_setkeycode pckbd_setkeycode +#define kbd_getkeycode pckbd_getkeycode +#define kbd_translate pckbd_translate +#define kbd_unexpected_up pckbd_unexpected_up +#define kbd_leds pckbd_leds +#define kbd_init_hw pckbd_init_hw +#define kbd_sysrq_xlate pckbd_sysrq_xlate + +#define SYSRQ_KEY 0x54 + +/* resource allocation */ +#define kbd_request_region() +#define kbd_request_irq(handler) request_irq(KEYBOARD_IRQ, handler, 0, \ + "keyboard", NULL) + +/* How to access the keyboard macros on this platform. */ +#define kbd_read_input() inb(KBD_DATA_REG) +#define kbd_read_status() inb(KBD_STATUS_REG) +#define kbd_write_output(val) outb(val, KBD_DATA_REG) +#define kbd_write_command(val) outb(val, KBD_CNTL_REG) + +/* Some stoneage hardware needs delays after some operations. */ +#define kbd_pause() do { } while(0) + +/* + * Machine specific bits for the PS/2 driver + */ + +#define AUX_IRQ 12 + +#define aux_request_irq(hand, dev_id) \ + request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS2 Mouse", dev_id) + +#define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) + +#endif /* __KERNEL__ */ diff --git a/include/asm-sh/mpc1211/m1543c.h b/include/asm-sh/mpc1211/m1543c.h new file mode 100644 index 0000000..c95d132 --- /dev/null +++ b/include/asm-sh/mpc1211/m1543c.h @@ -0,0 +1,200 @@ +#ifndef __ASM_SH_M1543C_H +#define __ASM_SH_M1543C_H + +/* + * linux/include/asm-sh/m1543c.h + * Copyright (C) 2001 Nobuhiro Sakawa + * M1543C:PCI-ISA Bus Bridge with Super IO Chip support + * + * from + * + * linux/include/asm-sh/smc37c93x.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * SMSC 37C93x Super IO Chip support + */ + +/* Default base I/O address */ +#define FDC_PRIMARY_BASE 0x3f0 +#define IDE1_PRIMARY_BASE 0x1f0 +#define IDE1_SECONDARY_BASE 0x170 +#define PARPORT_PRIMARY_BASE 0x378 +#define COM1_PRIMARY_BASE 0x2f8 +#define COM2_PRIMARY_BASE 0x3f8 +#define COM3_PRIMARY_BASE 0x3e8 +#define RTC_PRIMARY_BASE 0x070 +#define KBC_PRIMARY_BASE 0x060 +#define AUXIO_PRIMARY_BASE 0x000 /* XXX */ +#define I8259_M_CR 0x20 +#define I8259_M_MR 0x21 +#define I8259_S_CR 0xa0 +#define I8259_S_MR 0xa1 + +/* Logical device number */ +#define LDN_FDC 0 +#define LDN_IDE1 1 +#define LDN_IDE2 2 +#define LDN_PARPORT 3 +#define LDN_COM1 4 +#define LDN_COM2 5 +#define LDN_COM3 11 +#define LDN_RTC 6 +#define LDN_KBC 7 + +/* Configuration port and key */ +#define CONFIG_PORT 0x3f0 +#define INDEX_PORT CONFIG_PORT +#define DATA_PORT 0x3f1 +#define CONFIG_ENTER1 0x51 +#define CONFIG_ENTER2 0x23 +#define CONFIG_EXIT 0xbb + +/* Configuration index */ +#define CURRENT_LDN_INDEX 0x07 +#define POWER_CONTROL_INDEX 0x22 +#define ACTIVATE_INDEX 0x30 +#define IO_BASE_HI_INDEX 0x60 +#define IO_BASE_LO_INDEX 0x61 +#define IRQ_SELECT_INDEX 0x70 +#define PS2_IRQ_INDEX 0x72 +#define DMA_SELECT_INDEX 0x74 + +/* UART stuff. Only for debugging. */ +/* UART Register */ + +#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ +#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ +#define UART_IER 0x2 /* Interrupt Enable Register */ +#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ +#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ +#define UART_LCR 0x6 /* Line Control Register */ +#define UART_MCR 0x8 /* MODEM Control Register */ +#define UART_LSR 0xa /* Line Status Register */ +#define UART_MSR 0xc /* MODEM Status Register */ +#define UART_SCR 0xe /* Scratch Register */ +#define UART_DLL 0x0 /* Divisor Latch (LS) */ +#define UART_DLM 0x2 /* Divisor Latch (MS) */ + +#ifndef __ASSEMBLY__ +typedef struct uart_reg { + volatile __u16 rbr; + volatile __u16 ier; + volatile __u16 iir; + volatile __u16 lcr; + volatile __u16 mcr; + volatile __u16 lsr; + volatile __u16 msr; + volatile __u16 scr; +} uart_reg; +#endif /* ! __ASSEMBLY__ */ + +/* Alias for Write Only Register */ + +#define thr rbr +#define tcr iir + +/* Alias for Divisor Latch Register */ + +#define dll rbr +#define dlm ier +#define fcr iir + +/* Interrupt Enable Register */ + +#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ +#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ +#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ +#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ + +/* Interrupt Ident Register */ + +#define IIR_IP 0x0100 /* "0" if Interrupt Pending */ +#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ +#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ +#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ +#define IIR_FIFO 0xc000 /* FIFOs enabled */ + +/* FIFO Control Register */ + +#define FCR_FEN 0x0100 /* FIFO enable */ +#define FCR_RFRES 0x0200 /* Receiver FIFO reset */ +#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ +#define FCR_DMA 0x0800 /* DMA mode select */ +#define FCR_RTL 0x4000 /* Receiver triger (LSB) */ +#define FCR_RTM 0x8000 /* Receiver triger (MSB) */ + +/* Line Control Register */ + +#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ +#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ +#define LCR_STB 0x0400 /* Number of Stop Bits */ +#define LCR_PEN 0x0800 /* Parity Enable */ +#define LCR_EPS 0x1000 /* Even Parity Select */ +#define LCR_SP 0x2000 /* Stick Parity */ +#define LCR_SB 0x4000 /* Set Break */ +#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ + +/* MODEM Control Register */ + +#define MCR_DTR 0x0100 /* Data Terminal Ready */ +#define MCR_RTS 0x0200 /* Request to Send */ +#define MCR_OUT1 0x0400 /* Out 1 */ +#define MCR_IRQEN 0x0800 /* IRQ Enable */ +#define MCR_LOOP 0x1000 /* Loop */ + +/* Line Status Register */ + +#define LSR_DR 0x0100 /* Data Ready */ +#define LSR_OE 0x0200 /* Overrun Error */ +#define LSR_PE 0x0400 /* Parity Error */ +#define LSR_FE 0x0800 /* Framing Error */ +#define LSR_BI 0x1000 /* Break Interrupt */ +#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ +#define LSR_TEMT 0x4000 /* Transmitter Empty */ +#define LSR_FIFOE 0x8000 /* Receiver FIFO error */ + +/* MODEM Status Register */ + +#define MSR_DCTS 0x0100 /* Delta Clear to Send */ +#define MSR_DDSR 0x0200 /* Delta Data Set Ready */ +#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ +#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ +#define MSR_CTS 0x1000 /* Clear to Send */ +#define MSR_DSR 0x2000 /* Data Set Ready */ +#define MSR_RI 0x4000 /* Ring Indicator */ +#define MSR_DCD 0x8000 /* Data Carrier Detect */ + +/* Baud Rate Divisor */ + +#define UART_CLK (1843200) /* 1.8432 MHz */ +#define UART_BAUD(x) (UART_CLK / (16 * (x))) + +/* RTC register definition */ +#define RTC_SECONDS 0 +#define RTC_SECONDS_ALARM 1 +#define RTC_MINUTES 2 +#define RTC_MINUTES_ALARM 3 +#define RTC_HOURS 4 +#define RTC_HOURS_ALARM 5 +#define RTC_DAY_OF_WEEK 6 +#define RTC_DAY_OF_MONTH 7 +#define RTC_MONTH 8 +#define RTC_YEAR 9 +#define RTC_FREQ_SELECT 10 +# define RTC_UIP 0x80 +# define RTC_DIV_CTL 0x70 +/* This RTC can work under 32.768KHz clock only. */ +# define RTC_OSC_ENABLE 0x20 +# define RTC_OSC_DISABLE 0x00 +#define RTC_CONTROL 11 +# define RTC_SET 0x80 +# define RTC_PIE 0x40 +# define RTC_AIE 0x20 +# define RTC_UIE 0x10 +# define RTC_SQWE 0x08 +# define RTC_DM_BINARY 0x04 +# define RTC_24H 0x02 +# define RTC_DST_EN 0x01 + +#endif /* __ASM_SH_M1543C_H */ diff --git a/include/asm-sh/mpc1211/mc146818rtc.h b/include/asm-sh/mpc1211/mc146818rtc.h new file mode 100644 index 0000000..0ec78f6 --- /dev/null +++ b/include/asm-sh/mpc1211/mc146818rtc.h @@ -0,0 +1,6 @@ +/* + * MPC1211 uses PC/AT style RTC definitions. + */ +#include <asm-i386/mc146818rtc.h> + + diff --git a/include/asm-sh/mpc1211/mpc1211.h b/include/asm-sh/mpc1211/mpc1211.h new file mode 100644 index 0000000..fa456c3 --- /dev/null +++ b/include/asm-sh/mpc1211/mpc1211.h @@ -0,0 +1,18 @@ +#ifndef __ASM_SH_MPC1211_H +#define __ASM_SH_MPC1211_H + +/* + * linux/include/asm-sh/mpc1211.h + * + * Copyright (C) 2001 Saito.K & Jeanne + * + * Interface MPC-1211 support + */ + +#define PA_PCI_IO (0xa4000000) /* PCI I/O space */ +#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */ + +#define PCIPAR (0xa4000cf8) /* PCI Config address */ +#define PCIPDR (0xa4000cfc) /* PCI Config data */ + +#endif /* __ASM_SH_MPC1211_H */ diff --git a/include/asm-sh/mpc1211/pci.h b/include/asm-sh/mpc1211/pci.h new file mode 100644 index 0000000..5d3712c --- /dev/null +++ b/include/asm-sh/mpc1211/pci.h @@ -0,0 +1,40 @@ +/* + * Low-Level PCI Support for MPC-1211 + * + * (c) 2002 Saito.K & Jeanne + * + */ + +#ifndef _PCI_MPC1211_H_ +#define _PCI_MPC1211_H_ + +#include <linux/pci.h> + +/* set debug level 4=verbose...1=terse */ +//#define DEBUG_PCI 3 +#undef DEBUG_PCI + +#ifdef DEBUG_PCI +#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } +#else +#define PCIDBG(n, x...) +#endif + +/* startup values */ +#define PCI_PROBE_BIOS 1 +#define PCI_PROBE_CONF1 2 +#define PCI_PROBE_CONF2 4 +#define PCI_NO_SORT 0x100 +#define PCI_BIOS_SORT 0x200 +#define PCI_NO_CHECKS 0x400 +#define PCI_ASSIGN_ROMS 0x1000 +#define PCI_BIOS_IRQ_SCAN 0x2000 + +/* MPC-1211 Specific Values */ +#define PCIPAR (0xa4000cf8) /* PCI Config address */ +#define PCIPDR (0xa4000cfc) /* PCI Config data */ + +#define PA_PCI_IO (0xa4000000) /* PCI I/O space */ +#define PA_PCI_MEM (0xb0000000) /* PCI MEM space */ + +#endif /* _PCI_MPC1211_H_ */ diff --git a/include/asm-sh/msgbuf.h b/include/asm-sh/msgbuf.h new file mode 100644 index 0000000..5174323 --- /dev/null +++ b/include/asm-sh/msgbuf.h @@ -0,0 +1,31 @@ +#ifndef __ASM_SH_MSGBUF_H +#define __ASM_SH_MSGBUF_H + +/* + * The msqid64_ds structure for i386 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct msqid64_ds { + struct ipc64_perm msg_perm; + __kernel_time_t msg_stime; /* last msgsnd time */ + unsigned long __unused1; + __kernel_time_t msg_rtime; /* last msgrcv time */ + unsigned long __unused2; + __kernel_time_t msg_ctime; /* last change time */ + unsigned long __unused3; + unsigned long msg_cbytes; /* current number of bytes on queue */ + unsigned long msg_qnum; /* number of messages in queue */ + unsigned long msg_qbytes; /* max number of bytes on queue */ + __kernel_pid_t msg_lspid; /* pid of last msgsnd */ + __kernel_pid_t msg_lrpid; /* last receive pid */ + unsigned long __unused4; + unsigned long __unused5; +}; + +#endif /* __ASM_SH_MSGBUF_H */ diff --git a/include/asm-sh/namei.h b/include/asm-sh/namei.h new file mode 100644 index 0000000..338a5d9 --- /dev/null +++ b/include/asm-sh/namei.h @@ -0,0 +1,17 @@ +/* $Id: namei.h,v 1.3 2000/07/04 06:24:49 gniibe Exp $ + * linux/include/asm-sh/namei.h + * + * Included from linux/fs/namei.c + */ + +#ifndef __ASM_SH_NAMEI_H +#define __ASM_SH_NAMEI_H + +/* This dummy routine maybe changed to something useful + * for /usr/gnemul/ emulation stuff. + * Look at asm-sparc/namei.h for details. + */ + +#define __emul_prefix() NULL + +#endif /* __ASM_SH_NAMEI_H */ diff --git a/include/asm-sh/numnodes.h b/include/asm-sh/numnodes.h new file mode 100644 index 0000000..f73e85b --- /dev/null +++ b/include/asm-sh/numnodes.h @@ -0,0 +1,7 @@ +#ifndef _ASM_MAX_NUMNODES_H +#define _ASM_MAX_NUMNODES_H + +/* Max 2 Nodes */ +#define NODES_SHIFT 1 + +#endif /* _ASM_MAX_NUMNODES_H */ diff --git a/include/asm-sh/overdrive/fpga.h b/include/asm-sh/overdrive/fpga.h new file mode 100644 index 0000000..1cd8799 --- /dev/null +++ b/include/asm-sh/overdrive/fpga.h @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2000 David J. Mckay (david.mckay@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + */ + +#ifndef __FPGA_OD_H__ +#define __FPGA_OD_H__ + +/* This routine will program up the fpga which interfaces to the galileo */ +int init_overdrive_fpga(void); + +#endif diff --git a/include/asm-sh/overdrive/gt64111.h b/include/asm-sh/overdrive/gt64111.h new file mode 100644 index 0000000..01d58bc --- /dev/null +++ b/include/asm-sh/overdrive/gt64111.h @@ -0,0 +1,109 @@ +#ifndef _GT64111_H_ +#define _GT64111_H_ + +#define MASTER_INTERFACE 0x0 +#define RAS10_LO_DEC_ADR 0x8 +#define RAS10_HI_DEC_ADR 0x10 +#define RAS32_LO_DEC_ADR 0x18 +#define RAS32_HI_DEC_ADR 0x20 +#define CS20_LO_DEC_ADR 0x28 +#define CS20_HI_DEC_ADR 0x30 +#define CS3_LO_DEC_ADR 0x38 +#define CS3_HI_DEC_ADR 0x40 +#define PCI_IO_LO_DEC_ADR 0x48 +#define PCI_IO_HI_DEC_ADR 0x50 +#define PCI_MEM0_LO_DEC_ADR 0x58 +#define PCI_MEM0_HI_DEC_ADR 0x60 +#define INTERNAL_SPACE_DEC 0x68 +#define BUS_ERR_ADR_LO_CPU 0x70 +#define READONLY0 0x78 +#define PCI_MEM1_LO_DEC_ADR 0x80 +#define PCI_MEM1_HI_DEC_ADR 0x88 +#define RAS0_LO_DEC_ADR 0x400 +#define RAS0_HI_DEC_ADR 0x404 +#define RAS1_LO_DEC_ADR 0x408 +#define RAS1_HI_DEC_ADR 0x40c +#define RAS2_LO_DEC_ADR 0x410 +#define RAS2_HI_DEC_ADR 0x414 +#define RAS3_LO_DEC_ADR 0x418 +#define RAS3_HI_DEC_ADR 0x41c +#define DEV_CS0_LO_DEC_ADR 0x420 +#define DEV_CS0_HI_DEC_ADR 0x424 +#define DEV_CS1_LO_DEC_ADR 0x428 +#define DEV_CS1_HI_DEC_ADR 0x42c +#define DEV_CS2_LO_DEC_ADR 0x430 +#define DEV_CS2_HI_DEC_ADR 0x434 +#define DEV_CS3_LO_DEC_ADR 0x438 +#define DEV_CS3_HI_DEC_ADR 0x43c +#define DEV_BOOTCS_LO_DEC_ADR 0x440 +#define DEV_BOOTCS_HI_DEC_ADR 0x444 +#define DEV_ADR_DEC_ERR 0x470 +#define DRAM_CFG 0x448 +#define DRAM_BANK0_PARMS 0x44c +#define DRAM_BANK1_PARMS 0x450 +#define DRAM_BANK2_PARMS 0x454 +#define DRAM_BANK3_PARMS 0x458 +#define DEV_BANK0_PARMS 0x45c +#define DEV_BANK1_PARMS 0x460 +#define DEV_BANK2_PARMS 0x464 +#define DEV_BANK3_PARMS 0x468 +#define DEV_BOOT_BANK_PARMS 0x46c +#define CH0_DMA_BYTECOUNT 0x800 +#define CH1_DMA_BYTECOUNT 0x804 +#define CH2_DMA_BYTECOUNT 0x808 +#define CH3_DMA_BYTECOUNT 0x80c +#define CH0_DMA_SRC_ADR 0x810 +#define CH1_DMA_SRC_ADR 0x814 +#define CH2_DMA_SRC_ADR 0x818 +#define CH3_DMA_SRC_ADR 0x81c +#define CH0_DMA_DST_ADR 0x820 +#define CH1_DMA_DST_ADR 0x824 +#define CH2_DMA_DST_ADR 0x828 +#define CH3_DMA_DST_ADR 0x82c +#define CH0_NEXT_REC_PTR 0x830 +#define CH1_NEXT_REC_PTR 0x834 +#define CH2_NEXT_REC_PTR 0x838 +#define CH3_NEXT_REC_PTR 0x83c +#define CH0_CTRL 0x840 +#define CH1_CTRL 0x844 +#define CH2_CTRL 0x848 +#define CH3_CTRL 0x84c +#define DMA_ARBITER 0x860 +#define TIMER0 0x850 +#define TIMER1 0x854 +#define TIMER2 0x858 +#define TIMER3 0x85c +#define TIMER_CTRL 0x864 +#define PCI_CMD 0xc00 +#define PCI_TIMEOUT 0xc04 +#define PCI_RAS10_BANK_SIZE 0xc08 +#define PCI_RAS32_BANK_SIZE 0xc0c +#define PCI_CS20_BANK_SIZE 0xc10 +#define PCI_CS3_BANK_SIZE 0xc14 +#define PCI_SERRMASK 0xc28 +#define PCI_INTACK 0xc34 +#define PCI_BAR_EN 0xc3c +#define PCI_CFG_ADR 0xcf8 +#define PCI_CFG_DATA 0xcfc +#define PCI_INTCAUSE 0xc18 +#define PCI_MAST_MASK 0xc1c +#define PCI_PCIMASK 0xc24 +#define BAR_ENABLE_ADR 0xc3c + +/* These are config registers, accessible via PCI space */ +#define PCI_CONFIG_RAS10_BASE_ADR 0x010 +#define PCI_CONFIG_RAS32_BASE_ADR 0x014 +#define PCI_CONFIG_CS20_BASE_ADR 0x018 +#define PCI_CONFIG_CS3_BASE_ADR 0x01c +#define PCI_CONFIG_INT_REG_MM_ADR 0x020 +#define PCI_CONFIG_INT_REG_IO_ADR 0x024 +#define PCI_CONFIG_BOARD_VENDOR 0x02c +#define PCI_CONFIG_ROM_ADR 0x030 +#define PCI_CONFIG_INT_PIN_LINE 0x03c + + + + + +#endif + diff --git a/include/asm-sh/overdrive/io.h b/include/asm-sh/overdrive/io.h new file mode 100644 index 0000000..0dba700 --- /dev/null +++ b/include/asm-sh/overdrive/io.h @@ -0,0 +1,39 @@ +/* + * include/asm-sh/io_od.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an STMicroelectronics Overdrive + */ + +#ifndef _ASM_SH_IO_OD_H +#define _ASM_SH_IO_OD_H + +extern unsigned char od_inb(unsigned long port); +extern unsigned short od_inw(unsigned long port); +extern unsigned int od_inl(unsigned long port); + +extern void od_outb(unsigned char value, unsigned long port); +extern void od_outw(unsigned short value, unsigned long port); +extern void od_outl(unsigned int value, unsigned long port); + +extern unsigned char od_inb_p(unsigned long port); +extern unsigned short od_inw_p(unsigned long port); +extern unsigned int od_inl_p(unsigned long port); +extern void od_outb_p(unsigned char value, unsigned long port); +extern void od_outw_p(unsigned short value, unsigned long port); +extern void od_outl_p(unsigned int value, unsigned long port); + +extern void od_insb(unsigned long port, void *addr, unsigned long count); +extern void od_insw(unsigned long port, void *addr, unsigned long count); +extern void od_insl(unsigned long port, void *addr, unsigned long count); +extern void od_outsb(unsigned long port, const void *addr, unsigned long count); +extern void od_outsw(unsigned long port, const void *addr, unsigned long count); +extern void od_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned long od_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_OD_H */ diff --git a/include/asm-sh/overdrive/overdrive.h b/include/asm-sh/overdrive/overdrive.h new file mode 100644 index 0000000..aa62ae6 --- /dev/null +++ b/include/asm-sh/overdrive/overdrive.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2000 David J. Mckay (david.mckay@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + */ + +#include <linux/config.h> + +#ifndef __OVERDRIVE_H__ +#define __OVERDRIVE_H__ + +#define OVERDRIVE_INT_CT 0xa3a00000 +#define OVERDRIVE_INT_DT 0xa3b00000 + +#define OVERDRIVE_CTRL 0xa3000000 + +/* Shoving all these bits into the same register is not a good idea. + * As soon as I get a spare moment, I'll change the FPGA and put each + * bit in a separate register + */ + +#define VALID_CTRL_BITS 0x1f + +#define ENABLE_RS232_MASK 0x1e +#define DISABLE_RS232_BIT 0x01 + +#define ENABLE_NMI_MASK 0x1d +#define DISABLE_NMI_BIT 0x02 + +#define RESET_PCI_MASK 0x1b +#define ENABLE_PCI_BIT 0x04 + +#define ENABLE_LED_MASK 0x17 +#define DISABLE_LED_BIT 0x08 + +#define RESET_FPGA_MASK 0x0f +#define ENABLE_FPGA_BIT 0x10 + + +#define FPGA_DCLK_ADDRESS 0xA3C00000 + +#define FPGA_DATA 0x01 /* W */ +#define FPGA_CONFDONE 0x02 /* R */ +#define FPGA_NOT_STATUS 0x04 /* R */ +#define FPGA_INITDONE 0x08 /* R */ + +#define FPGA_TIMEOUT 100000 + + +/* Interrupts for the overdrive. Note that these numbers have + * nothing to do with the actual IRQ numbers they appear on, + * this is all programmable. This is simply the position in the + * INT_CT register. + */ + +#define OVERDRIVE_PCI_INTA 0 +#define OVERDRIVE_PCI_INTB 1 +#define OVERDRIVE_PCI_INTC 2 +#define OVERDRIVE_PCI_INTD 3 +#define OVERDRIVE_GALILEO_INT 4 +#define OVERDRIVE_GALILEO_LOCAL_INT 5 +#define OVERDRIVE_AUDIO_INT 6 +#define OVERDRIVE_KEYBOARD_INT 7 + +/* Which Linux IRQ should we assign to each interrupt source? */ +#define OVERDRIVE_PCI_IRQ1 2 +#ifdef CONFIG_HACKED_NE2K +#define OVERDRIVE_PCI_IRQ2 7 +#else +#define OVERDRIVE_PCI_IRQ2 2 +#undef OVERDRIVE_PCI_INTB +#define OVERDRIVE_PCI_INTB OVERDRIVE_PCI_INTA + +#endif + +/* Put the ESS solo audio chip on IRQ 4 */ +#define OVERDRIVE_ESS_IRQ 4 + +/* Where the memory behind the PCI bus appears */ +#define PCI_DRAM_BASE 0xb7000000 +#define PCI_DRAM_SIZE (16*1024*1024) +#define PCI_DRAM_FINISH (PCI_DRAM_BASE+PCI_DRAM_SIZE-1) + +/* Where the IO region appears in the memory */ +#define PCI_GTIO_BASE 0xb8000000 + +#endif diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h new file mode 100644 index 0000000..4c6d129 --- /dev/null +++ b/include/asm-sh/page.h @@ -0,0 +1,144 @@ +#ifndef __ASM_SH_PAGE_H +#define __ASM_SH_PAGE_H + +/* + * Copyright (C) 1999 Niibe Yutaka + */ + +/* + [ P0/U0 (virtual) ] 0x00000000 <------ User space + [ P1 (fixed) cached ] 0x80000000 <------ Kernel space + [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access + [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area + [ P4 control ] 0xE0000000 + */ + +#include <linux/config.h> + +/* PAGE_SHIFT determines the page size */ +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define PAGE_MASK (~(PAGE_SIZE-1)) +#define PTE_MASK PAGE_MASK + +#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) +#define HPAGE_SHIFT 16 +#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) +#define HPAGE_SHIFT 20 +#endif + +#ifdef CONFIG_HUGETLB_PAGE +#define HPAGE_SIZE (1UL << HPAGE_SHIFT) +#define HPAGE_MASK (~(HPAGE_SIZE-1)) +#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT) +#endif + +#ifdef __KERNEL__ +#ifndef __ASSEMBLY__ + +extern void (*clear_page)(void *to); +extern void (*copy_page)(void *to, void *from); + +extern void clear_page_slow(void *to); +extern void copy_page_slow(void *to, void *from); + +#if defined(CONFIG_SH7705_CACHE_32KB) && defined(CONFIG_MMU) +struct page; +extern void clear_user_page(void *to, unsigned long address, struct page *pg); +extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); +extern void __clear_user_page(void *to, void *orig_to); +extern void __copy_user_page(void *to, void *from, void *orig_to); +#elif defined(CONFIG_CPU_SH2) || defined(CONFIG_CPU_SH3) || !defined(CONFIG_MMU) +#define clear_user_page(page, vaddr, pg) clear_page(page) +#define copy_user_page(to, from, vaddr, pg) copy_page(to, from) +#elif defined(CONFIG_CPU_SH4) +struct page; +extern void clear_user_page(void *to, unsigned long address, struct page *pg); +extern void copy_user_page(void *to, void *from, unsigned long address, struct page *pg); +extern void __clear_user_page(void *to, void *orig_to); +extern void __copy_user_page(void *to, void *from, void *orig_to); +#endif + +/* + * These are used to make use of C type-checking.. + */ +typedef struct { unsigned long pte; } pte_t; +typedef struct { unsigned long pmd; } pmd_t; +typedef struct { unsigned long pgd; } pgd_t; +typedef struct { unsigned long pgprot; } pgprot_t; + +#define pte_val(x) ((x).pte) +#define pmd_val(x) ((x).pmd) +#define pgd_val(x) ((x).pgd) +#define pgprot_val(x) ((x).pgprot) + +#define __pte(x) ((pte_t) { (x) } ) +#define __pmd(x) ((pmd_t) { (x) } ) +#define __pgd(x) ((pgd_t) { (x) } ) +#define __pgprot(x) ((pgprot_t) { (x) } ) + +#endif /* !__ASSEMBLY__ */ + +/* to align the pointer to the (next) page boundary */ +#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) + +/* + * IF YOU CHANGE THIS, PLEASE ALSO CHANGE + * + * arch/sh/kernel/vmlinux.lds.S + * + * which has the same constant encoded.. + */ + +#define __MEMORY_START CONFIG_MEMORY_START +#define __MEMORY_SIZE CONFIG_MEMORY_SIZE +#ifdef CONFIG_DISCONTIGMEM +/* Just for HP690, for now.. */ +#define __MEMORY_START_2ND (__MEMORY_START+0x02000000) +#define __MEMORY_SIZE_2ND 0x001000000 /* 16MB */ +#endif + +#define PAGE_OFFSET (0x80000000UL) +#define __pa(x) ((unsigned long)(x)-PAGE_OFFSET) +#define __va(x) ((void *)((unsigned long)(x)+PAGE_OFFSET)) + +#define MAP_NR(addr) (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT) + +#ifndef CONFIG_DISCONTIGMEM +#define phys_to_page(phys) (mem_map + (((phys)-__MEMORY_START) >> PAGE_SHIFT)) +#define page_to_phys(page) (((page - mem_map) << PAGE_SHIFT) + __MEMORY_START) +#endif + +/* PFN start number, because of __MEMORY_START */ +#define PFN_START (__MEMORY_START >> PAGE_SHIFT) + +#define pfn_to_page(pfn) (mem_map + (pfn) - PFN_START) +#define page_to_pfn(page) ((unsigned long)((page) - mem_map) + PFN_START) +#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT) +#define pfn_valid(pfn) (((pfn) - PFN_START) < max_mapnr) +#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) + +#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ + VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) + +#ifndef __ASSEMBLY__ + +/* Pure 2^n version of get_order */ +static __inline__ int get_order(unsigned long size) +{ + int order; + + size = (size-1) >> (PAGE_SHIFT-1); + order = -1; + do { + size >>= 1; + order++; + } while (size); + return order; +} + +#endif + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_PAGE_H */ diff --git a/include/asm-sh/param.h b/include/asm-sh/param.h new file mode 100644 index 0000000..ce13064 --- /dev/null +++ b/include/asm-sh/param.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SH_PARAM_H +#define __ASM_SH_PARAM_H + +#ifdef __KERNEL__ +# ifdef CONFIG_SH_WDT +# define HZ 1000 /* Needed for high-res WOVF */ +# else +# define HZ 100 +# endif +# define USER_HZ 100 /* User interfaces are in "ticks" */ +# define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ +#endif + +#ifndef HZ +#define HZ 100 +#endif + +#define EXEC_PAGESIZE 4096 + +#ifndef NOGROUP +#define NOGROUP (-1) +#endif + +#define MAXHOSTNAMELEN 64 /* max length of hostname */ + +#endif /* __ASM_SH_PARAM_H */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h new file mode 100644 index 0000000..9c3b63d --- /dev/null +++ b/include/asm-sh/pci.h @@ -0,0 +1,120 @@ +#ifndef __ASM_SH_PCI_H +#define __ASM_SH_PCI_H + +#ifdef __KERNEL__ + +#include <linux/dma-mapping.h> + +/* Can be used to override the logic in pci_scan_bus for skipping + already-configured bus numbers - to be used for buggy BIOSes + or architectures with incomplete PCI setup by the loader */ + +#define pcibios_assign_all_busses() 1 +#define pcibios_scan_all_fns(a, b) 0 + +/* + * A board can define one or more PCI channels that represent built-in (or + * external) PCI controllers. + */ +struct pci_channel { + struct pci_ops *pci_ops; + struct resource *io_resource; + struct resource *mem_resource; + int first_devfn; + int last_devfn; +}; + +/* + * Each board initializes this array and terminates it with a NULL entry. + */ +extern struct pci_channel board_pci_channels[]; + +#define PCIBIOS_MIN_IO board_pci_channels->io_resource->start +#define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start + +struct pci_dev; + +extern void pcibios_set_master(struct pci_dev *dev); + +static inline void pcibios_penalize_isa_irq(int irq) +{ + /* We don't do dynamic PCI IRQ allocation */ +} + +/* Dynamic DMA mapping stuff. + * SuperH has everything mapped statically like x86. + */ + +/* The PCI address space does equal the physical memory + * address space. The networking and block device layers use + * this boolean for bounce buffer decisions. + */ +#define PCI_DMA_BUS_IS_PHYS (1) + +#include <linux/types.h> +#include <linux/slab.h> +#include <asm/scatterlist.h> +#include <linux/string.h> +#include <asm/io.h> + +/* pci_unmap_{single,page} being a nop depends upon the + * configuration. + */ +#ifdef CONFIG_SH_PCIDMA_NONCOHERENT +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \ + dma_addr_t ADDR_NAME; +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \ + __u32 LEN_NAME; +#define pci_unmap_addr(PTR, ADDR_NAME) \ + ((PTR)->ADDR_NAME) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \ + (((PTR)->ADDR_NAME) = (VAL)) +#define pci_unmap_len(PTR, LEN_NAME) \ + ((PTR)->LEN_NAME) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \ + (((PTR)->LEN_NAME) = (VAL)) +#else +#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) +#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) +#define pci_unmap_addr(PTR, ADDR_NAME) (0) +#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0) +#define pci_unmap_len(PTR, LEN_NAME) (0) +#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0) +#endif + +/* Not supporting more than 32-bit PCI bus addresses now, but + * must satisfy references to this function. Change if needed. + */ +#define pci_dac_dma_supported(pci_dev, mask) (0) + +/* These macros should be used after a pci_map_sg call has been done + * to get bus addresses of each of the SG entries and their lengths. + * You should only work with the number of sg entries pci_map_sg + * returns, or alternatively stop on the first sg_dma_len(sg) which + * is 0. + */ +#define sg_dma_address(sg) (virt_to_bus((sg)->dma_address)) +#define sg_dma_len(sg) ((sg)->length) + +/* Board-specific fixup routines. */ +extern void pcibios_fixup(void); +extern void pcibios_fixup_irqs(void); + +#ifdef CONFIG_PCI_AUTO +extern int pciauto_assign_resources(int busno, struct pci_channel *hose); +#endif + +static inline void pcibios_add_platform_entries(struct pci_dev *dev) +{ +} + +#endif /* __KERNEL__ */ + +/* generic pci stuff */ +#include <asm-generic/pci.h> + +/* generic DMA-mapping stuff */ +#include <asm-generic/pci-dma-compat.h> + +#endif /* __ASM_SH_PCI_H */ + diff --git a/include/asm-sh/percpu.h b/include/asm-sh/percpu.h new file mode 100644 index 0000000..4db4b39 --- /dev/null +++ b/include/asm-sh/percpu.h @@ -0,0 +1,6 @@ +#ifndef __ARCH_SH_PERCPU +#define __ARCH_SH_PERCPU + +#include <asm-generic/percpu.h> + +#endif /* __ARCH_SH_PERCPU */ diff --git a/include/asm-sh/pgalloc.h b/include/asm-sh/pgalloc.h new file mode 100644 index 0000000..f4f233f --- /dev/null +++ b/include/asm-sh/pgalloc.h @@ -0,0 +1,88 @@ +#ifndef __ASM_SH_PGALLOC_H +#define __ASM_SH_PGALLOC_H + +#include <linux/threads.h> +#include <linux/slab.h> +#include <linux/mm.h> + +#define pgd_quicklist ((unsigned long *)0) +#define pmd_quicklist ((unsigned long *)0) +#define pte_quicklist ((unsigned long *)0) +#define pgtable_cache_size 0L + +#define pmd_populate_kernel(mm, pmd, pte) \ + set_pmd(pmd, __pmd(_PAGE_TABLE + __pa(pte))) + +static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd, + struct page *pte) +{ + set_pmd(pmd, __pmd(_PAGE_TABLE + page_to_phys(pte))); +} + +/* + * Allocate and free page tables. + */ +static inline pgd_t *pgd_alloc(struct mm_struct *mm) +{ + unsigned int pgd_size = (USER_PTRS_PER_PGD * sizeof(pgd_t)); + pgd_t *pgd = (pgd_t *)kmalloc(pgd_size, GFP_KERNEL); + + if (pgd) + memset(pgd, 0, pgd_size); + + return pgd; +} + +static inline void pgd_free(pgd_t *pgd) +{ + kfree(pgd); +} + +static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm, + unsigned long address) +{ + pte_t *pte; + + pte = (pte_t *) __get_free_page(GFP_KERNEL | __GFP_REPEAT | __GFP_ZERO); + + return pte; +} + +static inline struct page *pte_alloc_one(struct mm_struct *mm, + unsigned long address) +{ + struct page *pte; + + pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0); + + return pte; +} + +static inline void pte_free_kernel(pte_t *pte) +{ + free_page((unsigned long)pte); +} + +static inline void pte_free(struct page *pte) +{ + __free_page(pte); +} + +#define __pte_free_tlb(tlb,pte) tlb_remove_page((tlb),(pte)) + +/* + * allocating and freeing a pmd is trivial: the 1-entry pmd is + * inside the pgd, so has no extra memory associated with it. + */ + +#define pmd_alloc_one(mm, addr) ({ BUG(); ((pmd_t *)2); }) +#define pmd_free(x) do { } while (0) +#define __pmd_free_tlb(tlb,x) do { } while (0) +#define pgd_populate(mm, pmd, pte) BUG() +#define check_pgt_cache() do { } while (0) + +#ifdef CONFIG_CPU_SH4 +#define PG_mapped PG_arch_1 +#endif + +#endif /* __ASM_SH_PGALLOC_H */ diff --git a/include/asm-sh/pgtable-2level.h b/include/asm-sh/pgtable-2level.h new file mode 100644 index 0000000..b0528aa --- /dev/null +++ b/include/asm-sh/pgtable-2level.h @@ -0,0 +1,67 @@ +#ifndef __ASM_SH_PGTABLE_2LEVEL_H +#define __ASM_SH_PGTABLE_2LEVEL_H + +/* + * traditional two-level paging structure: + */ + +#define PGDIR_SHIFT 22 +#define PTRS_PER_PGD 1024 + +/* + * this is two-level, so we don't really have any + * PMD directory physically. + */ +#define PMD_SHIFT 22 +#define PTRS_PER_PMD 1 + +#define PTRS_PER_PTE 1024 + +#ifndef __ASSEMBLY__ +#define pte_ERROR(e) \ + printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) +#define pmd_ERROR(e) \ + printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e)) +#define pgd_ERROR(e) \ + printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) + +/* + * The "pgd_xxx()" functions here are trivial for a folded two-level + * setup: the pgd is never bad, and a pmd always exists (as it's folded + * into the pgd entry) + */ +static inline int pgd_none(pgd_t pgd) { return 0; } +static inline int pgd_bad(pgd_t pgd) { return 0; } +static inline int pgd_present(pgd_t pgd) { return 1; } +static inline void pgd_clear (pgd_t * pgdp) { } + +/* + * Certain architectures need to do special things when PTEs + * within a page table are directly modified. Thus, the following + * hook is made available. + */ +#define set_pte(pteptr, pteval) (*(pteptr) = pteval) +#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval) + +/* + * (pmds are folded into pgds so this doesn't get actually called, + * but the define is needed for a generic inline function.) + */ +#define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval) +#define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval) + +#define pgd_page(pgd) \ +((unsigned long) __va(pgd_val(pgd) & PAGE_MASK)) + +static inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) +{ + return (pmd_t *) dir; +} + +#define pte_pfn(x) ((unsigned long)(((x).pte >> PAGE_SHIFT))) +#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pfn_pmd(pfn, prot) __pmd(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) + +#endif /* !__ASSEMBLY__ */ + +#endif /* __ASM_SH_PGTABLE_2LEVEL_H */ diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h new file mode 100644 index 0000000..8a9689d --- /dev/null +++ b/include/asm-sh/pgtable.h @@ -0,0 +1,306 @@ +#ifndef __ASM_SH_PGTABLE_H +#define __ASM_SH_PGTABLE_H + +#include <asm-generic/4level-fixup.h> + +/* + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2002, 2003, 2004 Paul Mundt + */ + +#include <linux/config.h> +#include <asm/pgtable-2level.h> + +/* + * This file contains the functions and defines necessary to modify and use + * the SuperH page table tree. + */ +#ifndef __ASSEMBLY__ +#include <asm/processor.h> +#include <asm/addrspace.h> +#include <asm/fixmap.h> +#include <linux/threads.h> + +extern pgd_t swapper_pg_dir[PTRS_PER_PGD]; +extern void paging_init(void); + +/* + * Basically we have the same two-level (which is the logical three level + * Linux page table layout folded) page tables as the i386. + */ + +/* + * ZERO_PAGE is a global shared page that is always zero: used + * for zero-mapped memory areas etc.. + */ +extern unsigned long empty_zero_page[1024]; +#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) + +#endif /* !__ASSEMBLY__ */ + +#define PMD_SIZE (1UL << PMD_SHIFT) +#define PMD_MASK (~(PMD_SIZE-1)) +#define PGDIR_SIZE (1UL << PGDIR_SHIFT) +#define PGDIR_MASK (~(PGDIR_SIZE-1)) + +#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) +#define FIRST_USER_PGD_NR 0 + +#define PTE_PHYS_MASK 0x1ffff000 + +#ifndef __ASSEMBLY__ +/* + * First 1MB map is used by fixed purpose. + * Currently only 4-enty (16kB) is used (see arch/sh/mm/cache.c) + */ +#define VMALLOC_START (P3SEG+0x00100000) +#define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) + +#define _PAGE_WT 0x001 /* WT-bit on SH-4, 0 on SH-3 */ +#define _PAGE_HW_SHARED 0x002 /* SH-bit : page is shared among processes */ +#define _PAGE_DIRTY 0x004 /* D-bit : page changed */ +#define _PAGE_CACHABLE 0x008 /* C-bit : cachable */ +#define _PAGE_SZ0 0x010 /* SZ0-bit : Size of page */ +#define _PAGE_RW 0x020 /* PR0-bit : write access allowed */ +#define _PAGE_USER 0x040 /* PR1-bit : user space access allowed */ +#define _PAGE_SZ1 0x080 /* SZ1-bit : Size of page (on SH-4) */ +#define _PAGE_PRESENT 0x100 /* V-bit : page is valid */ +#define _PAGE_PROTNONE 0x200 /* software: if not present */ +#define _PAGE_ACCESSED 0x400 /* software: page referenced */ +#define _PAGE_U0_SHARED 0x800 /* software: page is shared in user space */ + +#define _PAGE_FILE _PAGE_WT /* software: pagecache or swap? */ + +/* software: moves to PTEA.TC (Timing Control) */ +#define _PAGE_PCC_AREA5 0x00000000 /* use BSC registers for area5 */ +#define _PAGE_PCC_AREA6 0x80000000 /* use BSC registers for area6 */ + +/* software: moves to PTEA.SA[2:0] (Space Attributes) */ +#define _PAGE_PCC_IODYN 0x00000001 /* IO space, dynamically sized bus */ +#define _PAGE_PCC_IO8 0x20000000 /* IO space, 8 bit bus */ +#define _PAGE_PCC_IO16 0x20000001 /* IO space, 16 bit bus */ +#define _PAGE_PCC_COM8 0x40000000 /* Common Memory space, 8 bit bus */ +#define _PAGE_PCC_COM16 0x40000001 /* Common Memory space, 16 bit bus */ +#define _PAGE_PCC_ATR8 0x60000000 /* Attribute Memory space, 8 bit bus */ +#define _PAGE_PCC_ATR16 0x60000001 /* Attribute Memory space, 6 bit bus */ + + +/* Mask which drop software flags + * We also drop WT bit since it is used for _PAGE_FILE + * bit in this implementation. + */ +#define _PAGE_CLEAR_FLAGS (_PAGE_WT | _PAGE_PROTNONE | _PAGE_ACCESSED | _PAGE_U0_SHARED) + +#if defined(CONFIG_CPU_SH3) +/* + * MMU on SH-3 has bug on SH-bit: We can't use it if MMUCR.IX=1. + * Work around: Just drop SH-bit. + */ +#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS | _PAGE_HW_SHARED)) +#else +#define _PAGE_FLAGS_HARDWARE_MASK (0x1fffffff & ~(_PAGE_CLEAR_FLAGS)) +#endif + +/* Hardware flags: SZ0=1 (4k-byte) */ +#define _PAGE_FLAGS_HARD _PAGE_SZ0 + +#if defined(CONFIG_HUGETLB_PAGE_SIZE_64K) +#define _PAGE_SZHUGE (_PAGE_SZ1) +#elif defined(CONFIG_HUGETLB_PAGE_SIZE_1MB) +#define _PAGE_SZHUGE (_PAGE_SZ0 | _PAGE_SZ1) +#endif + +#define _PAGE_SHARED _PAGE_U0_SHARED + +#define _PAGE_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY) +#define _KERNPG_TABLE (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY) +#define _PAGE_CHG_MASK (PTE_MASK | _PAGE_ACCESSED | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_SHARED) + +#ifdef CONFIG_MMU +#define PAGE_NONE __pgprot(_PAGE_PROTNONE | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_FLAGS_HARD) +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_CACHABLE |_PAGE_ACCESSED | _PAGE_SHARED | _PAGE_FLAGS_HARD) +#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_CACHABLE | _PAGE_ACCESSED | _PAGE_FLAGS_HARD) +#define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) +#define PAGE_KERNEL_NOCACHE \ + __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) +#define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT | _PAGE_CACHABLE | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_HW_SHARED | _PAGE_FLAGS_HARD) +#define PAGE_KERNEL_PCC(slot, type) \ + __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_FLAGS_HARD | (slot ? _PAGE_PCC_AREA5 : _PAGE_PCC_AREA6) | (type)) +#else /* no mmu */ +#define PAGE_NONE __pgprot(0) +#define PAGE_SHARED __pgprot(0) +#define PAGE_COPY __pgprot(0) +#define PAGE_READONLY __pgprot(0) +#define PAGE_KERNEL __pgprot(0) +#define PAGE_KERNEL_NOCACHE __pgprot(0) +#define PAGE_KERNEL_RO __pgprot(0) +#define PAGE_KERNEL_PCC __pgprot(0) +#endif + +/* + * As i386 and MIPS, SuperH can't do page protection for execute, and + * considers that the same as a read. Also, write permissions imply + * read permissions. This is the closest we can get.. + */ + +#define __P000 PAGE_NONE +#define __P001 PAGE_READONLY +#define __P010 PAGE_COPY +#define __P011 PAGE_COPY +#define __P100 PAGE_READONLY +#define __P101 PAGE_READONLY +#define __P110 PAGE_COPY +#define __P111 PAGE_COPY + +#define __S000 PAGE_NONE +#define __S001 PAGE_READONLY +#define __S010 PAGE_SHARED +#define __S011 PAGE_SHARED +#define __S100 PAGE_READONLY +#define __S101 PAGE_READONLY +#define __S110 PAGE_SHARED +#define __S111 PAGE_SHARED + +#define pte_none(x) (!pte_val(x)) +#define pte_present(x) (pte_val(x) & (_PAGE_PRESENT | _PAGE_PROTNONE)) +#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0) + +#define pmd_none(x) (!pmd_val(x)) +#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT) +#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0) +#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE) + +#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT)) +#define pte_page(x) phys_to_page(pte_val(x)&PTE_PHYS_MASK) + +/* + * The following only work if pte_present() is true. + * Undefined behaviour if not.. + */ +static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; } +static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_USER; } +static inline int pte_dirty(pte_t pte){ return pte_val(pte) & _PAGE_DIRTY; } +static inline int pte_young(pte_t pte){ return pte_val(pte) & _PAGE_ACCESSED; } +static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE; } +static inline int pte_write(pte_t pte){ return pte_val(pte) & _PAGE_RW; } +static inline int pte_not_present(pte_t pte){ return !(pte_val(pte) & _PAGE_PRESENT); } + +static inline pte_t pte_rdprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } +static inline pte_t pte_exprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_USER)); return pte; } +static inline pte_t pte_mkclean(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_DIRTY)); return pte; } +static inline pte_t pte_mkold(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_ACCESSED)); return pte; } +static inline pte_t pte_wrprotect(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) & ~_PAGE_RW)); return pte; } +static inline pte_t pte_mkread(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; } +static inline pte_t pte_mkexec(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_USER)); return pte; } +static inline pte_t pte_mkdirty(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_DIRTY)); return pte; } +static inline pte_t pte_mkyoung(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_ACCESSED)); return pte; } +static inline pte_t pte_mkwrite(pte_t pte) { set_pte(&pte, __pte(pte_val(pte) | _PAGE_RW)); return pte; } + +/* + * Macro and implementation to make a page protection as uncachable. + */ +#define pgprot_noncached pgprot_noncached + +static inline pgprot_t pgprot_noncached(pgprot_t _prot) +{ + unsigned long prot = pgprot_val(_prot); + + prot &= ~_PAGE_CACHABLE; + return __pgprot(prot); +} + +#define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~_PAGE_CACHABLE) + +/* + * Conversion functions: convert a page and protection to a page entry, + * and a page entry and page directory to the page they refer to. + * + * extern pte_t mk_pte(struct page *page, pgprot_t pgprot) + */ +#define mk_pte(page, pgprot) pfn_pte(page_to_pfn(page), (pgprot)) + +static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) +{ set_pte(&pte, __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot))); return pte; } + +#define page_pte(page) page_pte_prot(page, __pgprot(0)) + +#define pmd_page_kernel(pmd) \ +((unsigned long) __va(pmd_val(pmd) & PAGE_MASK)) + +#define pmd_page(pmd) \ + (phys_to_page(pmd_val(pmd))) + +/* to find an entry in a page-table-directory. */ +#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) +#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) + +/* to find an entry in a kernel page-table-directory */ +#define pgd_offset_k(address) pgd_offset(&init_mm, address) + +/* Find an entry in the third-level page table.. */ +#define pte_index(address) \ + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) +#define pte_offset_kernel(dir, address) \ + ((pte_t *) pmd_page_kernel(*(dir)) + pte_index(address)) +#define pte_offset_map(dir, address) pte_offset_kernel(dir, address) +#define pte_offset_map_nested(dir, address) pte_offset_kernel(dir, address) +#define pte_unmap(pte) do { } while (0) +#define pte_unmap_nested(pte) do { } while (0) + +struct vm_area_struct; +extern void update_mmu_cache(struct vm_area_struct * vma, + unsigned long address, pte_t pte); + +/* Encode and de-code a swap entry */ +/* + * NOTE: We should set ZEROs at the position of _PAGE_PRESENT + * and _PAGE_PROTNONE bits + */ +#define __swp_type(x) ((x).val & 0xff) +#define __swp_offset(x) ((x).val >> 10) +#define __swp_entry(type, offset) ((swp_entry_t) { (type) | ((offset) << 10) }) +#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 1 }) +#define __swp_entry_to_pte(x) ((pte_t) { (x).val << 1 }) + +/* + * Encode and decode a nonlinear file mapping entry + */ +#define PTE_FILE_MAX_BITS 29 +#define pte_to_pgoff(pte) (pte_val(pte) >> 1) +#define pgoff_to_pte(off) ((pte_t) { ((off) << 1) | _PAGE_FILE }) + +typedef pte_t *pte_addr_t; + +#endif /* !__ASSEMBLY__ */ + +#define kern_addr_valid(addr) (1) + +#define io_remap_page_range(vma, vaddr, paddr, size, prot) \ + remap_pfn_range(vma, vaddr, (paddr) >> PAGE_SHIFT, size, prot) + +#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \ + remap_pfn_range(vma, vaddr, pfn, size, prot) + +#define MK_IOSPACE_PFN(space, pfn) (pfn) +#define GET_IOSPACE(pfn) 0 +#define GET_PFN(pfn) (pfn) + +/* + * No page table caches to initialise + */ +#define pgtable_cache_init() do { } while (0) + +#ifndef CONFIG_MMU +extern unsigned int kobjsize(const void *objp); +#endif /* !CONFIG_MMU */ + +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB) +#define __HAVE_ARCH_PTEP_GET_AND_CLEAR +extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep); +#endif + +#include <asm-generic/pgtable.h> + +#endif /* __ASM_SH_PAGE_H */ + diff --git a/include/asm-sh/poll.h b/include/asm-sh/poll.h new file mode 100644 index 0000000..52f95b9 --- /dev/null +++ b/include/asm-sh/poll.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SH_POLL_H +#define __ASM_SH_POLL_H + +/* These are specified by iBCS2 */ +#define POLLIN 0x0001 +#define POLLPRI 0x0002 +#define POLLOUT 0x0004 +#define POLLERR 0x0008 +#define POLLHUP 0x0010 +#define POLLNVAL 0x0020 + +/* The rest seem to be more-or-less nonstandard. Check them! */ +#define POLLRDNORM 0x0040 +#define POLLRDBAND 0x0080 +#define POLLWRNORM 0x0100 +#define POLLWRBAND 0x0200 +#define POLLMSG 0x0400 +#define POLLREMOVE 0x1000 + +struct pollfd { + int fd; + short events; + short revents; +}; + +#endif /* __ASM_SH_POLL_H */ diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h new file mode 100644 index 0000000..0a3d2f5 --- /dev/null +++ b/include/asm-sh/posix_types.h @@ -0,0 +1,122 @@ +#ifndef __ASM_SH_POSIX_TYPES_H +#define __ASM_SH_POSIX_TYPES_H + +/* + * This file is generally used by user-level software, so you need to + * be a little careful about namespace pollution etc. Also, we cannot + * assume GCC is being used. + */ + +typedef unsigned long __kernel_ino_t; +typedef unsigned short __kernel_mode_t; +typedef unsigned short __kernel_nlink_t; +typedef long __kernel_off_t; +typedef int __kernel_pid_t; +typedef unsigned short __kernel_ipc_pid_t; +typedef unsigned short __kernel_uid_t; +typedef unsigned short __kernel_gid_t; +typedef unsigned int __kernel_size_t; +typedef int __kernel_ssize_t; +typedef int __kernel_ptrdiff_t; +typedef long __kernel_time_t; +typedef long __kernel_suseconds_t; +typedef long __kernel_clock_t; +typedef int __kernel_timer_t; +typedef int __kernel_clockid_t; +typedef int __kernel_daddr_t; +typedef char * __kernel_caddr_t; +typedef unsigned short __kernel_uid16_t; +typedef unsigned short __kernel_gid16_t; +typedef unsigned int __kernel_uid32_t; +typedef unsigned int __kernel_gid32_t; + +typedef unsigned short __kernel_old_uid_t; +typedef unsigned short __kernel_old_gid_t; +typedef unsigned short __kernel_old_dev_t; + +#ifdef __GNUC__ +typedef long long __kernel_loff_t; +#endif + +typedef struct { +#if defined(__KERNEL__) || defined(__USE_ALL) + int val[2]; +#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ + int __val[2]; +#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ +} __kernel_fsid_t; + +#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) + +#undef __FD_SET +static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); +} + +#undef __FD_CLR +static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); +} + + +#undef __FD_ISSET +static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) +{ + unsigned long __tmp = __fd / __NFDBITS; + unsigned long __rem = __fd % __NFDBITS; + return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; +} + +/* + * This will unroll the loop for the normal constant case (8 ints, + * for a 256-bit fd_set) + */ +#undef __FD_ZERO +static __inline__ void __FD_ZERO(__kernel_fd_set *__p) +{ + unsigned long *__tmp = __p->fds_bits; + int __i; + + if (__builtin_constant_p(__FDSET_LONGS)) { + switch (__FDSET_LONGS) { + case 16: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + __tmp[ 8] = 0; __tmp[ 9] = 0; + __tmp[10] = 0; __tmp[11] = 0; + __tmp[12] = 0; __tmp[13] = 0; + __tmp[14] = 0; __tmp[15] = 0; + return; + + case 8: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + __tmp[ 4] = 0; __tmp[ 5] = 0; + __tmp[ 6] = 0; __tmp[ 7] = 0; + return; + + case 4: + __tmp[ 0] = 0; __tmp[ 1] = 0; + __tmp[ 2] = 0; __tmp[ 3] = 0; + return; + } + } + __i = __FDSET_LONGS; + while (__i) { + __i--; + *__tmp = 0; + __tmp++; + } +} + +#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ + +#endif /* __ASM_SH_POSIX_TYPES_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h new file mode 100644 index 0000000..c490479 --- /dev/null +++ b/include/asm-sh/processor.h @@ -0,0 +1,275 @@ +/* + * include/asm-sh/processor.h + * + * Copyright (C) 1999, 2000 Niibe Yutaka + * Copyright (C) 2002, 2003 Paul Mundt + */ + +#ifndef __ASM_SH_PROCESSOR_H +#define __ASM_SH_PROCESSOR_H +#ifdef __KERNEL__ + +#include <asm/page.h> +#include <asm/types.h> +#include <asm/cache.h> +#include <linux/threads.h> +#include <asm/ptrace.h> + +/* + * Default implementation of macro that returns current + * instruction pointer ("program counter"). + */ +#define current_text_addr() ({ void *pc; __asm__("mova 1f, %0\n1:":"=z" (pc)); pc; }) + +/* Core Processor Version Register */ +#define CCN_PVR 0xff000030 +#define CCN_CVR 0xff000040 +#define CCN_PRR 0xff000044 + +/* + * CPU type and hardware bug flags. Kept separately for each CPU. + * + * Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry + * in arch/sh/Kconfig, as well as an entry in arch/sh/kernel/setup.c + * for parsing the subtype in get_cpu_subtype(). + */ +enum cpu_type { + /* SH-2 types */ + CPU_SH7604, + + /* SH-3 types */ + CPU_SH7705, CPU_SH7707, CPU_SH7708, CPU_SH7708S, CPU_SH7708R, + CPU_SH7709, CPU_SH7709A, CPU_SH7729, CPU_SH7300, + + /* SH-4 types */ + CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R, + CPU_SH7760, CPU_ST40RA, CPU_ST40GX1, CPU_SH4_202, CPU_SH4_501, + CPU_SH73180, + + /* Unknown subtype */ + CPU_SH_NONE +}; + +struct sh_cpuinfo { + enum cpu_type type; + char hard_math; + unsigned long loops_per_jiffy; + + unsigned int cpu_clock, master_clock, bus_clock, module_clock; +#ifdef CONFIG_CPU_SUBTYPE_ST40STB1 + unsigned int memory_clock; +#endif + + struct cache_info icache; + struct cache_info dcache; + + unsigned long flags; +}; + +extern struct sh_cpuinfo boot_cpu_data; + +#ifdef CONFIG_SMP +extern struct sh_cpuinfo cpu_data[]; +#define current_cpu_data cpu_data[smp_processor_id()] +#else +#define cpu_data (&boot_cpu_data) +#define current_cpu_data boot_cpu_data +#endif + +/* + * User space process size: 2GB. + * + * Since SH7709 and SH7750 have "area 7", we can't use 0x7c000000--0x7fffffff + */ +#define TASK_SIZE 0x7c000000UL + +/* This decides where the kernel will search for a free chunk of vm + * space during mmap's. + */ +#define TASK_UNMAPPED_BASE (TASK_SIZE / 3) + +/* + * Bit of SR register + * + * FD-bit: + * When it's set, it means the processor doesn't have right to use FPU, + * and it results exception when the floating operation is executed. + * + * IMASK-bit: + * Interrupt level mask + */ +#define SR_FD 0x00008000 +#define SR_DSP 0x00001000 +#define SR_IMASK 0x000000f0 + +/* + * FPU structure and data + */ + +struct sh_fpu_hard_struct { + unsigned long fp_regs[16]; + unsigned long xfp_regs[16]; + unsigned long fpscr; + unsigned long fpul; + + long status; /* software status information */ +}; + +/* Dummy fpu emulator */ +struct sh_fpu_soft_struct { + unsigned long fp_regs[16]; + unsigned long xfp_regs[16]; + unsigned long fpscr; + unsigned long fpul; + + unsigned char lookahead; + unsigned long entry_pc; +}; + +union sh_fpu_union { + struct sh_fpu_hard_struct hard; + struct sh_fpu_soft_struct soft; +}; + +/* + * Processor flags + */ + +#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */ +#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */ +#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */ +#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */ +#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */ + +struct thread_struct { + unsigned long sp; + unsigned long pc; + + unsigned long trap_no, error_code; + unsigned long address; + /* Hardware debugging registers may come here */ + unsigned long ubc_pc; + + /* floating point info */ + union sh_fpu_union fpu; +}; + +/* Count of active tasks with UBC settings */ +extern int ubc_usercnt; + +#define INIT_THREAD { \ + sizeof(init_stack) + (long) &init_stack, /* sp */ \ + 0, /* pc */ \ + 0, 0, \ + 0, \ + 0, \ + {{{0,}},} /* fpu state */ \ +} + +/* + * Do necessary setup to start up a newly executed thread. + */ +#define start_thread(regs, new_pc, new_sp) \ + set_fs(USER_DS); \ + regs->pr = 0; \ + regs->sr = SR_FD; /* User mode. */ \ + regs->pc = new_pc; \ + regs->regs[15] = new_sp + +/* Forward declaration, a strange C thing */ +struct task_struct; +struct mm_struct; + +/* Free all resources held by a thread. */ +extern void release_thread(struct task_struct *); + +/* Prepare to copy thread state - unlazy all lazy status */ +#define prepare_to_copy(tsk) do { } while (0) + +/* + * create a kernel thread without removing it from tasklists + */ +extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags); + +/* Copy and release all segment info associated with a VM */ +#define copy_segments(p, mm) do { } while(0) +#define release_segments(mm) do { } while(0) + +/* + * FPU lazy state save handling. + */ + +static __inline__ void disable_fpu(void) +{ + unsigned long __dummy; + + /* Set FD flag in SR */ + __asm__ __volatile__("stc sr, %0\n\t" + "or %1, %0\n\t" + "ldc %0, sr" + : "=&r" (__dummy) + : "r" (SR_FD)); +} + +static __inline__ void enable_fpu(void) +{ + unsigned long __dummy; + + /* Clear out FD flag in SR */ + __asm__ __volatile__("stc sr, %0\n\t" + "and %1, %0\n\t" + "ldc %0, sr" + : "=&r" (__dummy) + : "r" (~SR_FD)); +} + +static __inline__ void release_fpu(struct pt_regs *regs) +{ + regs->sr |= SR_FD; +} + +static __inline__ void grab_fpu(struct pt_regs *regs) +{ + regs->sr &= ~SR_FD; +} + +#ifdef CONFIG_CPU_SH4 +extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs); +#else +#define save_fpu(tsk) do { } while (0) +#endif + +#define unlazy_fpu(tsk, regs) do { \ + if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ + save_fpu(tsk, regs); \ + } \ +} while (0) + +#define clear_fpu(tsk, regs) do { \ + if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \ + clear_tsk_thread_flag(tsk, TIF_USEDFPU); \ + release_fpu(regs); \ + } \ +} while (0) + +/* Double presision, NANS as NANS, rounding to nearest, no exceptions */ +#define FPSCR_INIT 0x00080000 + +#define FPSCR_CAUSE_MASK 0x0001f000 /* Cause bits */ +#define FPSCR_FLAG_MASK 0x0000007c /* Flag bits */ + +/* + * Return saved PC of a blocked thread. + */ +#define thread_saved_pc(tsk) (tsk->thread.pc) + +extern unsigned long get_wchan(struct task_struct *p); + +#define KSTK_EIP(tsk) ((tsk)->thread.pc) +#define KSTK_ESP(tsk) ((tsk)->thread.sp) + +#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory") +#define cpu_relax() do { } while (0) + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_PROCESSOR_H */ diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h new file mode 100644 index 0000000..0f75e16 --- /dev/null +++ b/include/asm-sh/ptrace.h @@ -0,0 +1,104 @@ +#ifndef __ASM_SH_PTRACE_H +#define __ASM_SH_PTRACE_H + +#include <asm/ubc.h> + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka + * + */ + +/* + * GCC defines register number like this: + * ----------------------------- + * 0 - 15 are integer registers + * 17 - 22 are control/special registers + * 24 - 39 fp registers + * 40 - 47 xd registers + * 48 - fpscr register + * ----------------------------- + * + * We follows above, except: + * 16 --- program counter (PC) + * 22 --- syscall # + * 23 --- floating point communication register + */ +#define REG_REG0 0 +#define REG_REG15 15 + +#define REG_PC 16 + +#define REG_PR 17 +#define REG_SR 18 +#define REG_GBR 19 +#define REG_MACH 20 +#define REG_MACL 21 + +#define REG_SYSCALL 22 + +#define REG_FPREG0 23 +#define REG_FPREG15 38 +#define REG_XFREG0 39 +#define REG_XFREG15 54 + +#define REG_FPSCR 55 +#define REG_FPUL 56 + +/* options set using PTRACE_SETOPTIONS */ +#define PTRACE_O_TRACESYSGOOD 0x00000001 + +/* + * This struct defines the way the registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_regs { + unsigned long regs[16]; + unsigned long pc; + unsigned long pr; + unsigned long sr; + unsigned long gbr; + unsigned long mach; + unsigned long macl; + long tra; +}; + +/* + * This struct defines the way the DSP registers are stored on the + * kernel stack during a system call or other kernel entry. + */ +struct pt_dspregs { + unsigned long a1; + unsigned long a0g; + unsigned long a1g; + unsigned long m0; + unsigned long m1; + unsigned long a0; + unsigned long x0; + unsigned long x1; + unsigned long y0; + unsigned long y1; + unsigned long dsr; + unsigned long rs; + unsigned long re; + unsigned long mod; +}; + +#define PTRACE_GETDSPREGS 55 +#define PTRACE_SETDSPREGS 56 + +#ifdef __KERNEL__ +#define user_mode(regs) (((regs)->sr & 0x40000000)==0) +#define instruction_pointer(regs) ((regs)->pc) +extern void show_regs(struct pt_regs *); + +static inline unsigned long profile_pc(struct pt_regs *regs) +{ + unsigned long pc = instruction_pointer(regs); + + if (pc >= 0xa0000000UL && pc < 0xc0000000UL) + pc -= 0x20000000; + return pc; +} +#endif + +#endif /* __ASM_SH_PTRACE_H */ diff --git a/include/asm-sh/resource.h b/include/asm-sh/resource.h new file mode 100644 index 0000000..9c2499a --- /dev/null +++ b/include/asm-sh/resource.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_RESOURCE_H +#define __ASM_SH_RESOURCE_H + +#include <asm-generic/resource.h> + +#endif /* __ASM_SH_RESOURCE_H */ diff --git a/include/asm-sh/rtc.h b/include/asm-sh/rtc.h new file mode 100644 index 0000000..cea9cdf --- /dev/null +++ b/include/asm-sh/rtc.h @@ -0,0 +1,29 @@ +#ifndef _ASM_RTC_H +#define _ASM_RTC_H +#ifdef __KERNEL__ + +#include <asm/machvec.h> +#include <asm/cpu/rtc.h> + +extern void sh_rtc_gettimeofday(struct timespec *ts); +extern int sh_rtc_settimeofday(const time_t secs); +extern void (*board_time_init)(void); +extern void (*rtc_get_time)(struct timespec *); +extern int (*rtc_set_time)(const time_t); + +/* RCR1 Bits */ +#define RCR1_CF 0x80 /* Carry Flag */ +#define RCR1_CIE 0x10 /* Carry Interrupt Enable */ +#define RCR1_AIE 0x08 /* Alarm Interrupt Enable */ +#define RCR1_AF 0x01 /* Alarm Flag */ + +/* RCR2 Bits */ +#define RCR2_PEF 0x80 /* PEriodic interrupt Flag */ +#define RCR2_PESMASK 0x70 /* Periodic interrupt Set */ +#define RCR2_RTCEN 0x08 /* ENable RTC */ +#define RCR2_ADJ 0x04 /* ADJustment (30-second) */ +#define RCR2_RESET 0x02 /* Reset bit */ +#define RCR2_START 0x01 /* Start bit */ + +#endif /* __KERNEL__ */ +#endif /* _ASM_RTC_H */ diff --git a/include/asm-sh/rts7751r2d/ide.h b/include/asm-sh/rts7751r2d/ide.h new file mode 100644 index 0000000..416f96b --- /dev/null +++ b/include/asm-sh/rts7751r2d/ide.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_RTS7751R2D_IDE_H +#define __ASM_SH_RTS7751R2D_IDE_H + +/* Nothing to see here.. */ +#include <asm/rts7751r2d/rts7751r2d.h> + +#endif /* __ASM_SH_RTS7751R2D_IDE_H */ + diff --git a/include/asm-sh/rts7751r2d/io.h b/include/asm-sh/rts7751r2d/io.h new file mode 100644 index 0000000..2410940 --- /dev/null +++ b/include/asm-sh/rts7751r2d/io.h @@ -0,0 +1,37 @@ +/* + * include/asm-sh/io_rts7751r2d.h + * + * Modified version of io_se.h for the rts7751r2d-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Renesas Technology sales RTS7751R2D + */ + +#ifndef _ASM_SH_IO_RTS7751R2D_H +#define _ASM_SH_IO_RTS7751R2D_H + +extern unsigned char rts7751r2d_inb(unsigned long port); +extern unsigned short rts7751r2d_inw(unsigned long port); +extern unsigned int rts7751r2d_inl(unsigned long port); + +extern void rts7751r2d_outb(unsigned char value, unsigned long port); +extern void rts7751r2d_outw(unsigned short value, unsigned long port); +extern void rts7751r2d_outl(unsigned int value, unsigned long port); + +extern unsigned char rts7751r2d_inb_p(unsigned long port); +extern void rts7751r2d_outb_p(unsigned char value, unsigned long port); + +extern void rts7751r2d_insb(unsigned long port, void *addr, unsigned long count); +extern void rts7751r2d_insw(unsigned long port, void *addr, unsigned long count); +extern void rts7751r2d_insl(unsigned long port, void *addr, unsigned long count); +extern void rts7751r2d_outsb(unsigned long port, const void *addr, unsigned long count); +extern void rts7751r2d_outsw(unsigned long port, const void *addr, unsigned long count); +extern void rts7751r2d_outsl(unsigned long port, const void *addr, unsigned long count); + +extern void *rts7751r2d_ioremap(unsigned long offset, unsigned long size); + +extern unsigned long rts7751r2d_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_RTS7751R2D_H */ diff --git a/include/asm-sh/rts7751r2d/rts7751r2d.h b/include/asm-sh/rts7751r2d/rts7751r2d.h new file mode 100644 index 0000000..4e09ba5 --- /dev/null +++ b/include/asm-sh/rts7751r2d/rts7751r2d.h @@ -0,0 +1,73 @@ +#ifndef __ASM_SH_RENESAS_RTS7751R2D_H +#define __ASM_SH_RENESAS_RTS7751R2D_H + +/* + * linux/include/asm-sh/renesas_rts7751r2d.h + * + * Copyright (C) 2000 Atom Create Engineering Co., Ltd. + * + * Renesas Technology Sales RTS7751R2D support + */ + +/* Box specific addresses. */ + +#define PA_BCR 0xa4000000 /* FPGA */ +#define PA_IRLMON 0xa4000002 /* Interrupt Status control */ +#define PA_CFCTL 0xa4000004 /* CF Timing control */ +#define PA_CFPOW 0xa4000006 /* CF Power control */ +#define PA_DISPCTL 0xa4000008 /* Display Timing control */ +#define PA_SDMPOW 0xa400000a /* SD Power control */ +#define PA_RTCCE 0xa400000c /* RTC(9701) Enable control */ +#define PA_PCICD 0xa400000e /* PCI Extention detect control */ +#define PA_VOYAGERRTS 0xa4000020 /* VOYAGER Reset control */ +#if defined(CONFIG_RTS7751R2D_REV11) +#define PA_AXRST 0xa4000022 /* AX_LAN Reset control */ +#define PA_CFRST 0xa4000024 /* CF Reset control */ +#define PA_ADMRTS 0xa4000026 /* SD Reset control */ +#define PA_EXTRST 0xa4000028 /* Extention Reset control */ +#define PA_CFCDINTCLR 0xa400002a /* CF Insert Interrupt clear */ +#else +#define PA_CFRST 0xa4000022 /* CF Reset control */ +#define PA_ADMRTS 0xa4000024 /* SD Reset control */ +#define PA_EXTRST 0xa4000026 /* Extention Reset control */ +#define PA_CFCDINTCLR 0xa4000028 /* CF Insert Interrupt clear */ +#define PA_KEYCTLCLR 0xa400002a /* Key Interrupt clear */ +#endif +#define PA_POWOFF 0xa4000030 /* Board Power OFF control */ +#define PA_VERREG 0xa4000032 /* FPGA Version Register */ +#define PA_INPORT 0xa4000034 /* KEY Input Port control */ +#define PA_OUTPORT 0xa4000036 /* LED control */ +#define PA_DMPORT 0xa4000038 /* DM270 Output Port control */ + +#define PA_AX88796L 0xaa000400 /* AX88796L Area */ +#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */ +#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */ +#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */ +#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */ +#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */ + +#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */ + +#if defined(CONFIG_RTS7751R2D_REV11) +#define IRQ_PCIETH 0 /* PCI Ethernet IRQ */ +#define IRQ_CFCARD 1 /* CF Card IRQ */ +#define IRQ_CFINST 2 /* CF Card Insert IRQ */ +#define IRQ_PCMCIA 3 /* PCMCIA IRQ */ +#define IRQ_VOYAGER 4 /* VOYAGER IRQ */ +#define IRQ_ONETH 5 /* On board Ethernet IRQ */ +#else +#define IRQ_KEYIN 0 /* Key Input IRQ */ +#define IRQ_PCIETH 1 /* PCI Ethernet IRQ */ +#define IRQ_CFCARD 2 /* CF Card IRQ */ +#define IRQ_CFINST 3 /* CF Card Insert IRQ */ +#define IRQ_PCMCIA 4 /* PCMCIA IRQ */ +#define IRQ_VOYAGER 5 /* VOYAGER IRQ */ +#endif +#define IRQ_RTCALM 6 /* RTC Alarm IRQ */ +#define IRQ_RTCTIME 7 /* RTC Timer IRQ */ +#define IRQ_SDCARD 8 /* SD Card IRQ */ +#define IRQ_PCISLOT1 9 /* PCI Slot #1 IRQ */ +#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */ +#define IRQ_EXTENTION 11 /* EXTn IRQ */ + +#endif /* __ASM_SH_RENESAS_RTS7751R2D */ diff --git a/include/asm-sh/rts7751r2d/voyagergx_reg.h b/include/asm-sh/rts7751r2d/voyagergx_reg.h new file mode 100644 index 0000000..f031b5d --- /dev/null +++ b/include/asm-sh/rts7751r2d/voyagergx_reg.h @@ -0,0 +1,313 @@ +/* -------------------------------------------------------------------- */ +/* voyagergx_reg.h */ +/* -------------------------------------------------------------------- */ +/* This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + + Copyright 2003 (c) Lineo uSolutions,Inc. +*/ +/* -------------------------------------------------------------------- */ + +#ifndef _VOYAGER_GX_REG_H +#define _VOYAGER_GX_REG_H + +#define VOYAGER_BASE 0xb3e00000 +#define VOYAGER_USBH_BASE (0x40000 + VOYAGER_BASE) +#define VOYAGER_UART_BASE (0x30000 + VOYAGER_BASE) +#define VOYAGER_AC97_BASE (0xa0000 + VOYAGER_BASE) + +#define VOYAGER_IRQ_NUM 32 +#define VOYAGER_IRQ_BASE 50 +#define VOYAGER_USBH_IRQ VOYAGER_IRQ_BASE + 6 +#define VOYAGER_8051_IRQ VOYAGER_IRQ_BASE + 10 +#define VOYAGER_UART0_IRQ VOYAGER_IRQ_BASE + 12 +#define VOYAGER_UART1_IRQ VOYAGER_IRQ_BASE + 13 +#define VOYAGER_AC97_IRQ VOYAGER_IRQ_BASE + 17 + +/* ----- MISC controle register ------------------------------ */ +#define MISC_CTRL (0x000004 + VOYAGER_BASE) +#define MISC_CTRL_USBCLK_48 (3 << 28) +#define MISC_CTRL_USBCLK_96 (2 << 28) +#define MISC_CTRL_USBCLK_CRYSTAL (1 << 28) + +/* ----- GPIO[31:0] register --------------------------------- */ +#define GPIO_MUX_LOW (0x000008 + VOYAGER_BASE) +#define GPIO_MUX_LOW_AC97 0x1F000000 +#define GPIO_MUX_LOW_8051 0x0000ffff +#define GPIO_MUX_LOW_PWM (1 << 29) + +/* ----- GPIO[63:32] register --------------------------------- */ +#define GPIO_MUX_HIGH (0x00000C + VOYAGER_BASE) + +/* ----- DRAM controle register ------------------------------- */ +#define DRAM_CTRL (0x000010 + VOYAGER_BASE) +#define DRAM_CTRL_EMBEDDED (1 << 31) +#define DRAM_CTRL_CPU_BURST_1 (0 << 28) +#define DRAM_CTRL_CPU_BURST_2 (1 << 28) +#define DRAM_CTRL_CPU_BURST_4 (2 << 28) +#define DRAM_CTRL_CPU_BURST_8 (3 << 28) +#define DRAM_CTRL_CPU_CAS_LATENCY (1 << 27) +#define DRAM_CTRL_CPU_SIZE_2 (0 << 24) +#define DRAM_CTRL_CPU_SIZE_4 (1 << 24) +#define DRAM_CTRL_CPU_SIZE_64 (4 << 24) +#define DRAM_CTRL_CPU_SIZE_32 (5 << 24) +#define DRAM_CTRL_CPU_SIZE_16 (6 << 24) +#define DRAM_CTRL_CPU_SIZE_8 (7 << 24) +#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 (0 << 22) +#define DRAM_CTRL_CPU_COLUMN_SIZE_512 (2 << 22) +#define DRAM_CTRL_CPU_COLUMN_SIZE_256 (3 << 22) +#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE (1 << 21) +#define DRAM_CTRL_CPU_RESET (1 << 20) +#define DRAM_CTRL_CPU_BANKS (1 << 19) +#define DRAM_CTRL_CPU_WRITE_PRECHARGE (1 << 18) +#define DRAM_CTRL_BLOCK_WRITE (1 << 17) +#define DRAM_CTRL_REFRESH_COMMAND (1 << 16) +#define DRAM_CTRL_SIZE_4 (0 << 13) +#define DRAM_CTRL_SIZE_8 (1 << 13) +#define DRAM_CTRL_SIZE_16 (2 << 13) +#define DRAM_CTRL_SIZE_32 (3 << 13) +#define DRAM_CTRL_SIZE_64 (4 << 13) +#define DRAM_CTRL_SIZE_2 (5 << 13) +#define DRAM_CTRL_COLUMN_SIZE_256 (0 << 11) +#define DRAM_CTRL_COLUMN_SIZE_512 (2 << 11) +#define DRAM_CTRL_COLUMN_SIZE_1024 (3 << 11) +#define DRAM_CTRL_BLOCK_WRITE_TIME (1 << 10) +#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE (1 << 9) +#define DRAM_CTRL_ACTIVE_PRECHARGE (1 << 8) +#define DRAM_CTRL_RESET (1 << 7) +#define DRAM_CTRL_REMAIN_ACTIVE (1 << 6) +#define DRAM_CTRL_BANKS (1 << 1) +#define DRAM_CTRL_WRITE_PRECHARGE (1 << 0) + +/* ----- Arvitration control register -------------------------- */ +#define ARBITRATION_CTRL (0x000014 + VOYAGER_BASE) +#define ARBITRATION_CTRL_CPUMEM (1 << 29) +#define ARBITRATION_CTRL_INTMEM (1 << 28) +#define ARBITRATION_CTRL_USB_OFF (0 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_1 (1 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_2 (2 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_3 (3 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_4 (4 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_5 (5 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_6 (6 << 24) +#define ARBITRATION_CTRL_USB_PRIORITY_7 (7 << 24) +#define ARBITRATION_CTRL_PANEL_OFF (0 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_1 (1 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_2 (2 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_3 (3 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_4 (4 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_5 (5 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_6 (6 << 20) +#define ARBITRATION_CTRL_PANEL_PRIORITY_7 (7 << 20) +#define ARBITRATION_CTRL_ZVPORT_OFF (0 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_1 (1 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_2 (2 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_3 (3 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_4 (4 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_5 (5 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_6 (6 << 16) +#define ARBITRATION_CTRL_ZVPORTL_PRIORITY_7 (7 << 16) +#define ARBITRATION_CTRL_CMD_INTPR_OFF (0 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 (1 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_2 (2 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_3 (3 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_4 (4 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_5 (5 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_6 (6 << 12) +#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_7 (7 << 12) +#define ARBITRATION_CTRL_DMA_OFF (0 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_1 (1 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_2 (2 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_3 (3 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_4 (4 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_5 (5 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_6 (6 << 8) +#define ARBITRATION_CTRL_DMA_PRIORITY_7 (7 << 8) +#define ARBITRATION_CTRL_VIDEO_OFF (0 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_1 (1 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_2 (2 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_3 (3 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_4 (4 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_5 (5 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_6 (6 << 4) +#define ARBITRATION_CTRL_VIDEO_PRIORITY_7 (7 << 4) +#define ARBITRATION_CTRL_CRT_OFF (0 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_1 (1 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_2 (2 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_3 (3 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_4 (4 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_5 (5 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_6 (6 << 0) +#define ARBITRATION_CTRL_CRT_PRIORITY_7 (7 << 0) + +/* ----- Command list status register -------------------------- */ +#define CMD_INTPR_STATUS (0x000024 + VOYAGER_BASE) + +/* ----- Interrupt status register ----------------------------- */ +#define INT_STATUS (0x00002c + VOYAGER_BASE) +#define INT_STATUS_UH (1 << 6) +#define INT_STATUS_MC (1 << 10) +#define INT_STATUS_U0 (1 << 12) +#define INT_STATUS_U1 (1 << 13) +#define INT_STATUS_AC (1 << 17) + +/* ----- Interrupt mask register ------------------------------ */ +#define VOYAGER_INT_MASK (0x000030 + VOYAGER_BASE) +#define VOYAGER_INT_MASK_AC (1 << 17) + +/* ----- Current Gate register ---------------------------------*/ +#define CURRENT_GATE (0x000038 + VOYAGER_BASE) + +/* ----- Power mode 0 gate register --------------------------- */ +#define POWER_MODE0_GATE (0x000040 + VOYAGER_BASE) +#define POWER_MODE0_GATE_G (1 << 6) +#define POWER_MODE0_GATE_U0 (1 << 7) +#define POWER_MODE0_GATE_U1 (1 << 8) +#define POWER_MODE0_GATE_UH (1 << 11) +#define POWER_MODE0_GATE_AC (1 << 18) + +/* ----- Power mode 1 gate register --------------------------- */ +#define POWER_MODE1_GATE (0x000048 + VOYAGER_BASE) +#define POWER_MODE1_GATE_G (1 << 6) +#define POWER_MODE1_GATE_U0 (1 << 7) +#define POWER_MODE1_GATE_U1 (1 << 8) +#define POWER_MODE1_GATE_UH (1 << 11) +#define POWER_MODE1_GATE_AC (1 << 18) + +/* ----- Power mode 0 clock register -------------------------- */ +#define POWER_MODE0_CLOCK (0x000044 + VOYAGER_BASE) + +/* ----- Power mode 1 clock register -------------------------- */ +#define POWER_MODE1_CLOCK (0x00004C + VOYAGER_BASE) + +/* ----- Power mode controll register ------------------------- */ +#define POWER_MODE_CTRL (0x000054 + VOYAGER_BASE) + +/* ----- Miscellaneous Timing register ------------------------ */ +#define SYSTEM_DRAM_CTRL (0x000068 + VOYAGER_BASE) + +/* ----- PWM register ------------------------------------------*/ +#define PWM_0 (0x010020 + VOYAGER_BASE) +#define PWM_0_HC(x) (((x)&0x0fff)<<20) +#define PWM_0_LC(x) (((x)&0x0fff)<<8 ) +#define PWM_0_CLK_DEV(x) (((x)&0x000f)<<4 ) +#define PWM_0_EN (1<<0) + +/* ----- I2C register ----------------------------------------- */ +#define I2C_BYTECOUNT (0x010040 + VOYAGER_BASE) +#define I2C_CONTROL (0x010041 + VOYAGER_BASE) +#define I2C_STATUS (0x010042 + VOYAGER_BASE) +#define I2C_RESET (0x010042 + VOYAGER_BASE) +#define I2C_SADDRESS (0x010043 + VOYAGER_BASE) +#define I2C_DATA (0x010044 + VOYAGER_BASE) + +/* ----- Controle register bits ----------------------------------------- */ +#define I2C_CONTROL_E (1 << 0) +#define I2C_CONTROL_MODE (1 << 1) +#define I2C_CONTROL_STATUS (1 << 2) +#define I2C_CONTROL_INT (1 << 4) +#define I2C_CONTROL_INTACK (1 << 5) +#define I2C_CONTROL_REPEAT (1 << 6) + +/* ----- Status register bits ----------------------------------------- */ +#define I2C_STATUS_BUSY (1 << 0) +#define I2C_STATUS_ACK (1 << 1) +#define I2C_STATUS_ERROR (1 << 2) +#define I2C_STATUS_COMPLETE (1 << 3) + +/* ----- Reset register ---------------------------------------------- */ +#define I2C_RESET_ERROR (1 << 2) + +/* ----- transmission frequencies ------------------------------------- */ +#define I2C_SADDRESS_SELECT (1 << 0) + +/* ----- Display Controll register ----------------------------------------- */ +#define PANEL_DISPLAY_CTRL (0x080000 + VOYAGER_BASE) +#define PANEL_DISPLAY_CTRL_BIAS (1<<26) +#define PANEL_PAN_CTRL (0x080004 + VOYAGER_BASE) +#define PANEL_COLOR_KEY (0x080008 + VOYAGER_BASE) +#define PANEL_FB_ADDRESS (0x08000C + VOYAGER_BASE) +#define PANEL_FB_WIDTH (0x080010 + VOYAGER_BASE) +#define PANEL_WINDOW_WIDTH (0x080014 + VOYAGER_BASE) +#define PANEL_WINDOW_HEIGHT (0x080018 + VOYAGER_BASE) +#define PANEL_PLANE_TL (0x08001C + VOYAGER_BASE) +#define PANEL_PLANE_BR (0x080020 + VOYAGER_BASE) +#define PANEL_HORIZONTAL_TOTAL (0x080024 + VOYAGER_BASE) +#define PANEL_HORIZONTAL_SYNC (0x080028 + VOYAGER_BASE) +#define PANEL_VERTICAL_TOTAL (0x08002C + VOYAGER_BASE) +#define PANEL_VERTICAL_SYNC (0x080030 + VOYAGER_BASE) +#define PANEL_CURRENT_LINE (0x080034 + VOYAGER_BASE) +#define VIDEO_DISPLAY_CTRL (0x080040 + VOYAGER_BASE) +#define VIDEO_FB_0_ADDRESS (0x080044 + VOYAGER_BASE) +#define VIDEO_FB_WIDTH (0x080048 + VOYAGER_BASE) +#define VIDEO_FB_0_LAST_ADDRESS (0x08004C + VOYAGER_BASE) +#define VIDEO_PLANE_TL (0x080050 + VOYAGER_BASE) +#define VIDEO_PLANE_BR (0x080054 + VOYAGER_BASE) +#define VIDEO_SCALE (0x080058 + VOYAGER_BASE) +#define VIDEO_INITIAL_SCALE (0x08005C + VOYAGER_BASE) +#define VIDEO_YUV_CONSTANTS (0x080060 + VOYAGER_BASE) +#define VIDEO_FB_1_ADDRESS (0x080064 + VOYAGER_BASE) +#define VIDEO_FB_1_LAST_ADDRESS (0x080068 + VOYAGER_BASE) +#define VIDEO_ALPHA_DISPLAY_CTRL (0x080080 + VOYAGER_BASE) +#define VIDEO_ALPHA_FB_ADDRESS (0x080084 + VOYAGER_BASE) +#define VIDEO_ALPHA_FB_WIDTH (0x080088 + VOYAGER_BASE) +#define VIDEO_ALPHA_FB_LAST_ADDRESS (0x08008C + VOYAGER_BASE) +#define VIDEO_ALPHA_PLANE_TL (0x080090 + VOYAGER_BASE) +#define VIDEO_ALPHA_PLANE_BR (0x080094 + VOYAGER_BASE) +#define VIDEO_ALPHA_SCALE (0x080098 + VOYAGER_BASE) +#define VIDEO_ALPHA_INITIAL_SCALE (0x08009C + VOYAGER_BASE) +#define VIDEO_ALPHA_CHROMA_KEY (0x0800A0 + VOYAGER_BASE) +#define PANEL_HWC_ADDRESS (0x0800F0 + VOYAGER_BASE) +#define PANEL_HWC_LOCATION (0x0800F4 + VOYAGER_BASE) +#define PANEL_HWC_COLOR_12 (0x0800F8 + VOYAGER_BASE) +#define PANEL_HWC_COLOR_3 (0x0800FC + VOYAGER_BASE) +#define ALPHA_DISPLAY_CTRL (0x080100 + VOYAGER_BASE) +#define ALPHA_FB_ADDRESS (0x080104 + VOYAGER_BASE) +#define ALPHA_FB_WIDTH (0x080108 + VOYAGER_BASE) +#define ALPHA_PLANE_TL (0x08010C + VOYAGER_BASE) +#define ALPHA_PLANE_BR (0x080110 + VOYAGER_BASE) +#define ALPHA_CHROMA_KEY (0x080114 + VOYAGER_BASE) +#define CRT_DISPLAY_CTRL (0x080200 + VOYAGER_BASE) +#define CRT_FB_ADDRESS (0x080204 + VOYAGER_BASE) +#define CRT_FB_WIDTH (0x080208 + VOYAGER_BASE) +#define CRT_HORIZONTAL_TOTAL (0x08020C + VOYAGER_BASE) +#define CRT_HORIZONTAL_SYNC (0x080210 + VOYAGER_BASE) +#define CRT_VERTICAL_TOTAL (0x080214 + VOYAGER_BASE) +#define CRT_VERTICAL_SYNC (0x080218 + VOYAGER_BASE) +#define CRT_SIGNATURE_ANALYZER (0x08021C + VOYAGER_BASE) +#define CRT_CURRENT_LINE (0x080220 + VOYAGER_BASE) +#define CRT_MONITOR_DETECT (0x080224 + VOYAGER_BASE) +#define CRT_HWC_ADDRESS (0x080230 + VOYAGER_BASE) +#define CRT_HWC_LOCATION (0x080234 + VOYAGER_BASE) +#define CRT_HWC_COLOR_12 (0x080238 + VOYAGER_BASE) +#define CRT_HWC_COLOR_3 (0x08023C + VOYAGER_BASE) +#define CRT_PALETTE_RAM (0x080400 + VOYAGER_BASE) +#define PANEL_PALETTE_RAM (0x080800 + VOYAGER_BASE) +#define VIDEO_PALETTE_RAM (0x080C00 + VOYAGER_BASE) + +/* ----- 8051 Controle register ----------------------------------------- */ +#define VOYAGER_8051_BASE (0x000c0000 + VOYAGER_BASE) +#define VOYAGER_8051_RESET (0x000b0000 + VOYAGER_BASE) +#define VOYAGER_8051_SELECT (0x000b0004 + VOYAGER_BASE) +#define VOYAGER_8051_CPU_INT (0x000b000c + VOYAGER_BASE) + +/* ----- AC97 Controle register ----------------------------------------- */ +#define AC97_TX_SLOT0 (0x00000000 + VOYAGER_AC97_BASE) +#define AC97_CONTROL_STATUS (0x00000080 + VOYAGER_AC97_BASE) +#define AC97C_READ (1 << 19) +#define AC97C_WD_BIT (1 << 2) +#define AC97C_INDEX_MASK 0x7f +/* -------------------------------------------------------------------- */ + +#endif /* _VOYAGER_GX_REG_H */ diff --git a/include/asm-sh/rwsem.h b/include/asm-sh/rwsem.h new file mode 100644 index 0000000..1be4337 --- /dev/null +++ b/include/asm-sh/rwsem.h @@ -0,0 +1,170 @@ +/* + * include/asm-ppc/rwsem.h: R/W semaphores for SH using the stuff + * in lib/rwsem.c. + */ + +#ifndef _ASM_SH_RWSEM_H +#define _ASM_SH_RWSEM_H + +#ifdef __KERNEL__ +#include <linux/list.h> +#include <linux/spinlock.h> +#include <asm/atomic.h> +#include <asm/system.h> + +/* + * the semaphore definition + */ +struct rw_semaphore { + long count; +#define RWSEM_UNLOCKED_VALUE 0x00000000 +#define RWSEM_ACTIVE_BIAS 0x00000001 +#define RWSEM_ACTIVE_MASK 0x0000ffff +#define RWSEM_WAITING_BIAS (-0x00010000) +#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS +#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS) + spinlock_t wait_lock; + struct list_head wait_list; +#if RWSEM_DEBUG + int debug; +#endif +}; + +/* + * initialisation + */ +#if RWSEM_DEBUG +#define __RWSEM_DEBUG_INIT , 0 +#else +#define __RWSEM_DEBUG_INIT /* */ +#endif + +#define __RWSEM_INITIALIZER(name) \ + { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \ + LIST_HEAD_INIT((name).wait_list) \ + __RWSEM_DEBUG_INIT } + +#define DECLARE_RWSEM(name) \ + struct rw_semaphore name = __RWSEM_INITIALIZER(name) + +extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem); +extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem); +extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem); +extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem); + +static inline void init_rwsem(struct rw_semaphore *sem) +{ + sem->count = RWSEM_UNLOCKED_VALUE; + spin_lock_init(&sem->wait_lock); + INIT_LIST_HEAD(&sem->wait_list); +#if RWSEM_DEBUG + sem->debug = 0; +#endif +} + +/* + * lock for reading + */ +static inline void __down_read(struct rw_semaphore *sem) +{ + if (atomic_inc_return((atomic_t *)(&sem->count)) > 0) + smp_wmb(); + else + rwsem_down_read_failed(sem); +} + +static inline int __down_read_trylock(struct rw_semaphore *sem) +{ + int tmp; + + while ((tmp = sem->count) >= 0) { + if (tmp == cmpxchg(&sem->count, tmp, + tmp + RWSEM_ACTIVE_READ_BIAS)) { + smp_wmb(); + return 1; + } + } + return 0; +} + +/* + * lock for writing + */ +static inline void __down_write(struct rw_semaphore *sem) +{ + int tmp; + + tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS, + (atomic_t *)(&sem->count)); + if (tmp == RWSEM_ACTIVE_WRITE_BIAS) + smp_wmb(); + else + rwsem_down_write_failed(sem); +} + +static inline int __down_write_trylock(struct rw_semaphore *sem) +{ + int tmp; + + tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE, + RWSEM_ACTIVE_WRITE_BIAS); + smp_wmb(); + return tmp == RWSEM_UNLOCKED_VALUE; +} + +/* + * unlock after reading + */ +static inline void __up_read(struct rw_semaphore *sem) +{ + int tmp; + + smp_wmb(); + tmp = atomic_dec_return((atomic_t *)(&sem->count)); + if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0) + rwsem_wake(sem); +} + +/* + * unlock after writing + */ +static inline void __up_write(struct rw_semaphore *sem) +{ + smp_wmb(); + if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS, + (atomic_t *)(&sem->count)) < 0) + rwsem_wake(sem); +} + +/* + * implement atomic add functionality + */ +static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem) +{ + atomic_add(delta, (atomic_t *)(&sem->count)); +} + +/* + * downgrade write lock to read lock + */ +static inline void __downgrade_write(struct rw_semaphore *sem) +{ + int tmp; + + smp_wmb(); + tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count)); + if (tmp < 0) + rwsem_downgrade_wake(sem); +} + +/* + * implement exchange and add functionality + */ +static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem) +{ + smp_mb(); + return atomic_add_return(delta, (atomic_t *)(&sem->count)); +} + +#endif /* __KERNEL__ */ +#endif /* _ASM_SH_RWSEM_H */ diff --git a/include/asm-sh/saturn/io.h b/include/asm-sh/saturn/io.h new file mode 100644 index 0000000..f1b9b5d --- /dev/null +++ b/include/asm-sh/saturn/io.h @@ -0,0 +1,19 @@ +/* + * include/asm-sh/saturn/io.h + * + * I/O functions for use on the Sega Saturn. + * + * Copyright (C) 2002 Paul Mundt + * + * Released under the terms of the GNU GPL v2.0. + */ +#ifndef __ASM_SH_SATURN_IO_H +#define __ASM_SH_SATURN_IO_H + +/* arch/sh/boards/saturn/io.c */ +extern unsigned long saturn_isa_port2addr(unsigned long offset); +extern void *saturn_ioremap(unsigned long offset, unsigned long size); +extern void saturn_iounmap(void *addr); + +#endif /* __ASM_SH_SATURN_IO_H */ + diff --git a/include/asm-sh/saturn/smpc.h b/include/asm-sh/saturn/smpc.h new file mode 100644 index 0000000..5de5c12 --- /dev/null +++ b/include/asm-sh/saturn/smpc.h @@ -0,0 +1,34 @@ +/* + * include/asm-sh/saturn/smpc.h + * + * System Manager / Peripheral Control definitions. + * + * Copyright (C) 2002 Paul Mundt + * + * Released under the terms of the GNU GPL v2.0. + */ +#ifndef __ASM_SH_SATURN_SMPC_H +#define __ASM_SH_SATURN_SMPC_H + +#include <asm/io.h> + +#define SMPC_COMMAND 0x2010001f /* SMPC command register */ +#define SMPC_RESULT 0x2010005f /* SMPC result register */ +#define SMPC_STATUS 0x20100063 /* SMPC status register */ + +#define SMPC_CMD_MSHON 0x0001 /* Master SH On */ +#define SMPC_CMD_SSHON 0x0002 /* Slave SH On */ +#define SMPC_CMD_SSHOFF 0x0003 /* Slave SH Off */ +#define SMPC_CMD_SNDON 0x0004 /* Sound On */ +#define SMPC_CMD_SNDOFF 0x0005 /* Sound Off */ +#define SMPC_CMD_CDON 0x0006 /* CD On */ +#define SMPC_CMD_CDOFF 0x0007 /* CD Off */ + +static inline void smpc_barrier(void) +{ + while ((ctrl_inb(SMPC_STATUS) & 0x0001) == 0x0001) + ; +} + +#endif /* __ASM_SH_SATURN_SMPC_H */ + diff --git a/include/asm-sh/scatterlist.h b/include/asm-sh/scatterlist.h new file mode 100644 index 0000000..7b91df1 --- /dev/null +++ b/include/asm-sh/scatterlist.h @@ -0,0 +1,13 @@ +#ifndef __ASM_SH_SCATTERLIST_H +#define __ASM_SH_SCATTERLIST_H + +struct scatterlist { + struct page * page; /* Location for highmem page, if any */ + unsigned int offset;/* for highmem, page offset */ + dma_addr_t dma_address; + unsigned int length; +}; + +#define ISA_DMA_THRESHOLD (0x1fffffff) + +#endif /* !(__ASM_SH_SCATTERLIST_H) */ diff --git a/include/asm-sh/se/io.h b/include/asm-sh/se/io.h new file mode 100644 index 0000000..9eeb86c --- /dev/null +++ b/include/asm-sh/se/io.h @@ -0,0 +1,35 @@ +/* + * include/asm-sh/io_se.h + * + * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Hitachi SolutionEngine + */ + +#ifndef _ASM_SH_IO_SE_H +#define _ASM_SH_IO_SE_H + +extern unsigned char se_inb(unsigned long port); +extern unsigned short se_inw(unsigned long port); +extern unsigned int se_inl(unsigned long port); + +extern void se_outb(unsigned char value, unsigned long port); +extern void se_outw(unsigned short value, unsigned long port); +extern void se_outl(unsigned int value, unsigned long port); + +extern unsigned char se_inb_p(unsigned long port); +extern void se_outb_p(unsigned char value, unsigned long port); + +extern void se_insb(unsigned long port, void *addr, unsigned long count); +extern void se_insw(unsigned long port, void *addr, unsigned long count); +extern void se_insl(unsigned long port, void *addr, unsigned long count); +extern void se_outsb(unsigned long port, const void *addr, unsigned long count); +extern void se_outsw(unsigned long port, const void *addr, unsigned long count); +extern void se_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned long se_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_SE_H */ diff --git a/include/asm-sh/se/se.h b/include/asm-sh/se/se.h new file mode 100644 index 0000000..791c5da --- /dev/null +++ b/include/asm-sh/se/se.h @@ -0,0 +1,77 @@ +#ifndef __ASM_SH_HITACHI_SE_H +#define __ASM_SH_HITACHI_SE_H + +/* + * linux/include/asm-sh/hitachi_se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_83902 0xb0000000 /* DP83902A */ +#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ +#define PA_83902_RST 0xb0080000 /* DP83902A reset port */ + +#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ +#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ +#define PA_LED 0xb0c00000 /* LED */ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define PA_BCR 0xb0e00000 +#else +#define PA_BCR 0xb1400000 /* FPGA */ +#endif + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define IRQ_STNIC 12 +#else +#define IRQ_STNIC 10 +#endif + +#endif /* __ASM_SH_HITACHI_SE_H */ diff --git a/include/asm-sh/se/smc37c93x.h b/include/asm-sh/se/smc37c93x.h new file mode 100644 index 0000000..585da2a --- /dev/null +++ b/include/asm-sh/se/smc37c93x.h @@ -0,0 +1,190 @@ +#ifndef __ASM_SH_SMC37C93X_H +#define __ASM_SH_SMC37C93X_H + +/* + * linux/include/asm-sh/smc37c93x.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * SMSC 37C93x Super IO Chip support + */ + +/* Default base I/O address */ +#define FDC_PRIMARY_BASE 0x3f0 +#define IDE1_PRIMARY_BASE 0x1f0 +#define IDE1_SECONDARY_BASE 0x170 +#define PARPORT_PRIMARY_BASE 0x378 +#define COM1_PRIMARY_BASE 0x2f8 +#define COM2_PRIMARY_BASE 0x3f8 +#define RTC_PRIMARY_BASE 0x070 +#define KBC_PRIMARY_BASE 0x060 +#define AUXIO_PRIMARY_BASE 0x000 /* XXX */ + +/* Logical device number */ +#define LDN_FDC 0 +#define LDN_IDE1 1 +#define LDN_IDE2 2 +#define LDN_PARPORT 3 +#define LDN_COM1 4 +#define LDN_COM2 5 +#define LDN_RTC 6 +#define LDN_KBC 7 +#define LDN_AUXIO 8 + +/* Configuration port and key */ +#define CONFIG_PORT 0x3f0 +#define INDEX_PORT CONFIG_PORT +#define DATA_PORT 0x3f1 +#define CONFIG_ENTER 0x55 +#define CONFIG_EXIT 0xaa + +/* Configuration index */ +#define CURRENT_LDN_INDEX 0x07 +#define POWER_CONTROL_INDEX 0x22 +#define ACTIVATE_INDEX 0x30 +#define IO_BASE_HI_INDEX 0x60 +#define IO_BASE_LO_INDEX 0x61 +#define IRQ_SELECT_INDEX 0x70 +#define DMA_SELECT_INDEX 0x74 + +#define GPIO46_INDEX 0xc6 +#define GPIO47_INDEX 0xc7 + +/* UART stuff. Only for debugging. */ +/* UART Register */ + +#define UART_RBR 0x0 /* Receiver Buffer Register (Read Only) */ +#define UART_THR 0x0 /* Transmitter Holding Register (Write Only) */ +#define UART_IER 0x2 /* Interrupt Enable Register */ +#define UART_IIR 0x4 /* Interrupt Ident Register (Read Only) */ +#define UART_FCR 0x4 /* FIFO Control Register (Write Only) */ +#define UART_LCR 0x6 /* Line Control Register */ +#define UART_MCR 0x8 /* MODEM Control Register */ +#define UART_LSR 0xa /* Line Status Register */ +#define UART_MSR 0xc /* MODEM Status Register */ +#define UART_SCR 0xe /* Scratch Register */ +#define UART_DLL 0x0 /* Divisor Latch (LS) */ +#define UART_DLM 0x2 /* Divisor Latch (MS) */ + +#ifndef __ASSEMBLY__ +typedef struct uart_reg { + volatile __u16 rbr; + volatile __u16 ier; + volatile __u16 iir; + volatile __u16 lcr; + volatile __u16 mcr; + volatile __u16 lsr; + volatile __u16 msr; + volatile __u16 scr; +} uart_reg; +#endif /* ! __ASSEMBLY__ */ + +/* Alias for Write Only Register */ + +#define thr rbr +#define tcr iir + +/* Alias for Divisor Latch Register */ + +#define dll rbr +#define dlm ier +#define fcr iir + +/* Interrupt Enable Register */ + +#define IER_ERDAI 0x0100 /* Enable Received Data Available Interrupt */ +#define IER_ETHREI 0x0200 /* Enable Transmitter Holding Register Empty Interrupt */ +#define IER_ELSI 0x0400 /* Enable Receiver Line Status Interrupt */ +#define IER_EMSI 0x0800 /* Enable MODEM Status Interrupt */ + +/* Interrupt Ident Register */ + +#define IIR_IP 0x0100 /* "0" if Interrupt Pending */ +#define IIR_IIB0 0x0200 /* Interrupt ID Bit 0 */ +#define IIR_IIB1 0x0400 /* Interrupt ID Bit 1 */ +#define IIR_IIB2 0x0800 /* Interrupt ID Bit 2 */ +#define IIR_FIFO 0xc000 /* FIFOs enabled */ + +/* FIFO Control Register */ + +#define FCR_FEN 0x0100 /* FIFO enable */ +#define FCR_RFRES 0x0200 /* Receiver FIFO reset */ +#define FCR_TFRES 0x0400 /* Transmitter FIFO reset */ +#define FCR_DMA 0x0800 /* DMA mode select */ +#define FCR_RTL 0x4000 /* Receiver triger (LSB) */ +#define FCR_RTM 0x8000 /* Receiver triger (MSB) */ + +/* Line Control Register */ + +#define LCR_WLS0 0x0100 /* Word Length Select Bit 0 */ +#define LCR_WLS1 0x0200 /* Word Length Select Bit 1 */ +#define LCR_STB 0x0400 /* Number of Stop Bits */ +#define LCR_PEN 0x0800 /* Parity Enable */ +#define LCR_EPS 0x1000 /* Even Parity Select */ +#define LCR_SP 0x2000 /* Stick Parity */ +#define LCR_SB 0x4000 /* Set Break */ +#define LCR_DLAB 0x8000 /* Divisor Latch Access Bit */ + +/* MODEM Control Register */ + +#define MCR_DTR 0x0100 /* Data Terminal Ready */ +#define MCR_RTS 0x0200 /* Request to Send */ +#define MCR_OUT1 0x0400 /* Out 1 */ +#define MCR_IRQEN 0x0800 /* IRQ Enable */ +#define MCR_LOOP 0x1000 /* Loop */ + +/* Line Status Register */ + +#define LSR_DR 0x0100 /* Data Ready */ +#define LSR_OE 0x0200 /* Overrun Error */ +#define LSR_PE 0x0400 /* Parity Error */ +#define LSR_FE 0x0800 /* Framing Error */ +#define LSR_BI 0x1000 /* Break Interrupt */ +#define LSR_THRE 0x2000 /* Transmitter Holding Register Empty */ +#define LSR_TEMT 0x4000 /* Transmitter Empty */ +#define LSR_FIFOE 0x8000 /* Receiver FIFO error */ + +/* MODEM Status Register */ + +#define MSR_DCTS 0x0100 /* Delta Clear to Send */ +#define MSR_DDSR 0x0200 /* Delta Data Set Ready */ +#define MSR_TERI 0x0400 /* Trailing Edge Ring Indicator */ +#define MSR_DDCD 0x0800 /* Delta Data Carrier Detect */ +#define MSR_CTS 0x1000 /* Clear to Send */ +#define MSR_DSR 0x2000 /* Data Set Ready */ +#define MSR_RI 0x4000 /* Ring Indicator */ +#define MSR_DCD 0x8000 /* Data Carrier Detect */ + +/* Baud Rate Divisor */ + +#define UART_CLK (1843200) /* 1.8432 MHz */ +#define UART_BAUD(x) (UART_CLK / (16 * (x))) + +/* RTC register definition */ +#define RTC_SECONDS 0 +#define RTC_SECONDS_ALARM 1 +#define RTC_MINUTES 2 +#define RTC_MINUTES_ALARM 3 +#define RTC_HOURS 4 +#define RTC_HOURS_ALARM 5 +#define RTC_DAY_OF_WEEK 6 +#define RTC_DAY_OF_MONTH 7 +#define RTC_MONTH 8 +#define RTC_YEAR 9 +#define RTC_FREQ_SELECT 10 +# define RTC_UIP 0x80 +# define RTC_DIV_CTL 0x70 +/* This RTC can work under 32.768KHz clock only. */ +# define RTC_OSC_ENABLE 0x20 +# define RTC_OSC_DISABLE 0x00 +#define RTC_CONTROL 11 +# define RTC_SET 0x80 +# define RTC_PIE 0x40 +# define RTC_AIE 0x20 +# define RTC_UIE 0x10 +# define RTC_SQWE 0x08 +# define RTC_DM_BINARY 0x04 +# define RTC_24H 0x02 +# define RTC_DST_EN 0x01 + +#endif /* __ASM_SH_SMC37C93X_H */ diff --git a/include/asm-sh/se7300/io.h b/include/asm-sh/se7300/io.h new file mode 100644 index 0000000..c6af855 --- /dev/null +++ b/include/asm-sh/se7300/io.h @@ -0,0 +1,29 @@ +/* + * include/asm-sh/se7300/io.h + * + * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> + * IO functions for SH-Mobile(SH7300) SolutionEngine + */ + +#ifndef _ASM_SH_IO_7300SE_H +#define _ASM_SH_IO_7300SE_H + +extern unsigned char sh7300se_inb(unsigned long port); +extern unsigned short sh7300se_inw(unsigned long port); +extern unsigned int sh7300se_inl(unsigned long port); + +extern void sh7300se_outb(unsigned char value, unsigned long port); +extern void sh7300se_outw(unsigned short value, unsigned long port); +extern void sh7300se_outl(unsigned int value, unsigned long port); + +extern unsigned char sh7300se_inb_p(unsigned long port); +extern void sh7300se_outb_p(unsigned char value, unsigned long port); + +extern void sh7300se_insb(unsigned long port, void *addr, unsigned long count); +extern void sh7300se_insw(unsigned long port, void *addr, unsigned long count); +extern void sh7300se_insl(unsigned long port, void *addr, unsigned long count); +extern void sh7300se_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh7300se_outsw(unsigned long port, const void *addr, unsigned long count); +extern void sh7300se_outsl(unsigned long port, const void *addr, unsigned long count); + +#endif /* _ASM_SH_IO_7300SE_H */ diff --git a/include/asm-sh/se7300/se7300.h b/include/asm-sh/se7300/se7300.h new file mode 100644 index 0000000..3ec1ded --- /dev/null +++ b/include/asm-sh/se7300/se7300.h @@ -0,0 +1,61 @@ +#ifndef __ASM_SH_HITACHI_SE7300_H +#define __ASM_SH_HITACHI_SE7300_H + +/* + * linux/include/asm-sh/se/se7300.h + * + * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> + * + * SH-Mobile SolutionEngine 7300 support + */ + +/* Box specific addresses. */ + +/* Area 0 */ +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ +#define PA_FROM 0x00400000 /* Flash ROM */ +#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ +#define PA_SRAM 0x00800000 /* SRAM */ +#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ +/* Area 1 */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +/* Area 2 */ +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +/* Area 3 */ +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 +/* Area 4 */ +#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) +#define PA_LED 0xb0800000 /* LED */ +#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ +#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ +#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ +#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ +/* Area 5 */ +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +/* Area 6 */ +#define PA_LCD1 0xb8000000 +#define PA_LCD2 0xb8800000 + +#endif /* __ASM_SH_HITACHI_SE7300_H */ diff --git a/include/asm-sh/se73180/io.h b/include/asm-sh/se73180/io.h new file mode 100644 index 0000000..c9cb1b9 --- /dev/null +++ b/include/asm-sh/se73180/io.h @@ -0,0 +1,32 @@ +/* + * include/asm-sh/se73180/io.h + * + * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> + * Based on include/asm-sh/se7300/io.h + * + * IO functions for SH-Mobile3(SH73180) SolutionEngine + * + */ + +#ifndef _ASM_SH_IO_73180SE_H +#define _ASM_SH_IO_73180SE_H + +extern unsigned char sh73180se_inb(unsigned long port); +extern unsigned short sh73180se_inw(unsigned long port); +extern unsigned int sh73180se_inl(unsigned long port); + +extern void sh73180se_outb(unsigned char value, unsigned long port); +extern void sh73180se_outw(unsigned short value, unsigned long port); +extern void sh73180se_outl(unsigned int value, unsigned long port); + +extern unsigned char sh73180se_inb_p(unsigned long port); +extern void sh73180se_outb_p(unsigned char value, unsigned long port); + +extern void sh73180se_insb(unsigned long port, void *addr, unsigned long count); +extern void sh73180se_insw(unsigned long port, void *addr, unsigned long count); +extern void sh73180se_insl(unsigned long port, void *addr, unsigned long count); +extern void sh73180se_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh73180se_outsw(unsigned long port, const void *addr, unsigned long count); +extern void sh73180se_outsl(unsigned long port, const void *addr, unsigned long count); + +#endif /* _ASM_SH_IO_73180SE_H */ diff --git a/include/asm-sh/se73180/se73180.h b/include/asm-sh/se73180/se73180.h new file mode 100644 index 0000000..f5b93e3 --- /dev/null +++ b/include/asm-sh/se73180/se73180.h @@ -0,0 +1,62 @@ +#ifndef __ASM_SH_HITACHI_SE73180_H +#define __ASM_SH_HITACHI_SE73180_H + +/* + * include/asm-sh/se/se73180.h + * + * Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp> + * + * SH-Mobile SolutionEngine 73180 support + */ + +/* Box specific addresses. */ + +/* Area 0 */ +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ +#define PA_FROM 0x00400000 /* Flash ROM */ +#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ +#define PA_SRAM 0x00800000 /* SRAM */ +#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ +/* Area 1 */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +/* Area 2 */ +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +/* Area 3 */ +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 +/* Area 4 */ +#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) +#define PA_LED 0xb0C00000 /* LED */ +#define LED_SHIFT 0 +#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ +#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ +#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ +#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ +/* Area 5 */ +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +/* Area 6 */ +#define PA_LCD1 0xb8000000 +#define PA_LCD2 0xb8800000 + +#endif /* __ASM_SH_HITACHI_SE73180_H */ diff --git a/include/asm-sh/se7751/io.h b/include/asm-sh/se7751/io.h new file mode 100644 index 0000000..78d8f57 --- /dev/null +++ b/include/asm-sh/se7751/io.h @@ -0,0 +1,42 @@ +/* + * include/asm-sh/io_7751se.h + * + * Modified version of io_se.h for the 7751se-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for an Hitachi SolutionEngine + */ + +#ifndef _ASM_SH_IO_7751SE_H +#define _ASM_SH_IO_7751SE_H + +extern unsigned char sh7751se_inb(unsigned long port); +extern unsigned short sh7751se_inw(unsigned long port); +extern unsigned int sh7751se_inl(unsigned long port); + +extern void sh7751se_outb(unsigned char value, unsigned long port); +extern void sh7751se_outw(unsigned short value, unsigned long port); +extern void sh7751se_outl(unsigned int value, unsigned long port); + +extern unsigned char sh7751se_inb_p(unsigned long port); +extern void sh7751se_outb_p(unsigned char value, unsigned long port); + +extern void sh7751se_insb(unsigned long port, void *addr, unsigned long count); +extern void sh7751se_insw(unsigned long port, void *addr, unsigned long count); +extern void sh7751se_insl(unsigned long port, void *addr, unsigned long count); +extern void sh7751se_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh7751se_outsw(unsigned long port, const void *addr, unsigned long count); +extern void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned char sh7751se_readb(unsigned long addr); +extern unsigned short sh7751se_readw(unsigned long addr); +extern unsigned int sh7751se_readl(unsigned long addr); +extern void sh7751se_writeb(unsigned char b, unsigned long addr); +extern void sh7751se_writew(unsigned short b, unsigned long addr); +extern void sh7751se_writel(unsigned int b, unsigned long addr); + +extern unsigned long sh7751se_isa_port2addr(unsigned long offset); + +#endif /* _ASM_SH_IO_7751SE_H */ diff --git a/include/asm-sh/se7751/se7751.h b/include/asm-sh/se7751/se7751.h new file mode 100644 index 0000000..738e22b --- /dev/null +++ b/include/asm-sh/se7751/se7751.h @@ -0,0 +1,68 @@ +#ifndef __ASM_SH_HITACHI_7751SE_H +#define __ASM_SH_HITACHI_7751SE_H + +/* + * linux/include/asm-sh/hitachi_7751se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ +#define PA_LED 0xba000000 /* LED */ +#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_MODE (PA_MRSHPC + 4) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#define IRQ_79C973 13 + +#endif /* __ASM_SH_HITACHI_7751SE_H */ diff --git a/include/asm-sh/sections.h b/include/asm-sh/sections.h new file mode 100644 index 0000000..57abd70 --- /dev/null +++ b/include/asm-sh/sections.h @@ -0,0 +1,9 @@ +#ifndef __ASM_SH_SECTIONS_H +#define __ASM_SH_SECTIONS_H + +#include <asm-generic/sections.h> + +extern char _end[]; + +#endif /* __ASM_SH_SECTIONS_H */ + diff --git a/include/asm-sh/segment.h b/include/asm-sh/segment.h new file mode 100644 index 0000000..e417eab --- /dev/null +++ b/include/asm-sh/segment.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_SEGMENT_H +#define __ASM_SH_SEGMENT_H + +/* Only here because we have some old header files that expect it.. */ + +#endif /* __ASM_SH_SEGMENT_H */ diff --git a/include/asm-sh/semaphore-helper.h b/include/asm-sh/semaphore-helper.h new file mode 100644 index 0000000..bd8230c --- /dev/null +++ b/include/asm-sh/semaphore-helper.h @@ -0,0 +1,89 @@ +#ifndef __ASM_SH_SEMAPHORE_HELPER_H +#define __ASM_SH_SEMAPHORE_HELPER_H + +/* + * SMP- and interrupt-safe semaphores helper functions. + * + * (C) Copyright 1996 Linus Torvalds + * (C) Copyright 1999 Andrea Arcangeli + */ + +/* + * These two _must_ execute atomically wrt each other. + * + * This is trivially done with load_locked/store_cond, + * which we have. Let the rest of the losers suck eggs. + */ +static __inline__ void wake_one_more(struct semaphore * sem) +{ + atomic_inc((atomic_t *)&sem->sleepers); +} + +static __inline__ int waking_non_zero(struct semaphore *sem) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&semaphore_wake_lock, flags); + if (sem->sleepers > 0) { + sem->sleepers--; + ret = 1; + } + spin_unlock_irqrestore(&semaphore_wake_lock, flags); + return ret; +} + +/* + * waking_non_zero_interruptible: + * 1 got the lock + * 0 go to sleep + * -EINTR interrupted + * + * We must undo the sem->count down_interruptible() increment while we are + * protected by the spinlock in order to make atomic this atomic_inc() with the + * atomic_read() in wake_one_more(), otherwise we can race. -arca + */ +static __inline__ int waking_non_zero_interruptible(struct semaphore *sem, + struct task_struct *tsk) +{ + unsigned long flags; + int ret = 0; + + spin_lock_irqsave(&semaphore_wake_lock, flags); + if (sem->sleepers > 0) { + sem->sleepers--; + ret = 1; + } else if (signal_pending(tsk)) { + atomic_inc(&sem->count); + ret = -EINTR; + } + spin_unlock_irqrestore(&semaphore_wake_lock, flags); + return ret; +} + +/* + * waking_non_zero_trylock: + * 1 failed to lock + * 0 got the lock + * + * We must undo the sem->count down_trylock() increment while we are + * protected by the spinlock in order to make atomic this atomic_inc() with the + * atomic_read() in wake_one_more(), otherwise we can race. -arca + */ +static __inline__ int waking_non_zero_trylock(struct semaphore *sem) +{ + unsigned long flags; + int ret = 1; + + spin_lock_irqsave(&semaphore_wake_lock, flags); + if (sem->sleepers <= 0) + atomic_inc(&sem->count); + else { + sem->sleepers--; + ret = 0; + } + spin_unlock_irqrestore(&semaphore_wake_lock, flags); + return ret; +} + +#endif /* __ASM_SH_SEMAPHORE_HELPER_H */ diff --git a/include/asm-sh/semaphore.h b/include/asm-sh/semaphore.h new file mode 100644 index 0000000..b923a77 --- /dev/null +++ b/include/asm-sh/semaphore.h @@ -0,0 +1,119 @@ +#ifndef __ASM_SH_SEMAPHORE_H +#define __ASM_SH_SEMAPHORE_H + +#include <linux/linkage.h> + +#ifdef __KERNEL__ +/* + * SMP- and interrupt-safe semaphores. + * + * (C) Copyright 1996 Linus Torvalds + * + * SuperH verison by Niibe Yutaka + * (Currently no asm implementation but generic C code...) + */ + +#include <linux/spinlock.h> +#include <linux/rwsem.h> +#include <linux/wait.h> + +#include <asm/system.h> +#include <asm/atomic.h> + +struct semaphore { + atomic_t count; + int sleepers; + wait_queue_head_t wait; +}; + +#define __SEMAPHORE_INITIALIZER(name, n) \ +{ \ + .count = ATOMIC_INIT(n), \ + .sleepers = 0, \ + .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \ +} + +#define __MUTEX_INITIALIZER(name) \ + __SEMAPHORE_INITIALIZER(name,1) + +#define __DECLARE_SEMAPHORE_GENERIC(name,count) \ + struct semaphore name = __SEMAPHORE_INITIALIZER(name,count) + +#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1) +#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0) + +static inline void sema_init (struct semaphore *sem, int val) +{ +/* + * *sem = (struct semaphore)__SEMAPHORE_INITIALIZER((*sem),val); + * + * i'd rather use the more flexible initialization above, but sadly + * GCC 2.7.2.3 emits a bogus warning. EGCS doesn't. Oh well. + */ + atomic_set(&sem->count, val); + sem->sleepers = 0; + init_waitqueue_head(&sem->wait); +} + +static inline void init_MUTEX (struct semaphore *sem) +{ + sema_init(sem, 1); +} + +static inline void init_MUTEX_LOCKED (struct semaphore *sem) +{ + sema_init(sem, 0); +} + +#if 0 +asmlinkage void __down_failed(void /* special register calling convention */); +asmlinkage int __down_failed_interruptible(void /* params in registers */); +asmlinkage int __down_failed_trylock(void /* params in registers */); +asmlinkage void __up_wakeup(void /* special register calling convention */); +#endif + +asmlinkage void __down(struct semaphore * sem); +asmlinkage int __down_interruptible(struct semaphore * sem); +asmlinkage int __down_trylock(struct semaphore * sem); +asmlinkage void __up(struct semaphore * sem); + +extern spinlock_t semaphore_wake_lock; + +static inline void down(struct semaphore * sem) +{ + might_sleep(); + if (atomic_dec_return(&sem->count) < 0) + __down(sem); +} + +static inline int down_interruptible(struct semaphore * sem) +{ + int ret = 0; + + might_sleep(); + if (atomic_dec_return(&sem->count) < 0) + ret = __down_interruptible(sem); + return ret; +} + +static inline int down_trylock(struct semaphore * sem) +{ + int ret = 0; + + if (atomic_dec_return(&sem->count) < 0) + ret = __down_trylock(sem); + return ret; +} + +/* + * Note! This is subtle. We jump to wake people up only if + * the semaphore was negative (== somebody was waiting on it). + */ +static inline void up(struct semaphore * sem) +{ + if (atomic_inc_return(&sem->count) <= 0) + __up(sem); +} + +#endif +#endif /* __ASM_SH_SEMAPHORE_H */ diff --git a/include/asm-sh/sembuf.h b/include/asm-sh/sembuf.h new file mode 100644 index 0000000..d79f3bd --- /dev/null +++ b/include/asm-sh/sembuf.h @@ -0,0 +1,25 @@ +#ifndef __ASM_SH_SEMBUF_H +#define __ASM_SH_SEMBUF_H + +/* + * The semid64_ds structure for i386 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct semid64_ds { + struct ipc64_perm sem_perm; /* permissions .. see ipc.h */ + __kernel_time_t sem_otime; /* last semop time */ + unsigned long __unused1; + __kernel_time_t sem_ctime; /* last change time */ + unsigned long __unused2; + unsigned long sem_nsems; /* no. of semaphores in array */ + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* __ASM_SH_SEMBUF_H */ diff --git a/include/asm-sh/serial.h b/include/asm-sh/serial.h new file mode 100644 index 0000000..5474dbd --- /dev/null +++ b/include/asm-sh/serial.h @@ -0,0 +1,48 @@ +/* + * include/asm-sh/serial.h + * + * Configuration details for 8250, 16450, 16550, etc. serial ports + */ + +#ifndef _ASM_SERIAL_H +#define _ASM_SERIAL_H + +#include <linux/config.h> +#include <linux/kernel.h> + +#ifdef CONFIG_SH_EC3104 +#include <asm/serial-ec3104.h> +#elif defined (CONFIG_SH_BIGSUR) +#include <asm/serial-bigsur.h> +#else +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) + +#ifdef CONFIG_HD64465 +#include <asm/hd64465.h> + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */ + +#else + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */ + +#endif + +#define SERIAL_PORT_DFNS STD_SERIAL_PORT_DEFNS + +#endif +#endif /* _ASM_SERIAL_H */ diff --git a/include/asm-sh/setup.h b/include/asm-sh/setup.h new file mode 100644 index 0000000..d19de7c --- /dev/null +++ b/include/asm-sh/setup.h @@ -0,0 +1,8 @@ +#ifdef __KERNEL__ +#ifndef _SH_SETUP_H +#define _SH_SETUP_H + +#define COMMAND_LINE_SIZE 256 + +#endif /* _SH_SETUP_H */ +#endif /* __KERNEL__ */ diff --git a/include/asm-sh/sh03/ide.h b/include/asm-sh/sh03/ide.h new file mode 100644 index 0000000..73ee92e --- /dev/null +++ b/include/asm-sh/sh03/ide.h @@ -0,0 +1,7 @@ +#ifndef __ASM_SH_SH03_IDE_H +#define __ASM_SH_SH03_IDE_H + +#define IRQ_CFCARD 8 +#define IRQ_PCMCIA 8 + +#endif /* __ASM_SH_SH03_IDE_H */ diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h new file mode 100644 index 0000000..25792e9 --- /dev/null +++ b/include/asm-sh/sh03/io.h @@ -0,0 +1,46 @@ +/* + * include/asm-sh/sh03/io.h + * + * Copyright 2004 Interface Co.,Ltd. Saito.K + * + * IO functions for an Interface CTP/PCI-SH03 + */ + +#ifndef _ASM_SH_IO_SH03_H +#define _ASM_SH_IO_SH03_H + +#include <linux/time.h> + +#define INTC_IPRD 0xffd00010UL + +#define IRL0_IRQ 2 +#define IRL0_IPR_ADDR INTC_IPRD +#define IRL0_IPR_POS 3 +#define IRL0_PRIORITY 13 + +#define IRL1_IRQ 5 +#define IRL1_IPR_ADDR INTC_IPRD +#define IRL1_IPR_POS 2 +#define IRL1_PRIORITY 10 + +#define IRL2_IRQ 8 +#define IRL2_IPR_ADDR INTC_IPRD +#define IRL2_IPR_POS 1 +#define IRL2_PRIORITY 7 + +#define IRL3_IRQ 11 +#define IRL3_IPR_ADDR INTC_IPRD +#define IRL3_IPR_POS 0 +#define IRL3_PRIORITY 4 + + +extern unsigned long sh03_isa_port2addr(unsigned long offset); + +extern void setup_sh03(void); +extern void init_sh03_IRQ(void); +extern void heartbeat_sh03(void); + +extern void sh03_rtc_gettimeofday(struct timeval *tv); +extern int sh03_rtc_settimeofday(const struct timeval *tv); + +#endif /* _ASM_SH_IO_SH03_H */ diff --git a/include/asm-sh/sh03/sh03.h b/include/asm-sh/sh03/sh03.h new file mode 100644 index 0000000..19c40b8 --- /dev/null +++ b/include/asm-sh/sh03/sh03.h @@ -0,0 +1,18 @@ +#ifndef __ASM_SH_SH03_H +#define __ASM_SH_SH03_H + +/* + * linux/include/asm-sh/sh03/sh03.h + * + * Copyright (C) 2004 Interface Co., Ltd. Saito.K + * + * Interface CTP/PCI-SH03 support + */ + +#define PA_PCI_IO (0xbe240000) /* PCI I/O space */ +#define PA_PCI_MEM (0xbd000000) /* PCI MEM space */ + +#define PCIPAR (0xa4000cf8) /* PCI Config address */ +#define PCIPDR (0xa4000cfc) /* PCI Config data */ + +#endif /* __ASM_SH_SH03_H */ diff --git a/include/asm-sh/sh2000/sh2000.h b/include/asm-sh/sh2000/sh2000.h new file mode 100644 index 0000000..8d54732 --- /dev/null +++ b/include/asm-sh/sh2000/sh2000.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_SH2000_SH2000_H +#define __ASM_SH_SH2000_SH2000_H + +/* arch/sh/boards/sh2000/setup.c */ +extern int setup_sh2000(void); + +#endif /* __ASM_SH_SH2000_SH2000_H */ + diff --git a/include/asm-sh/sh_bios.h b/include/asm-sh/sh_bios.h new file mode 100644 index 0000000..0ca2619 --- /dev/null +++ b/include/asm-sh/sh_bios.h @@ -0,0 +1,19 @@ +#ifndef __ASM_SH_BIOS_H +#define __ASM_SH_BIOS_H + +/* + * Copyright (C) 2000 Greg Banks, Mitch Davis + * C API to interface to the standard LinuxSH BIOS + * usually from within the early stages of kernel boot. + */ + + +extern void sh_bios_console_write(const char *buf, unsigned int len); +extern void sh_bios_char_out(char ch); +extern int sh_bios_in_gdb_mode(void); +extern void sh_bios_gdb_detach(void); + +extern void sh_bios_get_node_addr(unsigned char *node_addr); +extern void sh_bios_shutdown(unsigned int how); + +#endif /* __ASM_SH_BIOS_H */ diff --git a/include/asm-sh/shmbuf.h b/include/asm-sh/shmbuf.h new file mode 100644 index 0000000..b2101f4 --- /dev/null +++ b/include/asm-sh/shmbuf.h @@ -0,0 +1,42 @@ +#ifndef __ASM_SH_SHMBUF_H +#define __ASM_SH_SHMBUF_H + +/* + * The shmid64_ds structure for i386 architecture. + * Note extra padding because this structure is passed back and forth + * between kernel and user space. + * + * Pad space is left for: + * - 64-bit time_t to solve y2038 problem + * - 2 miscellaneous 32-bit values + */ + +struct shmid64_ds { + struct ipc64_perm shm_perm; /* operation perms */ + size_t shm_segsz; /* size of segment (bytes) */ + __kernel_time_t shm_atime; /* last attach time */ + unsigned long __unused1; + __kernel_time_t shm_dtime; /* last detach time */ + unsigned long __unused2; + __kernel_time_t shm_ctime; /* last change time */ + unsigned long __unused3; + __kernel_pid_t shm_cpid; /* pid of creator */ + __kernel_pid_t shm_lpid; /* pid of last operator */ + unsigned long shm_nattch; /* no. of current attaches */ + unsigned long __unused4; + unsigned long __unused5; +}; + +struct shminfo64 { + unsigned long shmmax; + unsigned long shmmin; + unsigned long shmmni; + unsigned long shmseg; + unsigned long shmall; + unsigned long __unused1; + unsigned long __unused2; + unsigned long __unused3; + unsigned long __unused4; +}; + +#endif /* __ASM_SH_SHMBUF_H */ diff --git a/include/asm-sh/shmparam.h b/include/asm-sh/shmparam.h new file mode 100644 index 0000000..0a95604 --- /dev/null +++ b/include/asm-sh/shmparam.h @@ -0,0 +1,8 @@ +#ifndef __ASM_SH_SHMPARAM_H +#define __ASM_SH_SHMPARAM_H +#ifdef __KERNEL__ + +#include <asm/cpu/shmparam.h> + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_SHMPARAM_H */ diff --git a/include/asm-sh/sigcontext.h b/include/asm-sh/sigcontext.h new file mode 100644 index 0000000..eb8effb --- /dev/null +++ b/include/asm-sh/sigcontext.h @@ -0,0 +1,26 @@ +#ifndef __ASM_SH_SIGCONTEXT_H +#define __ASM_SH_SIGCONTEXT_H + +struct sigcontext { + unsigned long oldmask; + + /* CPU registers */ + unsigned long sc_regs[16]; + unsigned long sc_pc; + unsigned long sc_pr; + unsigned long sc_sr; + unsigned long sc_gbr; + unsigned long sc_mach; + unsigned long sc_macl; + +#if defined(__SH4__) || defined(CONFIG_CPU_SH4) + /* FPU registers */ + unsigned long sc_fpregs[16]; + unsigned long sc_xfpregs[16]; + unsigned int sc_fpscr; + unsigned int sc_fpul; + unsigned int sc_ownedfp; +#endif +}; + +#endif /* __ASM_SH_SIGCONTEXT_H */ diff --git a/include/asm-sh/siginfo.h b/include/asm-sh/siginfo.h new file mode 100644 index 0000000..813040e --- /dev/null +++ b/include/asm-sh/siginfo.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_SIGINFO_H +#define __ASM_SH_SIGINFO_H + +#include <asm-generic/siginfo.h> + +#endif /* __ASM_SH_SIGINFO_H */ diff --git a/include/asm-sh/signal.h b/include/asm-sh/signal.h new file mode 100644 index 0000000..0a7ff71 --- /dev/null +++ b/include/asm-sh/signal.h @@ -0,0 +1,185 @@ +#ifndef __ASM_SH_SIGNAL_H +#define __ASM_SH_SIGNAL_H + +#include <linux/types.h> + +/* Avoid too many header ordering problems. */ +struct pt_regs; +struct siginfo; + +#ifdef __KERNEL__ +/* Most things should be clean enough to redefine this at will, if care + is taken to make libc match. */ + +#define _NSIG 64 +#define _NSIG_BPW 32 +#define _NSIG_WORDS (_NSIG / _NSIG_BPW) + +typedef unsigned long old_sigset_t; /* at least 32 bits */ + +typedef struct { + unsigned long sig[_NSIG_WORDS]; +} sigset_t; + +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +#define NSIG 32 +typedef unsigned long sigset_t; + +#endif /* __KERNEL__ */ + +#define SIGHUP 1 +#define SIGINT 2 +#define SIGQUIT 3 +#define SIGILL 4 +#define SIGTRAP 5 +#define SIGABRT 6 +#define SIGIOT 6 +#define SIGBUS 7 +#define SIGFPE 8 +#define SIGKILL 9 +#define SIGUSR1 10 +#define SIGSEGV 11 +#define SIGUSR2 12 +#define SIGPIPE 13 +#define SIGALRM 14 +#define SIGTERM 15 +#define SIGSTKFLT 16 +#define SIGCHLD 17 +#define SIGCONT 18 +#define SIGSTOP 19 +#define SIGTSTP 20 +#define SIGTTIN 21 +#define SIGTTOU 22 +#define SIGURG 23 +#define SIGXCPU 24 +#define SIGXFSZ 25 +#define SIGVTALRM 26 +#define SIGPROF 27 +#define SIGWINCH 28 +#define SIGIO 29 +#define SIGPOLL SIGIO +/* +#define SIGLOST 29 +*/ +#define SIGPWR 30 +#define SIGSYS 31 +#define SIGUNUSED 31 + +/* These should not be considered constants from userland. */ +#define SIGRTMIN 32 +#define SIGRTMAX _NSIG + +/* + * SA_FLAGS values: + * + * SA_ONSTACK indicates that a registered stack_t will be used. + * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the + * SA_RESTART flag to get restarting signals (which were the default long ago) + * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop. + * SA_RESETHAND clears the handler when the signal is delivered. + * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies. + * SA_NODEFER prevents the current signal from being masked in the handler. + * + * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single + * Unix names RESETHAND and NODEFER respectively. + */ +#define SA_NOCLDSTOP 0x00000001 +#define SA_NOCLDWAIT 0x00000002 +#define SA_SIGINFO 0x00000004 +#define SA_ONSTACK 0x08000000 +#define SA_RESTART 0x10000000 +#define SA_NODEFER 0x40000000 +#define SA_RESETHAND 0x80000000 + +#define SA_NOMASK SA_NODEFER +#define SA_ONESHOT SA_RESETHAND +#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */ + +#define SA_RESTORER 0x04000000 + +/* + * sigaltstack controls + */ +#define SS_ONSTACK 1 +#define SS_DISABLE 2 + +#define MINSIGSTKSZ 2048 +#define SIGSTKSZ 8192 + +#ifdef __KERNEL__ + +/* + * These values of sa_flags are used only by the kernel as part of the + * irq handling routines. + * + * SA_INTERRUPT is also used by the irq handling routines. + * SA_SHIRQ is for shared interrupt support on PCI and EISA. + */ +#define SA_PROBE SA_ONESHOT +#define SA_SAMPLE_RANDOM SA_RESTART +#define SA_SHIRQ 0x04000000 +#endif + +#define SIG_BLOCK 0 /* for blocking signals */ +#define SIG_UNBLOCK 1 /* for unblocking signals */ +#define SIG_SETMASK 2 /* for setting the signal mask */ + +/* Type of a signal handler. */ +typedef void (*__sighandler_t)(int); + +#define SIG_DFL ((__sighandler_t)0) /* default signal handling */ +#define SIG_IGN ((__sighandler_t)1) /* ignore signal */ +#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */ + +#ifdef __KERNEL__ +struct old_sigaction { + __sighandler_t sa_handler; + old_sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +struct sigaction { + __sighandler_t sa_handler; + unsigned long sa_flags; + void (*sa_restorer)(void); + sigset_t sa_mask; /* mask last for extensibility */ +}; + +struct k_sigaction { + struct sigaction sa; +}; +#else +/* Here we must cater to libcs that poke about in kernel headers. */ + +struct sigaction { + union { + __sighandler_t _sa_handler; + void (*_sa_sigaction)(int, struct siginfo *, void *); + } _u; + sigset_t sa_mask; + unsigned long sa_flags; + void (*sa_restorer)(void); +}; + +#define sa_handler _u._sa_handler +#define sa_sigaction _u._sa_sigaction + +#endif /* __KERNEL__ */ + +typedef struct sigaltstack { + void *ss_sp; + int ss_flags; + size_t ss_size; +} stack_t; + +#ifdef __KERNEL__ +#include <asm/sigcontext.h> + +#define ptrace_signal_deliver(regs, cookie) do { } while (0) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_SIGNAL_H */ diff --git a/include/asm-sh/smp.h b/include/asm-sh/smp.h new file mode 100644 index 0000000..38b5446 --- /dev/null +++ b/include/asm-sh/smp.h @@ -0,0 +1,48 @@ +/* + * include/asm-sh/smp.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive for + * more details. + */ +#ifndef __ASM_SH_SMP_H +#define __ASM_SH_SMP_H + +#include <linux/config.h> +#include <linux/bitops.h> +#include <linux/cpumask.h> + +#ifdef CONFIG_SMP + +#include <asm/spinlock.h> +#include <asm/atomic.h> +#include <asm/current.h> + +extern cpumask_t cpu_online_map; +extern cpumask_t cpu_possible_map; + +#define cpu_online(cpu) cpu_isset(cpu, cpu_online_map) + +#define smp_processor_id() (current_thread_info()->cpu) + +/* I've no idea what the real meaning of this is */ +#define PROC_CHANGE_PENALTY 20 + +#define NO_PROC_ID (-1) + +struct smp_fn_call_struct { + spinlock_t lock; + atomic_t finished; + void (*fn)(void *); + void *data; +}; + +extern struct smp_fn_call_struct smp_fn_call; + +#define SMP_MSG_RESCHEDULE 0x0001 + +#endif /* CONFIG_SMP */ + +#endif /* __ASM_SH_SMP_H */ diff --git a/include/asm-sh/snapgear/io.h b/include/asm-sh/snapgear/io.h new file mode 100644 index 0000000..bfa97ac --- /dev/null +++ b/include/asm-sh/snapgear/io.h @@ -0,0 +1,92 @@ +/* + * include/asm-sh/snapgear/io.h + * + * Modified version of io_se.h for the snapgear-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for a SnapGear + */ + +#ifndef _ASM_SH_IO_SNAPGEAR_H +#define _ASM_SH_IO_SNAPGEAR_H + +#if defined(CONFIG_CPU_SH4) +/* + * The external interrupt lines, these take up ints 0 - 15 inclusive + * depending on the priority for the interrupt. In fact the priority + * is the interrupt :-) + */ + +#define IRL0_IRQ 2 +#define IRL0_IPR_ADDR INTC_IPRD +#define IRL0_IPR_POS 3 +#define IRL0_PRIORITY 13 + +#define IRL1_IRQ 5 +#define IRL1_IPR_ADDR INTC_IPRD +#define IRL1_IPR_POS 2 +#define IRL1_PRIORITY 10 + +#define IRL2_IRQ 8 +#define IRL2_IPR_ADDR INTC_IPRD +#define IRL2_IPR_POS 1 +#define IRL2_PRIORITY 7 + +#define IRL3_IRQ 11 +#define IRL3_IPR_ADDR INTC_IPRD +#define IRL3_IPR_POS 0 +#define IRL3_PRIORITY 4 +#endif + +extern unsigned char snapgear_inb(unsigned long port); +extern unsigned short snapgear_inw(unsigned long port); +extern unsigned int snapgear_inl(unsigned long port); + +extern void snapgear_outb(unsigned char value, unsigned long port); +extern void snapgear_outw(unsigned short value, unsigned long port); +extern void snapgear_outl(unsigned int value, unsigned long port); + +extern unsigned char snapgear_inb_p(unsigned long port); +extern void snapgear_outb_p(unsigned char value, unsigned long port); + +extern void snapgear_insl(unsigned long port, void *addr, unsigned long count); +extern void snapgear_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned long snapgear_isa_port2addr(unsigned long offset); + +#ifdef CONFIG_SH_SECUREEDGE5410 +/* + * We need to remember what was written to the ioport as some bits + * are shared with other functions and you cannot read back what was + * written :-| + * + * Bit Read Write + * ----------------------------------------------- + * D0 DCD on ttySC1 power + * D1 Reset Switch heatbeat + * D2 ttySC0 CTS (7100) LAN + * D3 - WAN + * D4 ttySC0 DCD (7100) CONSOLE + * D5 - ONLINE + * D6 - VPN + * D7 - DTR on ttySC1 + * D8 - ttySC0 RTS (7100) + * D9 - ttySC0 DTR (7100) + * D10 - RTC SCLK + * D11 RTC DATA RTC DATA + * D12 - RTS RESET + */ + + #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) + extern unsigned short secureedge5410_ioport; + + #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ + (secureedge5410_ioport = \ + ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) + #define SECUREEDGE_READ_IOPORT() \ + ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) +#endif + +#endif /* _ASM_SH_IO_SNAPGEAR_H */ diff --git a/include/asm-sh/socket.h b/include/asm-sh/socket.h new file mode 100644 index 0000000..dde696c --- /dev/null +++ b/include/asm-sh/socket.h @@ -0,0 +1,50 @@ +#ifndef __ASM_SH_SOCKET_H +#define __ASM_SH_SOCKET_H + +#include <asm/sockios.h> + +/* For setsockopt(2) */ +#define SOL_SOCKET 1 + +#define SO_DEBUG 1 +#define SO_REUSEADDR 2 +#define SO_TYPE 3 +#define SO_ERROR 4 +#define SO_DONTROUTE 5 +#define SO_BROADCAST 6 +#define SO_SNDBUF 7 +#define SO_RCVBUF 8 +#define SO_KEEPALIVE 9 +#define SO_OOBINLINE 10 +#define SO_NO_CHECK 11 +#define SO_PRIORITY 12 +#define SO_LINGER 13 +#define SO_BSDCOMPAT 14 +/* To add :#define SO_REUSEPORT 15 */ +#define SO_PASSCRED 16 +#define SO_PEERCRED 17 +#define SO_RCVLOWAT 18 +#define SO_SNDLOWAT 19 +#define SO_RCVTIMEO 20 +#define SO_SNDTIMEO 21 + +/* Security levels - as per NRL IPv6 - don't actually do anything */ +#define SO_SECURITY_AUTHENTICATION 22 +#define SO_SECURITY_ENCRYPTION_TRANSPORT 23 +#define SO_SECURITY_ENCRYPTION_NETWORK 24 + +#define SO_BINDTODEVICE 25 + +/* Socket filtering */ +#define SO_ATTACH_FILTER 26 +#define SO_DETACH_FILTER 27 + +#define SO_PEERNAME 28 +#define SO_TIMESTAMP 29 +#define SCM_TIMESTAMP SO_TIMESTAMP + +#define SO_ACCEPTCONN 30 + +#define SO_PEERSEC 31 + +#endif /* __ASM_SH_SOCKET_H */ diff --git a/include/asm-sh/sockios.h b/include/asm-sh/sockios.h new file mode 100644 index 0000000..08a71df --- /dev/null +++ b/include/asm-sh/sockios.h @@ -0,0 +1,13 @@ +#ifndef __ASM_SH_SOCKIOS_H +#define __ASM_SH_SOCKIOS_H + +/* Socket-level I/O control calls. */ +#define FIOGETOWN _IOR('f', 123, int) +#define FIOSETOWN _IOW('f', 124, int) + +#define SIOCATMARK _IOR('s', 7, int) +#define SIOCSPGRP _IOW('s', 8, pid_t) +#define SIOCGPGRP _IOR('s', 9, pid_t) + +#define SIOCGSTAMP _IOR('s', 100, struct timeval) /* Get stamp - linux-specific */ +#endif /* __ASM_SH_SOCKIOS_H */ diff --git a/include/asm-sh/spinlock.h b/include/asm-sh/spinlock.h new file mode 100644 index 0000000..e770b55 --- /dev/null +++ b/include/asm-sh/spinlock.h @@ -0,0 +1,124 @@ +/* + * include/asm-sh/spinlock.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_SPINLOCK_H +#define __ASM_SH_SPINLOCK_H + +#include <asm/atomic.h> + +/* + * Your basic SMP spinlocks, allowing only a single CPU anywhere + */ +typedef struct { + volatile unsigned long lock; +#ifdef CONFIG_PREEMPT + unsigned int break_lock; +#endif +} spinlock_t; + +#define SPIN_LOCK_UNLOCKED (spinlock_t) { 0 } + +#define spin_lock_init(x) do { *(x) = SPIN_LOCK_UNLOCKED; } while(0) + +#define spin_is_locked(x) ((x)->lock != 0) +#define spin_unlock_wait(x) do { barrier(); } while (spin_is_locked(x)) +#define _raw_spin_lock_flags(lock, flags) _raw_spin_lock(lock) + +/* + * Simple spin lock operations. There are two variants, one clears IRQ's + * on the local processor, one does not. + * + * We make no fairness assumptions. They have a cost. + */ +static inline void _raw_spin_lock(spinlock_t *lock) +{ + __asm__ __volatile__ ( + "1:\n\t" + "tas.b @%0\n\t" + "bf/s 1b\n\t" + "nop\n\t" + : "=r" (lock->lock) + : "r" (&lock->lock) + : "t", "memory" + ); +} + +static inline void _raw_spin_unlock(spinlock_t *lock) +{ + assert_spin_locked(lock); + + lock->lock = 0; +} + +#define _raw_spin_trylock(x) (!test_and_set_bit(0, &(x)->lock)) + +/* + * Read-write spinlocks, allowing multiple readers but only one writer. + * + * NOTE! it is quite common to have readers in interrupts but no interrupt + * writers. For those circumstances we can "mix" irq-safe locks - any writer + * needs to get a irq-safe write-lock, but readers can get non-irqsafe + * read-locks. + */ +typedef struct { + spinlock_t lock; + atomic_t counter; +#ifdef CONFIG_PREEMPT + unsigned int break_lock; +#endif +} rwlock_t; + +#define RW_LOCK_BIAS 0x01000000 +#define RW_LOCK_UNLOCKED (rwlock_t) { { 0 }, { RW_LOCK_BIAS } } +#define rwlock_init(x) do { *(x) = RW_LOCK_UNLOCKED; } while (0) + +static inline void _raw_read_lock(rwlock_t *rw) +{ + _raw_spin_lock(&rw->lock); + + atomic_inc(&rw->counter); + + _raw_spin_unlock(&rw->lock); +} + +static inline void _raw_read_unlock(rwlock_t *rw) +{ + _raw_spin_lock(&rw->lock); + + atomic_dec(&rw->counter); + + _raw_spin_unlock(&rw->lock); +} + +static inline void _raw_write_lock(rwlock_t *rw) +{ + _raw_spin_lock(&rw->lock); + atomic_set(&rw->counter, -1); +} + +static inline void _raw_write_unlock(rwlock_t *rw) +{ + atomic_set(&rw->counter, 0); + _raw_spin_unlock(&rw->lock); +} + +#define _raw_read_trylock(lock) generic_raw_read_trylock(lock) + +static inline int _raw_write_trylock(rwlock_t *rw) +{ + if (atomic_sub_and_test(RW_LOCK_BIAS, &rw->counter)) + return 1; + + atomic_add(RW_LOCK_BIAS, &rw->counter); + + return 0; +} + +#endif /* __ASM_SH_SPINLOCK_H */ + diff --git a/include/asm-sh/stat.h b/include/asm-sh/stat.h new file mode 100644 index 0000000..914e3fc --- /dev/null +++ b/include/asm-sh/stat.h @@ -0,0 +1,84 @@ +#ifndef __ASM_SH_STAT_H +#define __ASM_SH_STAT_H + +struct __old_kernel_stat { + unsigned short st_dev; + unsigned short st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned long st_size; + unsigned long st_atime; + unsigned long st_mtime; + unsigned long st_ctime; +}; + +struct stat { + unsigned short st_dev; + unsigned short __pad1; + unsigned long st_ino; + unsigned short st_mode; + unsigned short st_nlink; + unsigned short st_uid; + unsigned short st_gid; + unsigned short st_rdev; + unsigned short __pad2; + unsigned long st_size; + unsigned long st_blksize; + unsigned long st_blocks; + unsigned long st_atime; + unsigned long st_atime_nsec; + unsigned long st_mtime; + unsigned long st_mtime_nsec; + unsigned long st_ctime; + unsigned long st_ctime_nsec; + unsigned long __unused4; + unsigned long __unused5; +}; + +#define STAT_HAVE_NSEC 1 + +/* This matches struct stat64 in glibc2.1, hence the absolutely + * insane amounts of padding around dev_t's. + */ +struct stat64 { + unsigned long long st_dev; + unsigned char __pad0[4]; + + unsigned long st_ino; + unsigned int st_mode; + unsigned int st_nlink; + + unsigned long st_uid; + unsigned long st_gid; + + unsigned long long st_rdev; + unsigned char __pad3[4]; + + long long st_size; + unsigned long st_blksize; + +#if defined(__BIG_ENDIAN__) + unsigned long __pad4; /* Future possible st_blocks hi bits */ + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ +#else /* Must be little */ + unsigned long st_blocks; /* Number 512-byte blocks allocated. */ + unsigned long __pad4; /* Future possible st_blocks hi bits */ +#endif + + unsigned long st_atime; + unsigned long st_atime_nsec; + + unsigned long st_mtime; + unsigned long st_mtime_nsec; + + unsigned long st_ctime; + unsigned long st_ctime_nsec; + + unsigned long __unused1; + unsigned long __unused2; +}; + +#endif /* __ASM_SH_STAT_H */ diff --git a/include/asm-sh/statfs.h b/include/asm-sh/statfs.h new file mode 100644 index 0000000..9202a02 --- /dev/null +++ b/include/asm-sh/statfs.h @@ -0,0 +1,6 @@ +#ifndef __ASM_SH_STATFS_H +#define __ASM_SH_STATFS_H + +#include <asm-generic/statfs.h> + +#endif /* __ASM_SH_STATFS_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h new file mode 100644 index 0000000..3e0cff0 --- /dev/null +++ b/include/asm-sh/string.h @@ -0,0 +1,127 @@ +#ifndef __ASM_SH_STRING_H +#define __ASM_SH_STRING_H + +/* + * Copyright (C) 1999 Niibe Yutaka + * But consider these trivial functions to be public domain. + */ + +#define __HAVE_ARCH_STRCPY +static __inline__ char *strcpy(char *__dest, const char *__src) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + __asm__ __volatile__("1:\n\t" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bf/s 1b\n\t" + " add #1, %0\n\t" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRNCPY +static __inline__ char *strncpy(char *__dest, const char *__src, size_t __n) +{ + register char *__xdest = __dest; + unsigned long __dummy; + + if (__n == 0) + return __xdest; + + __asm__ __volatile__( + "1:\n" + "mov.b @%1+, %2\n\t" + "mov.b %2, @%0\n\t" + "cmp/eq #0, %2\n\t" + "bt/s 2f\n\t" + " cmp/eq %5,%1\n\t" + "bf/s 1b\n\t" + " add #1, %0\n" + "2:" + : "=r" (__dest), "=r" (__src), "=&z" (__dummy) + : "0" (__dest), "1" (__src), "r" (__src+__n) + : "memory", "t"); + + return __xdest; +} + +#define __HAVE_ARCH_STRCMP +static __inline__ int strcmp(const char *__cs, const char *__ct) +{ + register int __res; + unsigned long __dummy; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq #0, %3\n\t" + "bt 2f\n\t" + "cmp/eq %2, %3\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n\t" + "sub %3, %2\n" + "2:" + : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct) + : "t"); + + return __res; +} + +#define __HAVE_ARCH_STRNCMP +static __inline__ int strncmp(const char *__cs, const char *__ct, size_t __n) +{ + register int __res; + unsigned long __dummy; + + if (__n == 0) + return 0; + + __asm__ __volatile__( + "mov.b @%1+, %3\n" + "1:\n\t" + "mov.b @%0+, %2\n\t" + "cmp/eq %6, %0\n\t" + "bt/s 2f\n\t" + " cmp/eq #0, %3\n\t" + "bt/s 3f\n\t" + " cmp/eq %3, %2\n\t" + "bt/s 1b\n\t" + " mov.b @%1+, %3\n\t" + "add #-2, %1\n\t" + "mov.b @%1, %3\n" + "2:\n\t" + "sub %3, %2\n" + "3:" + :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) + : "0" (__cs), "1" (__ct), "r" (__cs+__n) + : "t"); + + return __res; +} + +#define __HAVE_ARCH_MEMSET +extern void *memset(void *__s, int __c, size_t __count); + +#define __HAVE_ARCH_MEMCPY +extern void *memcpy(void *__to, __const__ void *__from, size_t __n); + +#define __HAVE_ARCH_MEMMOVE +extern void *memmove(void *__dest, __const__ void *__src, size_t __n); + +#define __HAVE_ARCH_MEMCHR +extern void *memchr(const void *__s, int __c, size_t __n); + +#define __HAVE_ARCH_STRLEN +extern size_t strlen(const char *); + +#endif /* __ASM_SH_STRING_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h new file mode 100644 index 0000000..28a3c2d --- /dev/null +++ b/include/asm-sh/system.h @@ -0,0 +1,264 @@ +#ifndef __ASM_SH_SYSTEM_H +#define __ASM_SH_SYSTEM_H + +/* + * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima + * Copyright (C) 2002 Paul Mundt + */ + +#include <linux/config.h> + +/* + * switch_to() should switch tasks to task nr n, first + */ + +#define switch_to(prev, next, last) do { \ + task_t *__last; \ + register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \ + register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \ + register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \ + register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ + register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ + register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ + __asm__ __volatile__ (".balign 4\n\t" \ + "stc.l gbr, @-r15\n\t" \ + "sts.l pr, @-r15\n\t" \ + "mov.l r8, @-r15\n\t" \ + "mov.l r9, @-r15\n\t" \ + "mov.l r10, @-r15\n\t" \ + "mov.l r11, @-r15\n\t" \ + "mov.l r12, @-r15\n\t" \ + "mov.l r13, @-r15\n\t" \ + "mov.l r14, @-r15\n\t" \ + "mov.l r15, @r1 ! save SP\n\t" \ + "mov.l @r6, r15 ! change to new stack\n\t" \ + "mova 1f, %0\n\t" \ + "mov.l %0, @r2 ! save PC\n\t" \ + "mov.l 2f, %0\n\t" \ + "jmp @%0 ! call __switch_to\n\t" \ + " lds r7, pr ! with return to new PC\n\t" \ + ".balign 4\n" \ + "2:\n\t" \ + ".long __switch_to\n" \ + "1:\n\t" \ + "mov.l @r15+, r14\n\t" \ + "mov.l @r15+, r13\n\t" \ + "mov.l @r15+, r12\n\t" \ + "mov.l @r15+, r11\n\t" \ + "mov.l @r15+, r10\n\t" \ + "mov.l @r15+, r9\n\t" \ + "mov.l @r15+, r8\n\t" \ + "lds.l @r15+, pr\n\t" \ + "ldc.l @r15+, gbr\n\t" \ + : "=z" (__last) \ + : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ + "r" (__ts5), "r" (__ts6), "r" (__ts7) \ + : "r3", "t"); \ + last = __last; \ +} while (0) + +#define nop() __asm__ __volatile__ ("nop") + + +#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) + +static __inline__ unsigned long tas(volatile int *m) +{ /* #define tas(ptr) (xchg((ptr),1)) */ + unsigned long retval; + + __asm__ __volatile__ ("tas.b @%1\n\t" + "movt %0" + : "=r" (retval): "r" (m): "t", "memory"); + return retval; +} + +extern void __xchg_called_with_bad_pointer(void); + +#define mb() __asm__ __volatile__ ("": : :"memory") +#define rmb() mb() +#define wmb() __asm__ __volatile__ ("": : :"memory") +#define read_barrier_depends() do { } while(0) + +#ifdef CONFIG_SMP +#define smp_mb() mb() +#define smp_rmb() rmb() +#define smp_wmb() wmb() +#define smp_read_barrier_depends() read_barrier_depends() +#else +#define smp_mb() barrier() +#define smp_rmb() barrier() +#define smp_wmb() barrier() +#define smp_read_barrier_depends() do { } while(0) +#endif + +#define set_mb(var, value) do { xchg(&var, value); } while (0) +#define set_wmb(var, value) do { var = value; wmb(); } while (0) + +/* Interrupt Control */ +static __inline__ void local_irq_enable(void) +{ + unsigned long __dummy0, __dummy1; + + __asm__ __volatile__("stc sr, %0\n\t" + "and %1, %0\n\t" + "stc r6_bank, %1\n\t" + "or %1, %0\n\t" + "ldc %0, sr" + : "=&r" (__dummy0), "=r" (__dummy1) + : "1" (~0x000000f0) + : "memory"); +} + +static __inline__ void local_irq_disable(void) +{ + unsigned long __dummy; + __asm__ __volatile__("stc sr, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr" + : "=&z" (__dummy) + : /* no inputs */ + : "memory"); +} + +#define local_save_flags(x) \ + __asm__("stc sr, %0; and #0xf0, %0" : "=&z" (x) :/**/: "memory" ) + +#define irqs_disabled() \ +({ \ + unsigned long flags; \ + local_save_flags(flags); \ + (flags != 0); \ +}) + +static __inline__ unsigned long local_irq_save(void) +{ + unsigned long flags, __dummy; + + __asm__ __volatile__("stc sr, %1\n\t" + "mov %1, %0\n\t" + "or #0xf0, %0\n\t" + "ldc %0, sr\n\t" + "mov %1, %0\n\t" + "and #0xf0, %0" + : "=&z" (flags), "=&r" (__dummy) + :/**/ + : "memory" ); + return flags; +} + +#ifdef DEBUG_CLI_STI +static __inline__ void local_irq_restore(unsigned long x) +{ + if ((x & 0x000000f0) != 0x000000f0) + local_irq_enable(); + else { + unsigned long flags; + local_save_flags(flags); + + if (flags == 0) { + extern void dump_stack(void); + printk(KERN_ERR "BUG!\n"); + dump_stack(); + local_irq_disable(); + } + } +} +#else +#define local_irq_restore(x) do { \ + if ((x & 0x000000f0) != 0x000000f0) \ + local_irq_enable(); \ +} while (0) +#endif + +#define really_restore_flags(x) do { \ + if ((x & 0x000000f0) != 0x000000f0) \ + local_irq_enable(); \ + else \ + local_irq_disable(); \ +} while (0) + +/* + * Jump to P2 area. + * When handling TLB or caches, we need to do it from P2 area. + */ +#define jump_to_P2() \ +do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "mov.l 1f, %0\n\t" \ + "or %1, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy) \ + : "r" (0x20000000)); \ +} while (0) + +/* + * Back to P1 area. + */ +#define back_to_P1() \ +do { \ + unsigned long __dummy; \ + __asm__ __volatile__( \ + "nop;nop;nop;nop;nop;nop;nop\n\t" \ + "mov.l 1f, %0\n\t" \ + "jmp @%0\n\t" \ + " nop\n\t" \ + ".balign 4\n" \ + "1: .long 2f\n" \ + "2:" \ + : "=&r" (__dummy)); \ +} while (0) + +/* For spinlocks etc */ +#define local_irq_save(x) x = local_irq_save() + +static __inline__ unsigned long xchg_u32(volatile int * m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val; + local_irq_restore(flags); + return retval; +} + +static __inline__ unsigned long xchg_u8(volatile unsigned char * m, unsigned long val) +{ + unsigned long flags, retval; + + local_irq_save(flags); + retval = *m; + *m = val & 0xff; + local_irq_restore(flags); + return retval; +} + +static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr, int size) +{ + switch (size) { + case 4: + return xchg_u32(ptr, x); + break; + case 1: + return xchg_u8(ptr, x); + break; + } + __xchg_called_with_bad_pointer(); + return x; +} + +/* XXX + * disable hlt during certain critical i/o operations + */ +#define HAVE_DISABLE_HLT +void disable_hlt(void); +void enable_hlt(void); + +#define arch_align_stack(x) (x) + +#endif diff --git a/include/asm-sh/systemh/7751systemh.h b/include/asm-sh/systemh/7751systemh.h new file mode 100644 index 0000000..4170531 --- /dev/null +++ b/include/asm-sh/systemh/7751systemh.h @@ -0,0 +1,68 @@ +#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H +#define __ASM_SH_SYSTEMH_7751SYSTEMH_H + +/* + * linux/include/asm-sh/systemh/7751systemh.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SystemH support + + * Modified for 7751 SystemH by + * Jonathan Short, 2002. + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ +#define PA_LED 0xba000000 /* LED */ +#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_MODE (PA_MRSHPC + 4) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#define IRQ_79C973 13 + +#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */ diff --git a/include/asm-sh/systemh/io.h b/include/asm-sh/systemh/io.h new file mode 100644 index 0000000..327849b --- /dev/null +++ b/include/asm-sh/systemh/io.h @@ -0,0 +1,43 @@ +/* + * include/asm-sh/systemh/io.h + * + * Stupid I/O definitions for SystemH, cloned from SE7751. + * + * Copyright (C) 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_SYSTEMH_IO_H +#define __ASM_SH_SYSTEMH_IO_H + +extern unsigned char sh7751systemh_inb(unsigned long port); +extern unsigned short sh7751systemh_inw(unsigned long port); +extern unsigned int sh7751systemh_inl(unsigned long port); + +extern void sh7751systemh_outb(unsigned char value, unsigned long port); +extern void sh7751systemh_outw(unsigned short value, unsigned long port); +extern void sh7751systemh_outl(unsigned int value, unsigned long port); + +extern unsigned char sh7751systemh_inb_p(unsigned long port); +extern void sh7751systemh_outb_p(unsigned char value, unsigned long port); + +extern void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count); +extern void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count); +extern void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count); +extern void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count); +extern void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count); +extern void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count); + +extern unsigned char sh7751systemh_readb(unsigned long addr); +extern unsigned short sh7751systemh_readw(unsigned long addr); +extern unsigned int sh7751systemh_readl(unsigned long addr); +extern void sh7751systemh_writeb(unsigned char b, unsigned long addr); +extern void sh7751systemh_writew(unsigned short b, unsigned long addr); +extern void sh7751systemh_writel(unsigned int b, unsigned long addr); + +extern unsigned long sh7751systemh_isa_port2addr(unsigned long offset); + +#endif /* __ASM_SH_SYSTEMH_IO_H */ + diff --git a/include/asm-sh/termbits.h b/include/asm-sh/termbits.h new file mode 100644 index 0000000..4f9822a --- /dev/null +++ b/include/asm-sh/termbits.h @@ -0,0 +1,173 @@ +#ifndef __ASM_SH_TERMBITS_H +#define __ASM_SH_TERMBITS_H + +#include <linux/posix_types.h> + +typedef unsigned char cc_t; +typedef unsigned int speed_t; +typedef unsigned int tcflag_t; + +#define NCCS 19 +struct termios { + tcflag_t c_iflag; /* input mode flags */ + tcflag_t c_oflag; /* output mode flags */ + tcflag_t c_cflag; /* control mode flags */ + tcflag_t c_lflag; /* local mode flags */ + cc_t c_line; /* line discipline */ + cc_t c_cc[NCCS]; /* control characters */ +}; + +/* c_cc characters */ +#define VINTR 0 +#define VQUIT 1 +#define VERASE 2 +#define VKILL 3 +#define VEOF 4 +#define VTIME 5 +#define VMIN 6 +#define VSWTC 7 +#define VSTART 8 +#define VSTOP 9 +#define VSUSP 10 +#define VEOL 11 +#define VREPRINT 12 +#define VDISCARD 13 +#define VWERASE 14 +#define VLNEXT 15 +#define VEOL2 16 + +/* c_iflag bits */ +#define IGNBRK 0000001 +#define BRKINT 0000002 +#define IGNPAR 0000004 +#define PARMRK 0000010 +#define INPCK 0000020 +#define ISTRIP 0000040 +#define INLCR 0000100 +#define IGNCR 0000200 +#define ICRNL 0000400 +#define IUCLC 0001000 +#define IXON 0002000 +#define IXANY 0004000 +#define IXOFF 0010000 +#define IMAXBEL 0020000 +#define IUTF8 0040000 + +/* c_oflag bits */ +#define OPOST 0000001 +#define OLCUC 0000002 +#define ONLCR 0000004 +#define OCRNL 0000010 +#define ONOCR 0000020 +#define ONLRET 0000040 +#define OFILL 0000100 +#define OFDEL 0000200 +#define NLDLY 0000400 +#define NL0 0000000 +#define NL1 0000400 +#define CRDLY 0003000 +#define CR0 0000000 +#define CR1 0001000 +#define CR2 0002000 +#define CR3 0003000 +#define TABDLY 0014000 +#define TAB0 0000000 +#define TAB1 0004000 +#define TAB2 0010000 +#define TAB3 0014000 +#define XTABS 0014000 +#define BSDLY 0020000 +#define BS0 0000000 +#define BS1 0020000 +#define VTDLY 0040000 +#define VT0 0000000 +#define VT1 0040000 +#define FFDLY 0100000 +#define FF0 0000000 +#define FF1 0100000 + +/* c_cflag bit meaning */ +#define CBAUD 0010017 +#define B0 0000000 /* hang up */ +#define B50 0000001 +#define B75 0000002 +#define B110 0000003 +#define B134 0000004 +#define B150 0000005 +#define B200 0000006 +#define B300 0000007 +#define B600 0000010 +#define B1200 0000011 +#define B1800 0000012 +#define B2400 0000013 +#define B4800 0000014 +#define B9600 0000015 +#define B19200 0000016 +#define B38400 0000017 +#define EXTA B19200 +#define EXTB B38400 +#define CSIZE 0000060 +#define CS5 0000000 +#define CS6 0000020 +#define CS7 0000040 +#define CS8 0000060 +#define CSTOPB 0000100 +#define CREAD 0000200 +#define PARENB 0000400 +#define PARODD 0001000 +#define HUPCL 0002000 +#define CLOCAL 0004000 +#define CBAUDEX 0010000 +#define B57600 0010001 +#define B115200 0010002 +#define B230400 0010003 +#define B460800 0010004 +#define B500000 0010005 +#define B576000 0010006 +#define B921600 0010007 +#define B1000000 0010010 +#define B1152000 0010011 +#define B1500000 0010012 +#define B2000000 0010013 +#define B2500000 0010014 +#define B3000000 0010015 +#define B3500000 0010016 +#define B4000000 0010017 +#define CIBAUD 002003600000 /* input baud rate (not used) */ +#define CMSPAR 010000000000 /* mark or space (stick) parity */ +#define CRTSCTS 020000000000 /* flow control */ + +/* c_lflag bits */ +#define ISIG 0000001 +#define ICANON 0000002 +#define XCASE 0000004 +#define ECHO 0000010 +#define ECHOE 0000020 +#define ECHOK 0000040 +#define ECHONL 0000100 +#define NOFLSH 0000200 +#define TOSTOP 0000400 +#define ECHOCTL 0001000 +#define ECHOPRT 0002000 +#define ECHOKE 0004000 +#define FLUSHO 0010000 +#define PENDIN 0040000 +#define IEXTEN 0100000 + +/* tcflow() and TCXONC use these */ +#define TCOOFF 0 +#define TCOON 1 +#define TCIOFF 2 +#define TCION 3 + +/* tcflush() and TCFLSH use these */ +#define TCIFLUSH 0 +#define TCOFLUSH 1 +#define TCIOFLUSH 2 + +/* tcsetattr uses these */ +#define TCSANOW 0 +#define TCSADRAIN 1 +#define TCSAFLUSH 2 + +#endif /* __ASM_SH_TERMBITS_H */ diff --git a/include/asm-sh/termios.h b/include/asm-sh/termios.h new file mode 100644 index 0000000..44edfd4 --- /dev/null +++ b/include/asm-sh/termios.h @@ -0,0 +1,106 @@ +#ifndef __ASM_SH_TERMIOS_H +#define __ASM_SH_TERMIOS_H + +#include <asm/termbits.h> +#include <asm/ioctls.h> + +struct winsize { + unsigned short ws_row; + unsigned short ws_col; + unsigned short ws_xpixel; + unsigned short ws_ypixel; +}; + +#define NCC 8 +struct termio { + unsigned short c_iflag; /* input mode flags */ + unsigned short c_oflag; /* output mode flags */ + unsigned short c_cflag; /* control mode flags */ + unsigned short c_lflag; /* local mode flags */ + unsigned char c_line; /* line discipline */ + unsigned char c_cc[NCC]; /* control characters */ +}; + +/* modem lines */ +#define TIOCM_LE 0x001 +#define TIOCM_DTR 0x002 +#define TIOCM_RTS 0x004 +#define TIOCM_ST 0x008 +#define TIOCM_SR 0x010 +#define TIOCM_CTS 0x020 +#define TIOCM_CAR 0x040 +#define TIOCM_RNG 0x080 +#define TIOCM_DSR 0x100 +#define TIOCM_CD TIOCM_CAR +#define TIOCM_RI TIOCM_RNG +#define TIOCM_OUT1 0x2000 +#define TIOCM_OUT2 0x4000 +#define TIOCM_LOOP 0x8000 + +/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */ + +/* line disciplines */ +#define N_TTY 0 +#define N_SLIP 1 +#define N_MOUSE 2 +#define N_PPP 3 +#define N_STRIP 4 +#define N_AX25 5 +#define N_X25 6 /* X.25 async */ +#define N_6PACK 7 +#define N_MASC 8 /* Reserved for Mobitex module <kaz@cafe.net> */ +#define N_R3964 9 /* Reserved for Simatic R3964 module */ +#define N_PROFIBUS_FDL 10 /* Reserved for Profibus <Dave@mvhi.com> */ +#define N_IRDA 11 /* Linux IR - http://irda.sourceforge.net/ */ +#define N_SMSBLOCK 12 /* SMS block mode - for talking to GSM data cards about SMS messages */ +#define N_HDLC 13 /* synchronous HDLC */ +#define N_SYNC_PPP 14 +#define N_HCI 15 /* Bluetooth HCI UART */ + +#ifdef __KERNEL__ + +/* intr=^C quit=^\ erase=del kill=^U + eof=^D vtime=\0 vmin=\1 sxtc=\0 + start=^Q stop=^S susp=^Z eol=\0 + reprint=^R discard=^U werase=^W lnext=^V + eol2=\0 +*/ +#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0" + +/* + * Translate a "termio" structure into a "termios". Ugh. + */ +#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \ + unsigned short __tmp; \ + get_user(__tmp,&(termio)->x); \ + *(unsigned short *) &(termios)->x = __tmp; \ +} + +#define user_termio_to_kernel_termios(termios, termio) \ +({ \ + SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \ + SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \ + copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ +}) + +/* + * Translate a "termios" structure into a "termio". Ugh. + */ +#define kernel_termios_to_user_termio(termio, termios) \ +({ \ + put_user((termios)->c_iflag, &(termio)->c_iflag); \ + put_user((termios)->c_oflag, &(termio)->c_oflag); \ + put_user((termios)->c_cflag, &(termio)->c_cflag); \ + put_user((termios)->c_lflag, &(termio)->c_lflag); \ + put_user((termios)->c_line, &(termio)->c_line); \ + copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ +}) + +#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios)) +#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios)) + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_TERMIOS_H */ diff --git a/include/asm-sh/thread_info.h b/include/asm-sh/thread_info.h new file mode 100644 index 0000000..d82f883 --- /dev/null +++ b/include/asm-sh/thread_info.h @@ -0,0 +1,102 @@ +#ifndef __ASM_SH_THREAD_INFO_H +#define __ASM_SH_THREAD_INFO_H + +/* SuperH version + * Copyright (C) 2002 Niibe Yutaka + * + * The copyright of original i386 version is: + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + */ + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +#include <asm/processor.h> + +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + __u32 flags; /* low level flags */ + __u32 cpu; + __s32 preempt_count; /* 0 => preemptable, <0 => BUG */ + struct restart_block restart_block; + __u8 supervisor_stack[0]; +}; + +#endif + +#define PREEMPT_ACTIVE 0x4000000 + +/* + * macros/functions for gaining access to the thread information structure + */ +#ifndef __ASSEMBLY__ +#define INIT_THREAD_INFO(tsk) \ +{ \ + .task = &tsk, \ + .exec_domain = &default_exec_domain, \ + .flags = 0, \ + .cpu = 0, \ + .preempt_count = 1, \ + .restart_block = { \ + .fn = do_no_restart_syscall, \ + }, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__("stc r7_bank, %0" : "=r" (ti)); + return ti; +} + +/* thread information allocation */ +#define THREAD_SIZE (2*PAGE_SIZE) +#define alloc_thread_info(ti) ((struct thread_info *) __get_free_pages(GFP_KERNEL,1)) +#define free_thread_info(ti) free_pages((unsigned long) (ti), 1) +#define get_thread_info(ti) get_task_struct((ti)->task) +#define put_thread_info(ti) put_task_struct((ti)->task) + +#else /* !__ASSEMBLY__ */ + +/* how to get the thread information struct from ASM */ +#define GET_THREAD_INFO(reg) \ + stc r7_bank, reg + +#endif + +/* + * thread information flags + * - these are process state flags that various assembly files may need to access + * - pending work-to-be-done flags are in LSW + * - other flags in MSW + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_USEDFPU 16 /* FPU was used by this task this quantum (SMP) */ +#define TIF_POLLING_NRFLAG 17 /* true if poll_idle() is polling TIF_NEED_RESCHED */ +#define TIF_MEMDIE 18 +#define TIF_USERSPACE 31 /* true if FS sets userspace */ + +#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) +#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) +#define _TIF_USEDFPU (1<<TIF_USEDFPU) +#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) +#define _TIF_USERSPACE (1<<TIF_USERSPACE) + +#define _TIF_WORK_MASK 0x000000FE /* work to do on interrupt/exception return */ +#define _TIF_ALLWORK_MASK 0x000000FF /* work to do on any return to u-space */ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_THREAD_INFO_H */ diff --git a/include/asm-sh/timex.h b/include/asm-sh/timex.h new file mode 100644 index 0000000..a873e24 --- /dev/null +++ b/include/asm-sh/timex.h @@ -0,0 +1,18 @@ +/* + * linux/include/asm-sh/timex.h + * + * sh architecture timex specifications + */ +#ifndef __ASM_SH_TIMEX_H +#define __ASM_SH_TIMEX_H + +#define CLOCK_TICK_RATE (CONFIG_SH_PCLK_FREQ / 4) /* Underlying HZ */ + +typedef unsigned long long cycles_t; + +static __inline__ cycles_t get_cycles (void) +{ + return 0; +} + +#endif /* __ASM_SH_TIMEX_H */ diff --git a/include/asm-sh/tlb.h b/include/asm-sh/tlb.h new file mode 100644 index 0000000..53d185b --- /dev/null +++ b/include/asm-sh/tlb.h @@ -0,0 +1,18 @@ +#ifndef __ASM_SH_TLB_H +#define __ASM_SH_TLB_H + +#define tlb_start_vma(tlb, vma) \ + flush_cache_range(vma, vma->vm_start, vma->vm_end) + +#define tlb_end_vma(tlb, vma) \ + flush_tlb_range(vma, vma->vm_start, vma->vm_end) + +#define __tlb_remove_tlb_entry(tlb, pte, address) do { } while (0) + +/* + * Flush whole TLBs for MM + */ +#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm) + +#include <asm-generic/tlb.h> +#endif diff --git a/include/asm-sh/tlbflush.h b/include/asm-sh/tlbflush.h new file mode 100644 index 0000000..28c073b --- /dev/null +++ b/include/asm-sh/tlbflush.h @@ -0,0 +1,31 @@ +#ifndef __ASM_SH_TLBFLUSH_H +#define __ASM_SH_TLBFLUSH_H + +/* + * TLB flushing: + * + * - flush_tlb() flushes the current mm struct TLBs + * - flush_tlb_all() flushes all processes TLBs + * - flush_tlb_mm(mm) flushes the specified mm context TLB's + * - flush_tlb_page(vma, vmaddr) flushes one page + * - flush_tlb_range(vma, start, end) flushes a range of pages + * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages + * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables + */ + +extern void flush_tlb(void); +extern void flush_tlb_all(void); +extern void flush_tlb_mm(struct mm_struct *mm); +extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, + unsigned long end); +extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page); +extern void __flush_tlb_page(unsigned long asid, unsigned long page); + +static inline void flush_tlb_pgtables(struct mm_struct *mm, + unsigned long start, unsigned long end) +{ /* Nothing to do */ +} + +extern void flush_tlb_kernel_range(unsigned long start, unsigned long end); + +#endif /* __ASM_SH_TLBFLUSH_H */ diff --git a/include/asm-sh/topology.h b/include/asm-sh/topology.h new file mode 100644 index 0000000..cff001c --- /dev/null +++ b/include/asm-sh/topology.h @@ -0,0 +1,6 @@ +#ifndef _ASM_SH_TOPOLOGY_H +#define _ASM_SH_TOPOLOGY_H + +#include <asm-generic/topology.h> + +#endif /* _ASM_SH_TOPOLOGY_H */ diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h new file mode 100644 index 0000000..c4dc126 --- /dev/null +++ b/include/asm-sh/types.h @@ -0,0 +1,67 @@ +#ifndef __ASM_SH_TYPES_H +#define __ASM_SH_TYPES_H + +#ifndef __ASSEMBLY__ + +typedef unsigned short umode_t; + +/* + * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the + * header files exported to user space + */ + +typedef __signed__ char __s8; +typedef unsigned char __u8; + +typedef __signed__ short __s16; +typedef unsigned short __u16; + +typedef __signed__ int __s32; +typedef unsigned int __u32; + +#if defined(__GNUC__) && !defined(__STRICT_ANSI__) +typedef __signed__ long long __s64; +typedef unsigned long long __u64; +#endif + +#endif /* __ASSEMBLY__ */ + +/* + * These aren't exported outside the kernel to avoid name space clashes + */ +#ifdef __KERNEL__ + +#define BITS_PER_LONG 32 + +#ifndef __ASSEMBLY__ + +#include <linux/config.h> + +typedef __signed__ char s8; +typedef unsigned char u8; + +typedef __signed__ short s16; +typedef unsigned short u16; + +typedef __signed__ int s32; +typedef unsigned int u32; + +typedef __signed__ long long s64; +typedef unsigned long long u64; + +/* Dma addresses are 32-bits wide. */ + +typedef u32 dma_addr_t; + +#ifdef CONFIG_LBD +typedef u64 sector_t; +#define HAVE_SECTOR_T +#endif + +typedef unsigned int kmem_bufctl_t; + +#endif /* __ASSEMBLY__ */ + +#endif /* __KERNEL__ */ + +#endif /* __ASM_SH_TYPES_H */ diff --git a/include/asm-sh/uaccess.h b/include/asm-sh/uaccess.h new file mode 100644 index 0000000..fb9e334 --- /dev/null +++ b/include/asm-sh/uaccess.h @@ -0,0 +1,600 @@ +/* $Id: uaccess.h,v 1.11 2003/10/13 07:21:20 lethal Exp $ + * + * User space memory access functions + * + * Copyright (C) 1999, 2002 Niibe Yutaka + * Copyright (C) 2003 Paul Mundt + * + * Based on: + * MIPS implementation version 1.15 by + * Copyright (C) 1996, 1997, 1998 by Ralf Baechle + * and i386 version. + */ +#ifndef __ASM_SH_UACCESS_H +#define __ASM_SH_UACCESS_H + +#include <linux/errno.h> +#include <linux/sched.h> + +/* + * NOTE: Macro/functions in this file depends on threads_info.h implementation. + * Assumes: + * TI_FLAGS == 8 + * TIF_USERSPACE == 31 + * USER_ADDR_LIMIT == 0x80000000 + */ + +#define VERIFY_READ 0 +#define VERIFY_WRITE 1 + +typedef struct { + unsigned int is_user_space; +} mm_segment_t; + +/* + * The fs value determines whether argument validity checking should be + * performed or not. If get_fs() == USER_DS, checking is performed, with + * get_fs() == KERNEL_DS, checking is bypassed. + * + * For historical reasons (Data Segment Register?), these macros are misnamed. + */ + +#define MAKE_MM_SEG(s) ((mm_segment_t) { (s) }) +#define segment_eq(a,b) ((a).is_user_space == (b).is_user_space) + +#define USER_ADDR_LIMIT 0x80000000 + +#define KERNEL_DS MAKE_MM_SEG(0) +#define USER_DS MAKE_MM_SEG(1) + +#define get_ds() (KERNEL_DS) + +#if !defined(CONFIG_MMU) +static inline mm_segment_t get_fs(void) +{ + return USER_DS; +} + +static inline void set_fs(mm_segment_t s) +{ +} + +/* + * __access_ok: Check if address with size is OK or not. + * + * If we don't have an MMU (or if its disabled) the only thing we really have + * to look out for is if the address resides somewhere outside of what + * available RAM we have. + * + * TODO: This check could probably also stand to be restricted somewhat more.. + * though it still does the Right Thing(tm) for the time being. + */ +static inline int __access_ok(unsigned long addr, unsigned long size) +{ + extern unsigned long memory_start, memory_end; + + return ((addr >= memory_start) && ((addr + size) < memory_end)); +} +#else /* CONFIG_MMU */ +static inline mm_segment_t get_fs(void) +{ + return MAKE_MM_SEG(test_thread_flag(TIF_USERSPACE)); +} + +static inline void set_fs(mm_segment_t s) +{ + unsigned long ti, flag; + __asm__ __volatile__( + "stc r7_bank, %0\n\t" + "mov.l @(8,%0), %1\n\t" + "shal %1\n\t" + "cmp/pl %2\n\t" + "rotcr %1\n\t" + "mov.l %1, @(8,%0)" + : "=&r" (ti), "=&r" (flag) + : "r" (s.is_user_space) + : "t"); +/**** + if (s.is_user_space) + set_thread_flag(TIF_USERSPACE); + else + clear_thread_flag(TIF_USERSPACE); +****/ +} + +/* + * __access_ok: Check if address with size is OK or not. + * + * We do three checks: + * (1) is it user space? + * (2) addr + size --> carry? + * (3) addr + size >= 0x80000000 (USER_ADDR_LIMIT) + * + * (1) (2) (3) | RESULT + * 0 0 0 | ok + * 0 0 1 | ok + * 0 1 0 | bad + * 0 1 1 | bad + * 1 0 0 | ok + * 1 0 1 | bad + * 1 1 0 | bad + * 1 1 1 | bad + */ +static inline int __access_ok(unsigned long addr, unsigned long size) +{ + unsigned long flag, tmp; + + __asm__("stc r7_bank, %0\n\t" + "mov.l @(8,%0), %0\n\t" + "clrt\n\t" + "addc %2, %1\n\t" + "and %1, %0\n\t" + "rotcl %0\n\t" + "rotcl %0\n\t" + "and #3, %0" + : "=&z" (flag), "=r" (tmp) + : "r" (addr), "1" (size) + : "t"); + + return flag == 0; +} +#endif /* CONFIG_MMU */ + +static inline int access_ok(int type, const void __user *p, unsigned long size) +{ + unsigned long addr = (unsigned long)p; + return __access_ok(addr, size); +} + +/* this function will go away soon - use access_ok() instead */ +static inline int __deprecated verify_area(int type, const void __user * addr, unsigned long size) +{ + return access_ok(type,addr,size) ? 0 : -EFAULT; +} + +/* + * Uh, these should become the main single-value transfer routines ... + * They automatically use the right size if we just have the right + * pointer type ... + * + * As SuperH uses the same address space for kernel and user data, we + * can just do these as direct assignments. + * + * Careful to not + * (a) re-use the arguments for side effects (sizeof is ok) + * (b) require any knowledge of processes at this stage + */ +#define put_user(x,ptr) __put_user_check((x),(ptr),sizeof(*(ptr))) +#define get_user(x,ptr) __get_user_check((x),(ptr),sizeof(*(ptr))) + +/* + * The "__xxx" versions do not do address space checking, useful when + * doing multiple accesses to the same area (the user has to do the + * checks by hand with "access_ok()") + */ +#define __put_user(x,ptr) \ + __put_user_nocheck((__typeof__(*(ptr)))(x),(ptr),sizeof(*(ptr))) +#define __get_user(x,ptr) \ + __get_user_nocheck((x),(ptr),sizeof(*(ptr))) + +struct __large_struct { unsigned long buf[100]; }; +#define __m(x) (*(struct __large_struct *)(x)) + +#define __get_user_size(x,ptr,size,retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: \ + __get_user_asm(x, ptr, retval, "b"); \ + break; \ + case 2: \ + __get_user_asm(x, ptr, retval, "w"); \ + break; \ + case 4: \ + __get_user_asm(x, ptr, retval, "l"); \ + break; \ + default: \ + __get_user_unknown(); \ + break; \ + } \ +} while (0) + +#define __get_user_nocheck(x,ptr,size) \ +({ \ + long __gu_err, __gu_val; \ + __get_user_size(__gu_val, (ptr), (size), __gu_err); \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __get_user_check(x,ptr,size) \ +({ \ + long __gu_err, __gu_val; \ + switch (size) { \ + case 1: \ + __get_user_1(__gu_val, (ptr), __gu_err); \ + break; \ + case 2: \ + __get_user_2(__gu_val, (ptr), __gu_err); \ + break; \ + case 4: \ + __get_user_4(__gu_val, (ptr), __gu_err); \ + break; \ + default: \ + __get_user_unknown(); \ + break; \ + } \ + \ + (x) = (__typeof__(*(ptr)))__gu_val; \ + __gu_err; \ +}) + +#define __get_user_1(x,addr,err) ({ \ +__asm__("stc r7_bank, %1\n\t" \ + "mov.l @(8,%1), %1\n\t" \ + "and %2, %1\n\t" \ + "cmp/pz %1\n\t" \ + "bt/s 1f\n\t" \ + " mov #0, %0\n\t" \ + "0:\n" \ + "mov #-14, %0\n\t" \ + "bra 2f\n\t" \ + " mov #0, %1\n" \ + "1:\n\t" \ + "mov.b @%2, %1\n\t" \ + "extu.b %1, %1\n" \ + "2:\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 0b\n\t" \ + ".previous" \ + : "=&r" (err), "=&r" (x) \ + : "r" (addr) \ + : "t"); \ +}) + +#define __get_user_2(x,addr,err) ({ \ +__asm__("stc r7_bank, %1\n\t" \ + "mov.l @(8,%1), %1\n\t" \ + "and %2, %1\n\t" \ + "cmp/pz %1\n\t" \ + "bt/s 1f\n\t" \ + " mov #0, %0\n\t" \ + "0:\n" \ + "mov #-14, %0\n\t" \ + "bra 2f\n\t" \ + " mov #0, %1\n" \ + "1:\n\t" \ + "mov.w @%2, %1\n\t" \ + "extu.w %1, %1\n" \ + "2:\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 0b\n\t" \ + ".previous" \ + : "=&r" (err), "=&r" (x) \ + : "r" (addr) \ + : "t"); \ +}) + +#define __get_user_4(x,addr,err) ({ \ +__asm__("stc r7_bank, %1\n\t" \ + "mov.l @(8,%1), %1\n\t" \ + "and %2, %1\n\t" \ + "cmp/pz %1\n\t" \ + "bt/s 1f\n\t" \ + " mov #0, %0\n\t" \ + "0:\n" \ + "mov #-14, %0\n\t" \ + "bra 2f\n\t" \ + " mov #0, %1\n" \ + "1:\n\t" \ + "mov.l @%2, %1\n\t" \ + "2:\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 0b\n\t" \ + ".previous" \ + : "=&r" (err), "=&r" (x) \ + : "r" (addr) \ + : "t"); \ +}) + +#define __get_user_asm(x, addr, err, insn) \ +({ \ +__asm__ __volatile__( \ + "1:\n\t" \ + "mov." insn " %2, %1\n\t" \ + "mov #0, %0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:\n\t" \ + "mov #0, %1\n\t" \ + "mov.l 4f, %0\n\t" \ + "jmp @%0\n\t" \ + " mov %3, %0\n" \ + "4: .long 2b\n\t" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 3b\n\t" \ + ".previous" \ + :"=&r" (err), "=&r" (x) \ + :"m" (__m(addr)), "i" (-EFAULT)); }) + +extern void __get_user_unknown(void); + +#define __put_user_size(x,ptr,size,retval) \ +do { \ + retval = 0; \ + switch (size) { \ + case 1: \ + __put_user_asm(x, ptr, retval, "b"); \ + break; \ + case 2: \ + __put_user_asm(x, ptr, retval, "w"); \ + break; \ + case 4: \ + __put_user_asm(x, ptr, retval, "l"); \ + break; \ + case 8: \ + __put_user_u64(x, ptr, retval); \ + break; \ + default: \ + __put_user_unknown(); \ + } \ +} while (0) + +#define __put_user_nocheck(x,ptr,size) \ +({ \ + long __pu_err; \ + __put_user_size((x),(ptr),(size),__pu_err); \ + __pu_err; \ +}) + +#define __put_user_check(x,ptr,size) \ +({ \ + long __pu_err = -EFAULT; \ + __typeof__(*(ptr)) *__pu_addr = (ptr); \ + \ + if (__access_ok((unsigned long)__pu_addr,size)) \ + __put_user_size((x),__pu_addr,(size),__pu_err); \ + __pu_err; \ +}) + +#define __put_user_asm(x, addr, err, insn) \ +({ \ +__asm__ __volatile__( \ + "1:\n\t" \ + "mov." insn " %1, %2\n\t" \ + "mov #0, %0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:\n\t" \ + "nop\n\t" \ + "mov.l 4f, %0\n\t" \ + "jmp @%0\n\t" \ + "mov %3, %0\n" \ + "4: .long 2b\n\t" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 3b\n\t" \ + ".previous" \ + :"=&r" (err) \ + :"r" (x), "m" (__m(addr)), "i" (-EFAULT) \ + :"memory"); }) + +#if defined(__LITTLE_ENDIAN__) +#define __put_user_u64(val,addr,retval) \ +({ \ +__asm__ __volatile__( \ + "1:\n\t" \ + "mov.l %R1,%2\n\t" \ + "mov.l %S1,%T2\n\t" \ + "mov #0,%0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:\n\t" \ + "nop\n\t" \ + "mov.l 4f,%0\n\t" \ + "jmp @%0\n\t" \ + " mov %3,%0\n" \ + "4: .long 2b\n\t" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 3b\n\t" \ + ".previous" \ + : "=r" (retval) \ + : "r" (val), "m" (__m(addr)), "i" (-EFAULT) \ + : "memory"); }) +#else +#define __put_user_u64(val,addr,retval) \ +({ \ +__asm__ __volatile__( \ + "1:\n\t" \ + "mov.l %S1,%2\n\t" \ + "mov.l %R1,%T2\n\t" \ + "mov #0,%0\n" \ + "2:\n" \ + ".section .fixup,\"ax\"\n" \ + "3:\n\t" \ + "nop\n\t" \ + "mov.l 4f,%0\n\t" \ + "jmp @%0\n\t" \ + " mov %3,%0\n" \ + "4: .long 2b\n\t" \ + ".previous\n" \ + ".section __ex_table,\"a\"\n\t" \ + ".long 1b, 3b\n\t" \ + ".previous" \ + : "=r" (retval) \ + : "r" (val), "m" (__m(addr)), "i" (-EFAULT) \ + : "memory"); }) +#endif + +extern void __put_user_unknown(void); + +/* Generic arbitrary sized copy. */ +/* Return the number of bytes NOT copied */ +extern __kernel_size_t __copy_user(void *to, const void *from, __kernel_size_t n); + +#define copy_to_user(to,from,n) ({ \ +void *__copy_to = (void *) (to); \ +__kernel_size_t __copy_size = (__kernel_size_t) (n); \ +__kernel_size_t __copy_res; \ +if(__copy_size && __access_ok((unsigned long)__copy_to, __copy_size)) { \ +__copy_res = __copy_user(__copy_to, (void *) (from), __copy_size); \ +} else __copy_res = __copy_size; \ +__copy_res; }) + +#define __copy_to_user(to,from,n) \ + __copy_user((void *)(to), \ + (void *)(from), n) + +#define __copy_to_user_inatomic __copy_to_user +#define __copy_from_user_inatomic __copy_from_user + + +#define copy_from_user(to,from,n) ({ \ +void *__copy_to = (void *) (to); \ +void *__copy_from = (void *) (from); \ +__kernel_size_t __copy_size = (__kernel_size_t) (n); \ +__kernel_size_t __copy_res; \ +if(__copy_size && __access_ok((unsigned long)__copy_from, __copy_size)) { \ +__copy_res = __copy_user(__copy_to, __copy_from, __copy_size); \ +} else __copy_res = __copy_size; \ +__copy_res; }) + +#define __copy_from_user(to,from,n) \ + __copy_user((void *)(to), \ + (void *)(from), n) + +/* + * Clear the area and return remaining number of bytes + * (on failure. Usually it's 0.) + */ +extern __kernel_size_t __clear_user(void *addr, __kernel_size_t size); + +#define clear_user(addr,n) ({ \ +void * __cl_addr = (addr); \ +unsigned long __cl_size = (n); \ +if (__cl_size && __access_ok(((unsigned long)(__cl_addr)), __cl_size)) \ +__cl_size = __clear_user(__cl_addr, __cl_size); \ +__cl_size; }) + +static __inline__ int +__strncpy_from_user(unsigned long __dest, unsigned long __user __src, int __count) +{ + __kernel_size_t res; + unsigned long __dummy, _d, _s; + + __asm__ __volatile__( + "9:\n" + "mov.b @%2+, %1\n\t" + "cmp/eq #0, %1\n\t" + "bt/s 2f\n" + "1:\n" + "mov.b %1, @%3\n\t" + "dt %7\n\t" + "bf/s 9b\n\t" + " add #1, %3\n\t" + "2:\n\t" + "sub %7, %0\n" + "3:\n" + ".section .fixup,\"ax\"\n" + "4:\n\t" + "mov.l 5f, %1\n\t" + "jmp @%1\n\t" + " mov %8, %0\n\t" + ".balign 4\n" + "5: .long 3b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" + " .balign 4\n" + " .long 9b,4b\n" + ".previous" + : "=r" (res), "=&z" (__dummy), "=r" (_s), "=r" (_d) + : "0" (__count), "2" (__src), "3" (__dest), "r" (__count), + "i" (-EFAULT) + : "memory", "t"); + + return res; +} + +#define strncpy_from_user(dest,src,count) ({ \ +unsigned long __sfu_src = (unsigned long) (src); \ +int __sfu_count = (int) (count); \ +long __sfu_res = -EFAULT; \ +if(__access_ok(__sfu_src, __sfu_count)) { \ +__sfu_res = __strncpy_from_user((unsigned long) (dest), __sfu_src, __sfu_count); \ +} __sfu_res; }) + +/* + * Return the size of a string (including the ending 0!) + */ +static __inline__ long __strnlen_user(const char __user *__s, long __n) +{ + unsigned long res; + unsigned long __dummy; + + __asm__ __volatile__( + "9:\n" + "cmp/eq %4, %0\n\t" + "bt 2f\n" + "1:\t" + "mov.b @(%0,%3), %1\n\t" + "tst %1, %1\n\t" + "bf/s 9b\n\t" + " add #1, %0\n" + "2:\n" + ".section .fixup,\"ax\"\n" + "3:\n\t" + "mov.l 4f, %1\n\t" + "jmp @%1\n\t" + " mov %5, %0\n" + ".balign 4\n" + "4: .long 2b\n" + ".previous\n" + ".section __ex_table,\"a\"\n" + " .balign 4\n" + " .long 1b,3b\n" + ".previous" + : "=z" (res), "=&r" (__dummy) + : "0" (0), "r" (__s), "r" (__n), "i" (-EFAULT) + : "t"); + return res; +} + +static __inline__ long strnlen_user(const char __user *s, long n) +{ + if (!access_ok(VERIFY_READ, s, n)) + return 0; + else + return __strnlen_user(s, n); +} + +static __inline__ long strlen_user(const char __user *s) +{ + if (!access_ok(VERIFY_READ, s, 0)) + return 0; + else + return __strnlen_user(s, ~0UL >> 1); +} + +/* + * The exception table consists of pairs of addresses: the first is the + * address of an instruction that is allowed to fault, and the second is + * the address at which the program should continue. No registers are + * modified, so it is entirely up to the continuation code to figure out + * what to do. + * + * All the routines below use bits of fixup code that are out of line + * with the main instruction path. This means when everything is well, + * we don't even have to jump over them. Further, they do not intrude + * on our cache or tlb entries. + */ + +struct exception_table_entry +{ + unsigned long insn, fixup; +}; + +extern int fixup_exception(struct pt_regs *regs); + +#endif /* __ASM_SH_UACCESS_H */ diff --git a/include/asm-sh/ubc.h b/include/asm-sh/ubc.h new file mode 100644 index 0000000..694f51f --- /dev/null +++ b/include/asm-sh/ubc.h @@ -0,0 +1,60 @@ +/* + * include/asm-sh/ubc.h + * + * Copyright (C) 1999 Niibe Yutaka + * Copyright (C) 2002, 2003 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#ifndef __ASM_SH_UBC_H +#define __ASM_SH_UBC_H +#ifdef __KERNEL__ + +#include <asm/cpu/ubc.h> + +/* User Break Controller */ +#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ + defined(CONFIG_CPU_SUBTYPE_SH7300) +#define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729) +#else +#define UBC_TYPE_SH7729 0 +#endif + +#define BAMR_ASID (1 << 2) +#define BAMR_NONE 0 +#define BAMR_10 0x1 +#define BAMR_12 0x2 +#define BAMR_ALL 0x3 +#define BAMR_16 0x8 +#define BAMR_20 0x9 + +#define BBR_INST (1 << 4) +#define BBR_DATA (2 << 4) +#define BBR_READ (1 << 2) +#define BBR_WRITE (2 << 2) +#define BBR_BYTE 0x1 +#define BBR_HALF 0x2 +#define BBR_LONG 0x3 +#define BBR_QUAD (1 << 6) /* SH7750 */ +#define BBR_CPU (1 << 6) /* SH7709A,SH7729 */ +#define BBR_DMA (2 << 6) /* SH7709A,SH7729 */ + +#define BRCR_CMFA (1 << 15) +#define BRCR_CMFB (1 << 14) +#define BRCR_PCTE (1 << 11) +#define BRCR_PCBA (1 << 10) /* 1: after execution */ +#define BRCR_DBEB (1 << 7) +#define BRCR_PCBB (1 << 6) +#define BRCR_SEQ (1 << 3) +#define BRCR_UBDE (1 << 0) + +#ifndef __ASSEMBLY__ +/* arch/sh/kernel/ubc.S */ +extern void ubc_wakeup(void); +extern void ubc_sleep(void); +#endif + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_UBC_H */ diff --git a/include/asm-sh/ucontext.h b/include/asm-sh/ucontext.h new file mode 100644 index 0000000..202ef1d --- /dev/null +++ b/include/asm-sh/ucontext.h @@ -0,0 +1,12 @@ +#ifndef __ASM_SH_UCONTEXT_H +#define __ASM_SH_UCONTEXT_H + +struct ucontext { + unsigned long uc_flags; + struct ucontext *uc_link; + stack_t uc_stack; + struct sigcontext uc_mcontext; + sigset_t uc_sigmask; /* mask last for extensibility */ +}; + +#endif /* __ASM_SH_UCONTEXT_H */ diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h new file mode 100644 index 0000000..5250e30 --- /dev/null +++ b/include/asm-sh/unaligned.h @@ -0,0 +1,7 @@ +#ifndef __ASM_SH_UNALIGNED_H +#define __ASM_SH_UNALIGNED_H + +/* SH can't handle unaligned accesses. */ +#include <asm-generic/unaligned.h> + +#endif /* __ASM_SH_UNALIGNED_H */ diff --git a/include/asm-sh/unistd.h b/include/asm-sh/unistd.h new file mode 100644 index 0000000..2454470 --- /dev/null +++ b/include/asm-sh/unistd.h @@ -0,0 +1,523 @@ +#ifndef __ASM_SH_UNISTD_H +#define __ASM_SH_UNISTD_H + +/* + * Copyright (C) 1999 Niibe Yutaka + */ + +/* + * This file contains the system call numbers. + */ + +#define __NR_restart_syscall 0 +#define __NR_exit 1 +#define __NR_fork 2 +#define __NR_read 3 +#define __NR_write 4 +#define __NR_open 5 +#define __NR_close 6 +#define __NR_waitpid 7 +#define __NR_creat 8 +#define __NR_link 9 +#define __NR_unlink 10 +#define __NR_execve 11 +#define __NR_chdir 12 +#define __NR_time 13 +#define __NR_mknod 14 +#define __NR_chmod 15 +#define __NR_lchown 16 +#define __NR_break 17 +#define __NR_oldstat 18 +#define __NR_lseek 19 +#define __NR_getpid 20 +#define __NR_mount 21 +#define __NR_umount 22 +#define __NR_setuid 23 +#define __NR_getuid 24 +#define __NR_stime 25 +#define __NR_ptrace 26 +#define __NR_alarm 27 +#define __NR_oldfstat 28 +#define __NR_pause 29 +#define __NR_utime 30 +#define __NR_stty 31 +#define __NR_gtty 32 +#define __NR_access 33 +#define __NR_nice 34 +#define __NR_ftime 35 +#define __NR_sync 36 +#define __NR_kill 37 +#define __NR_rename 38 +#define __NR_mkdir 39 +#define __NR_rmdir 40 +#define __NR_dup 41 +#define __NR_pipe 42 +#define __NR_times 43 +#define __NR_prof 44 +#define __NR_brk 45 +#define __NR_setgid 46 +#define __NR_getgid 47 +#define __NR_signal 48 +#define __NR_geteuid 49 +#define __NR_getegid 50 +#define __NR_acct 51 +#define __NR_umount2 52 +#define __NR_lock 53 +#define __NR_ioctl 54 +#define __NR_fcntl 55 +#define __NR_mpx 56 +#define __NR_setpgid 57 +#define __NR_ulimit 58 +#define __NR_oldolduname 59 +#define __NR_umask 60 +#define __NR_chroot 61 +#define __NR_ustat 62 +#define __NR_dup2 63 +#define __NR_getppid 64 +#define __NR_getpgrp 65 +#define __NR_setsid 66 +#define __NR_sigaction 67 +#define __NR_sgetmask 68 +#define __NR_ssetmask 69 +#define __NR_setreuid 70 +#define __NR_setregid 71 +#define __NR_sigsuspend 72 +#define __NR_sigpending 73 +#define __NR_sethostname 74 +#define __NR_setrlimit 75 +#define __NR_getrlimit 76 /* Back compatible 2Gig limited rlimit */ +#define __NR_getrusage 77 +#define __NR_gettimeofday 78 +#define __NR_settimeofday 79 +#define __NR_getgroups 80 +#define __NR_setgroups 81 +#define __NR_select 82 +#define __NR_symlink 83 +#define __NR_oldlstat 84 +#define __NR_readlink 85 +#define __NR_uselib 86 +#define __NR_swapon 87 +#define __NR_reboot 88 +#define __NR_readdir 89 +#define __NR_mmap 90 +#define __NR_munmap 91 +#define __NR_truncate 92 +#define __NR_ftruncate 93 +#define __NR_fchmod 94 +#define __NR_fchown 95 +#define __NR_getpriority 96 +#define __NR_setpriority 97 +#define __NR_profil 98 +#define __NR_statfs 99 +#define __NR_fstatfs 100 +#define __NR_ioperm 101 +#define __NR_socketcall 102 +#define __NR_syslog 103 +#define __NR_setitimer 104 +#define __NR_getitimer 105 +#define __NR_stat 106 +#define __NR_lstat 107 +#define __NR_fstat 108 +#define __NR_olduname 109 +#define __NR_iopl 110 +#define __NR_vhangup 111 +#define __NR_idle 112 +#define __NR_vm86old 113 +#define __NR_wait4 114 +#define __NR_swapoff 115 +#define __NR_sysinfo 116 +#define __NR_ipc 117 +#define __NR_fsync 118 +#define __NR_sigreturn 119 +#define __NR_clone 120 +#define __NR_setdomainname 121 +#define __NR_uname 122 +#define __NR_modify_ldt 123 +#define __NR_adjtimex 124 +#define __NR_mprotect 125 +#define __NR_sigprocmask 126 +#define __NR_create_module 127 +#define __NR_init_module 128 +#define __NR_delete_module 129 +#define __NR_get_kernel_syms 130 +#define __NR_quotactl 131 +#define __NR_getpgid 132 +#define __NR_fchdir 133 +#define __NR_bdflush 134 +#define __NR_sysfs 135 +#define __NR_personality 136 +#define __NR_afs_syscall 137 /* Syscall for Andrew File System */ +#define __NR_setfsuid 138 +#define __NR_setfsgid 139 +#define __NR__llseek 140 +#define __NR_getdents 141 +#define __NR__newselect 142 +#define __NR_flock 143 +#define __NR_msync 144 +#define __NR_readv 145 +#define __NR_writev 146 +#define __NR_getsid 147 +#define __NR_fdatasync 148 +#define __NR__sysctl 149 +#define __NR_mlock 150 +#define __NR_munlock 151 +#define __NR_mlockall 152 +#define __NR_munlockall 153 +#define __NR_sched_setparam 154 +#define __NR_sched_getparam 155 +#define __NR_sched_setscheduler 156 +#define __NR_sched_getscheduler 157 +#define __NR_sched_yield 158 +#define __NR_sched_get_priority_max 159 +#define __NR_sched_get_priority_min 160 +#define __NR_sched_rr_get_interval 161 +#define __NR_nanosleep 162 +#define __NR_mremap 163 +#define __NR_setresuid 164 +#define __NR_getresuid 165 +#define __NR_vm86 166 +#define __NR_query_module 167 +#define __NR_poll 168 +#define __NR_nfsservctl 169 +#define __NR_setresgid 170 +#define __NR_getresgid 171 +#define __NR_prctl 172 +#define __NR_rt_sigreturn 173 +#define __NR_rt_sigaction 174 +#define __NR_rt_sigprocmask 175 +#define __NR_rt_sigpending 176 +#define __NR_rt_sigtimedwait 177 +#define __NR_rt_sigqueueinfo 178 +#define __NR_rt_sigsuspend 179 +#define __NR_pread64 180 +#define __NR_pwrite64 181 +#define __NR_chown 182 +#define __NR_getcwd 183 +#define __NR_capget 184 +#define __NR_capset 185 +#define __NR_sigaltstack 186 +#define __NR_sendfile 187 +#define __NR_streams1 188 /* some people actually want it */ +#define __NR_streams2 189 /* some people actually want it */ +#define __NR_vfork 190 +#define __NR_ugetrlimit 191 /* SuS compliant getrlimit */ +#define __NR_mmap2 192 +#define __NR_truncate64 193 +#define __NR_ftruncate64 194 +#define __NR_stat64 195 +#define __NR_lstat64 196 +#define __NR_fstat64 197 +#define __NR_lchown32 198 +#define __NR_getuid32 199 +#define __NR_getgid32 200 +#define __NR_geteuid32 201 +#define __NR_getegid32 202 +#define __NR_setreuid32 203 +#define __NR_setregid32 204 +#define __NR_getgroups32 205 +#define __NR_setgroups32 206 +#define __NR_fchown32 207 +#define __NR_setresuid32 208 +#define __NR_getresuid32 209 +#define __NR_setresgid32 210 +#define __NR_getresgid32 211 +#define __NR_chown32 212 +#define __NR_setuid32 213 +#define __NR_setgid32 214 +#define __NR_setfsuid32 215 +#define __NR_setfsgid32 216 +#define __NR_pivot_root 217 +#define __NR_mincore 218 +#define __NR_madvise 219 +#define __NR_getdents64 220 +#define __NR_fcntl64 221 +/* 223 is unused */ +#define __NR_gettid 224 +#define __NR_setxattr 226 +#define __NR_lsetxattr 227 +#define __NR_fsetxattr 228 +#define __NR_getxattr 229 +#define __NR_lgetxattr 230 +#define __NR_fgetxattr 231 +#define __NR_listxattr 232 +#define __NR_llistxattr 233 +#define __NR_flistxattr 234 +#define __NR_removexattr 235 +#define __NR_lremovexattr 236 +#define __NR_fremovexattr 237 +#define __NR_tkill 238 +#define __NR_sendfile64 239 +#define __NR_futex 240 +#define __NR_sched_setaffinity 241 +#define __NR_sched_getaffinity 242 +#define __NR_set_thread_area 243 +#define __NR_get_thread_area 244 +#define __NR_io_setup 245 +#define __NR_io_destroy 246 +#define __NR_io_getevents 247 +#define __NR_io_submit 248 +#define __NR_io_cancel 249 +#define __NR_fadvise64 250 + +#define __NR_exit_group 252 +#define __NR_lookup_dcookie 253 +#define __NR_epoll_create 254 +#define __NR_epoll_ctl 255 +#define __NR_epoll_wait 256 +#define __NR_remap_file_pages 257 +#define __NR_set_tid_address 258 +#define __NR_timer_create 259 +#define __NR_timer_settime (__NR_timer_create+1) +#define __NR_timer_gettime (__NR_timer_create+2) +#define __NR_timer_getoverrun (__NR_timer_create+3) +#define __NR_timer_delete (__NR_timer_create+4) +#define __NR_clock_settime (__NR_timer_create+5) +#define __NR_clock_gettime (__NR_timer_create+6) +#define __NR_clock_getres (__NR_timer_create+7) +#define __NR_clock_nanosleep (__NR_timer_create+8) +#define __NR_statfs64 268 +#define __NR_fstatfs64 269 +#define __NR_tgkill 270 +#define __NR_utimes 271 +#define __NR_fadvise64_64 272 +#define __NR_vserver 273 +#define __NR_mbind 274 +#define __NR_get_mempolicy 275 +#define __NR_set_mempolicy 276 +#define __NR_mq_open 277 +#define __NR_mq_unlink (__NR_mq_open+1) +#define __NR_mq_timedsend (__NR_mq_open+2) +#define __NR_mq_timedreceive (__NR_mq_open+3) +#define __NR_mq_notify (__NR_mq_open+4) +#define __NR_mq_getsetattr (__NR_mq_open+5) +#define __NR_sys_kexec_load 283 +#define __NR_waitid 284 +#define __NR_add_key 285 +#define __NR_request_key 286 +#define __NR_keyctl 287 + +#define NR_syscalls 288 + +/* user-visible error numbers are in the range -1 - -124: see <asm-sh/errno.h> */ + +#define __syscall_return(type, res) \ +do { \ + if ((unsigned long)(res) >= (unsigned long)(-124)) { \ + /* Avoid using "res" which is declared to be in register r0; \ + errno might expand to a function call and clobber it. */ \ + int __err = -(res); \ + errno = __err; \ + res = -1; \ + } \ + return (type) (res); \ +} while (0) + +/* XXX - _foo needs to be __foo, while __NR_bar could be _NR_bar. */ +#define _syscall0(type,name) \ +type name(void) \ +{ \ +register long __sc0 __asm__ ("r3") = __NR_##name; \ +__asm__ __volatile__ ("trapa #0x10" \ + : "=z" (__sc0) \ + : "0" (__sc0) \ + : "memory" ); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall1(type,name,type1,arg1) \ +type name(type1 arg1) \ +{ \ +register long __sc0 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +__asm__ __volatile__ ("trapa #0x11" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4) \ + : "memory"); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall2(type,name,type1,arg1,type2,arg2) \ +type name(type1 arg1,type2 arg2) \ +{ \ +register long __sc0 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +register long __sc5 __asm__ ("r5") = (long) arg2; \ +__asm__ __volatile__ ("trapa #0x12" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4), "r" (__sc5) \ + : "memory"); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \ +type name(type1 arg1,type2 arg2,type3 arg3) \ +{ \ +register long __sc0 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +register long __sc5 __asm__ ("r5") = (long) arg2; \ +register long __sc6 __asm__ ("r6") = (long) arg3; \ +__asm__ __volatile__ ("trapa #0x13" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6) \ + : "memory"); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4) \ +{ \ +register long __sc0 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +register long __sc5 __asm__ ("r5") = (long) arg2; \ +register long __sc6 __asm__ ("r6") = (long) arg3; \ +register long __sc7 __asm__ ("r7") = (long) arg4; \ +__asm__ __volatile__ ("trapa #0x14" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), \ + "r" (__sc7) \ + : "memory" ); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \ +{ \ +register long __sc3 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +register long __sc5 __asm__ ("r5") = (long) arg2; \ +register long __sc6 __asm__ ("r6") = (long) arg3; \ +register long __sc7 __asm__ ("r7") = (long) arg4; \ +register long __sc0 __asm__ ("r0") = (long) arg5; \ +__asm__ __volatile__ ("trapa #0x15" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ + "r" (__sc3) \ + : "memory" ); \ +__syscall_return(type,__sc0); \ +} + +#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \ +type name (type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \ +{ \ +register long __sc3 __asm__ ("r3") = __NR_##name; \ +register long __sc4 __asm__ ("r4") = (long) arg1; \ +register long __sc5 __asm__ ("r5") = (long) arg2; \ +register long __sc6 __asm__ ("r6") = (long) arg3; \ +register long __sc7 __asm__ ("r7") = (long) arg4; \ +register long __sc0 __asm__ ("r0") = (long) arg5; \ +register long __sc1 __asm__ ("r1") = (long) arg6; \ +__asm__ __volatile__ ("trapa #0x15" \ + : "=z" (__sc0) \ + : "0" (__sc0), "r" (__sc4), "r" (__sc5), "r" (__sc6), "r" (__sc7), \ + "r" (__sc3), "r" (__sc1) \ + : "memory" ); \ +__syscall_return(type,__sc0); \ +} + +#ifdef __KERNEL__ +#define __ARCH_WANT_IPC_PARSE_VERSION +#define __ARCH_WANT_OLD_READDIR +#define __ARCH_WANT_OLD_STAT +#define __ARCH_WANT_STAT64 +#define __ARCH_WANT_SYS_ALARM +#define __ARCH_WANT_SYS_GETHOSTNAME +#define __ARCH_WANT_SYS_PAUSE +#define __ARCH_WANT_SYS_SGETMASK +#define __ARCH_WANT_SYS_SIGNAL +#define __ARCH_WANT_SYS_TIME +#define __ARCH_WANT_SYS_UTIME +#define __ARCH_WANT_SYS_WAITPID +#define __ARCH_WANT_SYS_SOCKETCALL +#define __ARCH_WANT_SYS_FADVISE64 +#define __ARCH_WANT_SYS_GETPGRP +#define __ARCH_WANT_SYS_LLSEEK +#define __ARCH_WANT_SYS_NICE +#define __ARCH_WANT_SYS_OLD_GETRLIMIT +#define __ARCH_WANT_SYS_OLDUMOUNT +#define __ARCH_WANT_SYS_SIGPENDING +#define __ARCH_WANT_SYS_SIGPROCMASK +#define __ARCH_WANT_SYS_RT_SIGACTION +#endif + +#ifdef __KERNEL_SYSCALLS__ + +#include <linux/compiler.h> +#include <linux/types.h> +#include <linux/linkage.h> +#include <asm/ptrace.h> + +/* + * we need this inline - forking from kernel space will result + * in NO COPY ON WRITE (!!!), until an execve is executed. This + * is no problem, but for the stack. This is handled by not letting + * main() use the stack at all after fork(). Thus, no function + * calls - which means inline code for fork too, as otherwise we + * would use the stack upon exit from 'fork()'. + * + * Actually only pause and fork are needed inline, so that there + * won't be any messing with the stack from main(), but we define + * some others too. + */ +#define __NR__exit __NR_exit +static __inline__ _syscall0(int,pause) +static __inline__ _syscall0(int,sync) +static __inline__ _syscall0(pid_t,setsid) +static __inline__ _syscall3(int,write,int,fd,const char *,buf,off_t,count) +static __inline__ _syscall3(int,read,int,fd,char *,buf,off_t,count) +static __inline__ _syscall3(off_t,lseek,int,fd,off_t,offset,int,count) +static __inline__ _syscall1(int,dup,int,fd) +static __inline__ _syscall3(int,execve,const char *,file,char **,argv,char **,envp) +static __inline__ _syscall3(int,open,const char *,file,int,flag,int,mode) +static __inline__ _syscall1(int,close,int,fd) +static __inline__ _syscall3(pid_t,waitpid,pid_t,pid,int *,wait_stat,int,options) +static __inline__ _syscall1(int,delete_module,const char *,name) + +static __inline__ pid_t wait(int * wait_stat) +{ + return waitpid(-1,wait_stat,0); +} + +asmlinkage long sys_mmap2( + unsigned long addr, unsigned long len, + unsigned long prot, unsigned long flags, + unsigned long fd, unsigned long pgoff); +asmlinkage int sys_execve(char *ufilename, char **uargv, + char **uenvp, unsigned long r7, + struct pt_regs regs); +asmlinkage int sys_clone(unsigned long clone_flags, unsigned long newsp, + unsigned long parent_tidptr, + unsigned long child_tidptr, + struct pt_regs regs); +asmlinkage int sys_fork(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs regs); +asmlinkage int sys_vfork(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs regs); +asmlinkage int sys_pipe(unsigned long r4, unsigned long r5, + unsigned long r6, unsigned long r7, + struct pt_regs regs); +asmlinkage int sys_ptrace(long request, long pid, long addr, long data); +asmlinkage ssize_t sys_pread_wrapper(unsigned int fd, char *buf, + size_t count, long dummy, loff_t pos); +asmlinkage ssize_t sys_pwrite_wrapper(unsigned int fd, const char *buf, + size_t count, long dummy, loff_t pos); +struct sigaction; +asmlinkage long sys_rt_sigaction(int sig, + const struct sigaction __user *act, + struct sigaction __user *oact, + size_t sigsetsize); + +#endif + +/* + * "Conditional" syscalls + * + * What we want is __attribute__((weak,alias("sys_ni_syscall"))), + * but it doesn't work on all toolchains, so we just do it by hand + */ +#ifndef cond_syscall +#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall") +#endif + +#endif /* __ASM_SH_UNISTD_H */ diff --git a/include/asm-sh/user.h b/include/asm-sh/user.h new file mode 100644 index 0000000..d1b8511 --- /dev/null +++ b/include/asm-sh/user.h @@ -0,0 +1,60 @@ +#ifndef __ASM_SH_USER_H +#define __ASM_SH_USER_H + +#include <asm/ptrace.h> +#include <asm/page.h> + +/* + * Core file format: The core file is written in such a way that gdb + * can understand it and provide useful information to the user (under + * linux we use the `trad-core' bfd). The file contents are as follows: + * + * upage: 1 page consisting of a user struct that tells gdb + * what is present in the file. Directly after this is a + * copy of the task_struct, which is currently not used by gdb, + * but it may come in handy at some point. All of the registers + * are stored as part of the upage. The upage should always be + * only one page long. + * data: The data segment follows next. We use current->end_text to + * current->brk to pick up all of the user variables, plus any memory + * that may have been sbrk'ed. No attempt is made to determine if a + * page is demand-zero or if a page is totally unused, we just cover + * the entire range. All of the addresses are rounded in such a way + * that an integral number of pages is written. + * stack: We need the stack information in order to get a meaningful + * backtrace. We need to write the data from usp to + * current->start_stack, so we round each of these in order to be able + * to write an integer number of pages. + */ + +struct user_fpu_struct { + unsigned long fp_regs[16]; + unsigned long xfp_regs[16]; + unsigned long fpscr; + unsigned long fpul; +}; + +struct user { + struct pt_regs regs; /* entire machine state */ + struct user_fpu_struct fpu; /* Math Co-processor registers */ + int u_fpvalid; /* True if math co-processor being used */ + size_t u_tsize; /* text size (pages) */ + size_t u_dsize; /* data size (pages) */ + size_t u_ssize; /* stack size (pages) */ + unsigned long start_code; /* text starting address */ + unsigned long start_data; /* data starting address */ + unsigned long start_stack; /* stack starting address */ + long int signal; /* signal causing core dump */ + struct regs * u_ar0; /* help gdb find registers */ + struct user_fpu_struct* u_fpstate; /* Math Co-processor pointer */ + unsigned long magic; /* identifies a core file */ + char u_comm[32]; /* user command name */ +}; + +#define NBPG PAGE_SIZE +#define UPAGES 1 +#define HOST_TEXT_START_ADDR (u.start_code) +#define HOST_DATA_START_ADDR (u.start_data) +#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG) + +#endif /* __ASM_SH_USER_H */ diff --git a/include/asm-sh/watchdog.h b/include/asm-sh/watchdog.h new file mode 100644 index 0000000..f0cf4be --- /dev/null +++ b/include/asm-sh/watchdog.h @@ -0,0 +1,111 @@ +/* + * include/asm-sh/watchdog.h + * + * Copyright (C) 2002, 2003 Paul Mundt + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __ASM_SH_WATCHDOG_H +#define __ASM_SH_WATCHDOG_H +#ifdef __KERNEL__ + +#include <linux/types.h> +#include <linux/config.h> +#include <asm/cpu/watchdog.h> +#include <asm/io.h> + +/* + * See asm/cpu-sh2/watchdog.h for explanation of this stupidity.. + */ +#ifndef WTCNT_R +# define WTCNT_R WTCNT +#endif + +#ifndef WTCSR_R +# define WTCSR_R WTCSR +#endif + +#define WTCNT_HIGH 0x5a +#define WTCSR_HIGH 0xa5 + +#define WTCSR_CKS2 0x04 +#define WTCSR_CKS1 0x02 +#define WTCSR_CKS0 0x01 + +/* + * CKS0-2 supports a number of clock division ratios. At the time the watchdog + * is enabled, it defaults to a 41 usec overflow period .. we overload this to + * something a little more reasonable, and really can't deal with anything + * lower than WTCSR_CKS_1024, else we drop back into the usec range. + * + * Clock Division Ratio Overflow Period + * -------------------------------------------- + * 1/32 (initial value) 41 usecs + * 1/64 82 usecs + * 1/128 164 usecs + * 1/256 328 usecs + * 1/512 656 usecs + * 1/1024 1.31 msecs + * 1/2048 2.62 msecs + * 1/4096 5.25 msecs + */ +#define WTCSR_CKS_32 0x00 +#define WTCSR_CKS_64 0x01 +#define WTCSR_CKS_128 0x02 +#define WTCSR_CKS_256 0x03 +#define WTCSR_CKS_512 0x04 +#define WTCSR_CKS_1024 0x05 +#define WTCSR_CKS_2048 0x06 +#define WTCSR_CKS_4096 0x07 + +/** + * sh_wdt_read_cnt - Read from Counter + * + * Reads back the WTCNT value. + */ +static inline __u8 sh_wdt_read_cnt(void) +{ + return ctrl_inb(WTCNT_R); +} + +/** + * sh_wdt_write_cnt - Write to Counter + * + * @val: Value to write + * + * Writes the given value @val to the lower byte of the timer counter. + * The upper byte is set manually on each write. + */ +static inline void sh_wdt_write_cnt(__u8 val) +{ + ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT); +} + +/** + * sh_wdt_read_csr - Read from Control/Status Register + * + * Reads back the WTCSR value. + */ +static inline __u8 sh_wdt_read_csr(void) +{ + return ctrl_inb(WTCSR_R); +} + +/** + * sh_wdt_write_csr - Write to Control/Status Register + * + * @val: Value to write + * + * Writes the given value @val to the lower byte of the control/status + * register. The upper byte is set manually on each write. + */ +static inline void sh_wdt_write_csr(__u8 val) +{ + ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR); +} + +#endif /* __KERNEL__ */ +#endif /* __ASM_SH_WATCHDOG_H */ diff --git a/include/asm-sh/xor.h b/include/asm-sh/xor.h new file mode 100644 index 0000000..c82eb12 --- /dev/null +++ b/include/asm-sh/xor.h @@ -0,0 +1 @@ +#include <asm-generic/xor.h> |
