diff options
Diffstat (limited to 'include/asm-ppc')
| -rw-r--r-- | include/asm-ppc/cpm2.h | 5 | ||||
| -rw-r--r-- | include/asm-ppc/dma-mapping.h | 2 | ||||
| -rw-r--r-- | include/asm-ppc/ibm44x.h | 34 | ||||
| -rw-r--r-- | include/asm-ppc/ibm4xx.h | 4 | ||||
| -rw-r--r-- | include/asm-ppc/ibm_ocp.h | 12 | ||||
| -rw-r--r-- | include/asm-ppc/mpc10x.h | 3 | ||||
| -rw-r--r-- | include/asm-ppc/pci.h | 4 | ||||
| -rw-r--r-- | include/asm-ppc/pgtable.h | 52 | ||||
| -rw-r--r-- | include/asm-ppc/ppc_asm.h | 6 | ||||
| -rw-r--r-- | include/asm-ppc/unistd.h | 5 |
10 files changed, 115 insertions, 12 deletions
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h index c5883db..9483d4b 100644 --- a/include/asm-ppc/cpm2.h +++ b/include/asm-ppc/cpm2.h @@ -109,6 +109,7 @@ static inline long IS_DPERR(const uint offset) * and dual port ram. */ extern cpm_cpm2_t *cpmp; /* Pointer to comm processor */ + extern uint cpm_dpalloc(uint size, uint align); extern int cpm_dpfree(uint offset); extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align); @@ -116,6 +117,8 @@ extern void cpm_dpdump(void); extern void *cpm_dpram_addr(uint offset); extern void cpm_setbrg(uint brg, uint rate); extern void cpm2_fastbrg(uint brg, uint rate, int div16); +extern void cpm2_reset(void); + /* Buffer descriptors used by many of the CPM protocols. */ @@ -1087,5 +1090,3 @@ typedef struct im_idma { #endif /* __CPM2__ */ #endif /* __KERNEL__ */ - - diff --git a/include/asm-ppc/dma-mapping.h b/include/asm-ppc/dma-mapping.h index 7f0487a..6f74f59 100644 --- a/include/asm-ppc/dma-mapping.h +++ b/include/asm-ppc/dma-mapping.h @@ -117,7 +117,7 @@ dma_map_page(struct device *dev, struct page *page, __dma_sync_page(page, offset, size, direction); - return (page - mem_map) * PAGE_SIZE + PCI_DRAM_OFFSET + offset; + return page_to_bus(page) + offset; } /* We do nothing. */ diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index 87f0511..21e41c9 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h @@ -35,8 +35,10 @@ #define PPC44x_LOW_SLOT 63 /* LS 32-bits of UART0 physical address location for early serial text debug */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define UART0_PHYS_IO_BASE 0xf0000200 +#elif defined(CONFIG_440EP) +#define UART0_PHYS_IO_BASE 0xe0000000 #else #define UART0_PHYS_IO_BASE 0x40000200 #endif @@ -49,11 +51,16 @@ /* * Standard 4GB "page" definitions */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define PPC44x_IO_PAGE 0x0000000100000000ULL #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL +#elif defined(CONFIG_440EP) +#define PPC44x_IO_PAGE 0x0000000000000000ULL +#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL +#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE +#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL #else #define PPC44x_IO_PAGE 0x0000000100000000ULL #define PPC44x_PCICFG_PAGE 0x0000000200000000ULL @@ -64,7 +71,7 @@ /* * 36-bit trap ranges */ -#ifdef CONFIG_440SP +#if defined(CONFIG_440SP) #define PPC44x_IO_LO 0xf0000000UL #define PPC44x_IO_HI 0xf0000fffUL #define PPC44x_PCI0CFG_LO 0x0ec00000UL @@ -75,6 +82,13 @@ #define PPC44x_PCI2CFG_HI 0x2ec00007UL #define PPC44x_PCIMEM_LO 0x80000000UL #define PPC44x_PCIMEM_HI 0xdfffffffUL +#elif defined(CONFIG_440EP) +#define PPC44x_IO_LO 0xef500000UL +#define PPC44x_IO_HI 0xefffffffUL +#define PPC44x_PCI0CFG_LO 0xeec00000UL +#define PPC44x_PCI0CFG_HI 0xeecfffffUL +#define PPC44x_PCIMEM_LO 0xa0000000UL +#define PPC44x_PCIMEM_HI 0xdfffffffUL #else #define PPC44x_IO_LO 0x40000000UL #define PPC44x_IO_HI 0x40000fffUL @@ -152,6 +166,12 @@ #define DCRN_SDR_UART0 0x0120 #define DCRN_SDR_UART1 0x0121 +#ifdef CONFIG_440EP +#define DCRN_SDR_UART2 0x0122 +#define DCRN_SDR_UART3 0x0123 +#define DCRN_SDR_CUST0 0x4000 +#endif + /* SDR read/write helper macros */ #define SDR_READ(offset) ({\ mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ @@ -169,6 +189,14 @@ #define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ #define DCRN_MAL_BASE 0x180 +#ifdef CONFIG_440EP +#define DCRN_DMA2P40_BASE 0x300 +#define DCRN_DMA2P41_BASE 0x308 +#define DCRN_DMA2P42_BASE 0x310 +#define DCRN_DMA2P43_BASE 0x318 +#define DCRN_DMA2P4SR_BASE 0x320 +#endif + /* UIC */ #define DCRN_UIC0_BASE 0xc0 #define DCRN_UIC1_BASE 0xd0 diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h index 35260af..e807be9 100644 --- a/include/asm-ppc/ibm4xx.h +++ b/include/asm-ppc/ibm4xx.h @@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5, #elif CONFIG_44x +#if defined(CONFIG_BAMBOO) +#include <platforms/4xx/bamboo.h> +#endif + #if defined(CONFIG_EBONY) #include <platforms/4xx/ebony.h> #endif diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h index 8c61d93..3f7b566 100644 --- a/include/asm-ppc/ibm_ocp.h +++ b/include/asm-ppc/ibm_ocp.h @@ -71,6 +71,8 @@ struct ocp_func_emac_data { /* Sysfs support */ #define OCP_SYSFS_EMAC_DATA() \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ @@ -78,9 +80,14 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \ +OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \ \ void ocp_show_emac_data(struct device *dev) \ { \ + device_create_file(dev, &dev_attr_emac_rgmii_idx); \ + device_create_file(dev, &dev_attr_emac_rgmii_mux); \ device_create_file(dev, &dev_attr_emac_zmii_idx); \ device_create_file(dev, &dev_attr_emac_zmii_mux); \ device_create_file(dev, &dev_attr_emac_mal_idx); \ @@ -88,6 +95,9 @@ void ocp_show_emac_data(struct device *dev) \ device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ device_create_file(dev, &dev_attr_emac_wol_irq); \ device_create_file(dev, &dev_attr_emac_mdio_idx); \ + device_create_file(dev, &dev_attr_emac_tah_idx); \ + device_create_file(dev, &dev_attr_emac_phy_mode); \ + device_create_file(dev, &dev_attr_emac_phy_map); \ } #ifdef CONFIG_40x @@ -157,7 +167,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \ \ void ocp_show_iic_data(struct device *dev) \ { \ - device_create_file(dev, &dev_attr_iic_fast_mode); \ + device_create_file(dev, &dev_attr_iic_fast_mode); \ } #endif /* __IBM_OCP_H__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h index f5196a4..77b1e09 100644 --- a/include/asm-ppc/mpc10x.h +++ b/include/asm-ppc/mpc10x.h @@ -163,7 +163,8 @@ enum ppc_sys_devices { MPC10X_IIC1, MPC10X_DMA0, MPC10X_DMA1, - MPC10X_DUART, + MPC10X_UART0, + MPC10X_UART1, }; int mpc10x_bridge_init(struct pci_controller *hose, diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index a13d558..a811e44 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -105,6 +105,10 @@ extern void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, struct resource *res); +extern void +pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res, + struct pci_bus_region *region); + extern void pcibios_add_platform_entries(struct pci_dev *dev); struct file; diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 4d4b20c..92f30b2 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base; * * Note that these bits preclude future use of a page size * less than 4KB. + * + * + * PPC 440 core has following TLB attribute fields; + * + * TLB1: + * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + * RPN................................. - - - - - - ERPN....... + * + * TLB2: + * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR + * + * There are some constrains and options, to decide mapping software bits + * into TLB entry. + * + * - PRESENT *must* be in the bottom three bits because swap cache + * entries use the top 29 bits for TLB2. + * + * - FILE *must* be in the bottom three bits because swap cache + * entries use the top 29 bits for TLB2. + * + * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it + * doesn't support SMP. So we can use this as software bit, like + * DIRTY. + * + * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used + * for memory protection related functions (see PTE structure in + * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the + * above bits. Note that the bit values are CPU specific, not architecture + * specific. + * + * The kernel PTE entry holds an arch-dependent swp_entry structure under + * certain situations. In other words, in such situations some portion of + * the PTE bits are used as a swp_entry. In the PPC implementation, the + * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still + * hold protection values. That means the three protection bits are + * reserved for both PTE and SWAP entry at the most significant three + * LSBs. + * + * There are three protection bits available for SWAP entry: + * _PAGE_PRESENT + * _PAGE_FILE + * _PAGE_HASHPTE (if HW has) + * + * So those three bits have to be inside of 0-2nd LSB of PTE. + * */ + #define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ #define _PAGE_RW 0x00000002 /* S: Write permission */ -#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ +#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */ #define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ #define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ #define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ #define _PAGE_USER 0x00000040 /* S: User page */ #define _PAGE_ENDIAN 0x00000080 /* H: E bit */ #define _PAGE_GUARDED 0x00000100 /* H: G bit */ -#define _PAGE_COHERENT 0x00000200 /* H: M bit */ -#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */ +#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */ #define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ #define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h index f76221d..bb53e2d 100644 --- a/include/asm-ppc/ppc_asm.h +++ b/include/asm-ppc/ppc_asm.h @@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #define PPC405_ERR77_SYNC #endif +#ifdef CONFIG_IBM440EP_ERR42 +#define PPC440EP_ERR42 isync +#else +#define PPC440EP_ERR42 +#endif + /* The boring bits... */ /* Condition Register Bit Fields */ diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h index a7894e0..3173ab3 100644 --- a/include/asm-ppc/unistd.h +++ b/include/asm-ppc/unistd.h @@ -279,8 +279,11 @@ #define __NR_waitid 272 #define __NR_ioprio_set 273 #define __NR_ioprio_get 274 +#define __NR_inotify_init 275 +#define __NR_inotify_add_watch 276 +#define __NR_inotify_rm_watch 277 -#define __NR_syscalls 275 +#define __NR_syscalls 278 #define __NR(n) #n |
